KR20050061077A - Method for forming dielectric layer in semiconductor device - Google Patents

Abstract

In a semiconductor manufacturing process, a method of forming a dielectric film is disclosed. On the silicon substrate, a first gate dielectric film is formed to prevent reaction with silicon. The first gate dielectric layer is nitrided in a nitrogen atmosphere. A high-k dielectric material is deposited on the nitrided first gate dielectric layer to form a second gate dielectric layer. The dielectric film has improved thermal stability and reduced interface trap density. In addition, the gate dielectric layer may prevent diffusion of the dopant from the gate electrode to the channel region.

Description

Method for forming dielectric layer in semiconductor device

The present invention relates to a method for producing a dielectric film. More particularly, the present invention relates to a method of manufacturing a dielectric film used for a gate and a capacitor.

Recent semiconductor devices are designed to provide high integration and high performance, and in particular, dielectric films used for MOS transistors and capacitors are formed as thin as possible. This is because the driving current of the MOS transistor increases as the thickness of the gate dielectric film of the MOS transistor decreases, and the storage capacitance increases as the thickness of the dielectric film of the capacitor decreases. Therefore, in order to improve the performance of the device, it is increasingly important to form a dielectric film that is not only extremely thin but also reliable and has few defects.

Conventionally, a silicon oxide film has been used as the gate dielectric film. This is because the process is simple and very stable since the silicon substrate is formed by oxidizing. However, since the silicon oxide film has a low dielectric constant of about 3.9, there is a limit in reducing the thickness of the gate dielectric film made of the silicon oxide film. In addition, in the case where the gate dielectric layer is formed very thin using the silicon oxide layer, a tunnel current flows through the gate dielectric layer, thereby increasing leakage current.

Accordingly, a method of forming the gate dielectric layer using a high dielectric material has been developed. When the gate dielectric layer is formed of a high dielectric material, the same capacitance as that of the silicon oxide may be obtained while being formed thicker than that of the silicon oxide. Accordingly, metal oxides having a higher dielectric constant than silicon oxide have been proposed as alternative dielectric materials for gate dielectric films or capacitor dielectric films.

However, when depositing a metal oxide having a high dielectric constant on the silicon substrate, it easily reacts with the silicon substrate to increase the interface trap density and thus rapidly increase the leakage current.

In addition, the silicon substrate surface easily reacts with the high dielectric metal oxide or is easily oxidized during the deposition or subsequent thermal process of the high dielectric metal oxide. Thus, a boundary film such as a silicon oxide film is formed between the silicon substrate and the metal oxide film. As a result, the equivalent oxide film (EOT) thickness is increased to deteriorate the performance of the device.

In addition, when polysilicon is used as the gate electrode, dopants in the polysilicon are diffused, thereby degrading the characteristics of the transistor.

Various attempts have been made to solve the above problems. For example, Japanese Patent Laid-Open No. 2000-22139 discloses a technique of forming a gate insulating film including a silicon oxide film layer, a silicon nitride film, and a tantalum oxide film on a silicon substrate. However, these methods are not successful in solving the above problems. For example, a silicon nitride film interposed between the high dielectric film and the silicon substrate or between the high dielectric film and the polysilicon gate electrode causes trapping of charge with a high interface state density.

Accordingly, it is a first object of the present invention to provide a gate dielectric film in which thermal stability is increased and leakage current is reduced.

It is a second object of the present invention to provide a capacitor dielectric film in which thermal stability is increased and leakage current is reduced.

In order to achieve the first object described above, the present invention forms a first gate dielectric film on the silicon substrate to prevent reaction with silicon. The first gate dielectric layer is nitrided in a nitrogen atmosphere. A high-k dielectric material is deposited on the nitrided first gate dielectric layer to form a second gate dielectric layer.

In order to achieve the above second object, the present invention forms a lower electrode on a silicon substrate. A first capacitor dielectric layer is formed on the lower electrode to prevent a reaction with the lower electrode. The first capacitor dielectric layer is nitrided in a nitrogen atmosphere. A high dielectric material is deposited on the nitrided first capacitor dielectric layer to form a second capacitor dielectric layer. Subsequently, an upper electrode is formed on the second capacitor dielectric layer.

The dielectric film formed by this method has improved thermal stability and reduced interface trap density. In addition, the gate dielectric layer may prevent diffusion of the dopant from the gate electrode to the channel region.

Hereinafter, the present invention will be described in more detail.

On the silicon substrate, a first gate dielectric film is formed as a reaction prevention film for preventing a reaction between silicon and a high dielectric material formed by a subsequent process.

The first gate dielectric layer may be formed of a silicon oxide layer (SiO ₂ ), but may be formed of aluminum oxide (Al 2 O 3), yttrium oxide (Y 2 O 3), magnesium oxide (MgO), or strontium oxide (Al 2 O 3), which is a material having a higher dielectric constant than the silicon oxide layer. (SrO), a titanium oxide film (TiO2), a lanthanum oxide film (La ₂ O ₃ ) or a tantalum oxide film (TaO5) is more preferable. Alternatively, at least one of the aluminum oxide (Al ₂ O ₃ ), yttrium oxide (Y ₂ O ₃ ), magnesium oxide (MgO), strontium oxide (SrO), titanium oxide (TiO 2), lanthanum oxide (La ₂ O ₃ ), and tantalum oxide (TaO5). It can be formed of a silicate material comprising one material.

The first gate dielectric layer serves to improve an interface property by suppressing a reaction between the silicon substrate and a high dielectric material subsequently formed. That is, by forming the first gate dielectric layer, the interface trap density between the substrate and the dielectric layer is reduced. In addition, when the first gate dielectric layer is formed of a material having a higher dielectric constant than the silicon oxide layer, for example, aluminum oxide layer (Al 2 O 3), the equivalent oxide thickness of the entire dielectric layer may be minimized.

The first gate dielectric layer should be formed to a thin thickness of about 5 to about 30 Å. To this end, the first gate dielectric layer is most preferably formed by an atomic layer deposition method. When the first gate dielectric film is formed by an atomic layer deposition method, the thickness of the first gate dielectric film can be accurately controlled, and the process is performed at a lower temperature than that of a conventional deposition method (for example, a chemical vapor deposition method). There is an advantage to proceed.

Next, the first gate dielectric film is nitrided in a nitrogen atmosphere. The nitriding of the one gate dielectric layer is performed by maintaining a temperature of 100 to 1000 ° C. under a gas atmosphere including N ₂ , NH ₃ , N ₂ O, or NO. The nitriding step may be carried out in a furnace by a thermal method or by a plasma treatment. Nitriding by plasma treatment can be carried out within a short time of several seconds to several minutes, so the process is very simple. When the nitriding process is performed, nitrogen flows into the first gate dielectric layer, thereby changing characteristics of the first gate dielectric layer.

Specifically, the nitrided first gate dielectric layer has improved thermal stability. In addition, the nitrogen in the nitrided first gate dielectric layer may generate a fixed positive charge to offset the fixed negative charge in the high dielectric material formed by a subsequent process, thereby minimizing the flat band voltage shift of the finished dielectric layer.

 In the case of employing the nitrided first gate dielectric layer, even if a gate electrode is formed of the polysilicon layer in a subsequent process, diffusion of dopants included in the gate electrode into the substrate may be minimized.

Next, a high dielectric material is deposited on the nitrided first gate dielectric layer to form a second gate dielectric layer. The second gate dielectric layer includes an yttrium oxide layer (Y ₂ O ₃ ), a magnesium oxide layer (MgO), a strontium oxide layer (SrO), a titanium oxide layer (TiO ₂ ), a lanthanum oxide layer (La ₂ O ₃ ), and a tantalum oxide layer (Ta ₂ O). _5), hafnium oxide (HfO _2), zirconium oxide (ZrO _2), it may form a strontium titanium oxide (SrTiO _3), barium strontium oxide (BaSrO ₃₎ or barium titanium oxide (BaTiO _3). In addition, the second gate dielectric layer may be formed of a silicate material including at least one of the materials. Preferably, the second gate dielectric layer is formed as a film having a dielectric constant equal to or greater than that of the first gate dielectric layer. This is to reduce the equivalent oxide film thickness of the entire dielectric film including the first and second gate dielectric films so that the equivalent oxide film thickness does not increase even if the physical thickness of the entire dielectric film is increased.

The second gate dielectric layer should be formed to a thin thickness of about 5 to about 30 Å. To this end, the first gate dielectric layer is most preferably formed by an atomic layer deposition method. When the first gate dielectric film is formed by an atomic layer deposition method, the thickness of the second gate dielectric film can be accurately controlled, and the process is performed at a lower temperature than that of a conventional deposition method (for example, a chemical vapor deposition method). There is an advantage to proceed.

When the dielectric film structure is formed in this manner, the thermal stability is improved and the interface trap density is reduced. In addition, the gate dielectric layer may prevent diffusion of the dopant from the gate electrode to the channel region.

In the above description, the method of forming the gate dielectric film of the MOS transistor on the substrate has been described, but the same applies to the capacitor dielectric film.

1 is a cross-sectional view showing a capacitor dielectric film.

Specifically, the lower electrode 12 is formed on the silicon substrate 10. The lower electrode 12 is provided in a cylindrical shape and is made of polysilicon material. The lower electrode 12 is formed to contact the contact 11 connected to a predetermined portion of the silicon substrate 10.

A first capacitor dielectric layer is formed on the lower electrode 12 to prevent a reaction between the lower electrode 12 and the high dielectric material to be formed thereafter. The first capacitor dielectric layer may be formed of a silicon oxide layer (SiO 2), but may be formed of aluminum oxide (Al ₂ O ₃ ), yttrium oxide (Y ₂ O ₃ ), and magnesium oxide ( MgO), a strontium oxide film (SrO), a titanium oxide film (TiO ₂ ), a lanthanum oxide film (La ₂ O ₃ ), or a tantalum oxide film (TaO ₅ ) is more preferable. Alternatively, the aluminum oxide (Al ₂ O ₃ ), yttrium oxide (Y ₂ O ₃ ), magnesium oxide (MgO), strontium oxide (SrO), titanium oxide (TiO ₂ ), lanthanum oxide (La ₂ O ₃ ), The tantalum oxide layer TaO5 may be formed of a silicate material including at least one material.

The first capacitor dielectric layer is nitrided in a nitrogen atmosphere. The nitriding of the first capacitor dielectric layer is performed by maintaining a temperature of 100 to 1000 ° C. under a gas atmosphere including N ₂ , NH ₃ , N ₂ O, or NO. The nitriding process includes thermal nitriding or plasma nitriding.

A high dielectric material is deposited on the nitrided first capacitor dielectric layer 14 to form a second capacitor dielectric layer 16. The second capacitor dielectric layer 16 may include an yttrium oxide layer (Y ₂ O ₃ ), a magnesium oxide layer (MgO), a strontium oxide layer (SrO), a titanium oxide layer (TiO ₂ ), a lanthanum oxide layer (La ₂ O ₃ ), and a tantalum oxide layer ( Ta ₂ O _5), hafnium oxide (HfO _2), zirconium oxide (ZrO _2), may form a strontium titanium oxide (SrTiO _3), barium strontium oxide (BaSrO ₃₎ or barium titanium oxide (BaTiO _3). In addition, the second capacitor dielectric layer 16 may be formed of a silicate material including at least one of the materials.

An upper electrode 18 is formed on the second capacitor dielectric layer 16. The upper electrode 18 may be formed of metal or polysilicon.

Hereinafter, preferred embodiments of the present invention will be described in detail.

Example

2A to 2C are cross-sectional views illustrating a method of forming a dielectric film according to an embodiment of the present invention.

Referring to FIG. 2A, aluminum oxide films Al ₂ O ₃ and 102 are formed on the semiconductor substrate 100 as a reaction prevention film for preventing a reaction between silicon and a high dielectric film to be formed thereafter. It is more preferable to perform a cleaning process for removing the natural oxide film immediately before forming the aluminum oxide film 102. The aluminum oxide film 102 has a dielectric constant of about 10, which is higher than that of the silicon oxide film, and has excellent thermal stability, and thus is suitable as the reaction prevention film.

The aluminum oxide film 102 is preferably formed to a predetermined thickness to function as the reaction prevention film and to easily penetrate nitrogen during the subsequent nitriding process. Specifically, the aluminum oxide film 102 may be formed to a thickness of 5 kPa to 30 kPa, and in the present embodiment, a thickness of 20 kPa.

The aluminum oxide film 102 is formed by ALD deposition, which is easy to control the thickness and components in the film. Specifically, TMA (TriMethyl Aluminum, Al (CH ₃ ) ₃ ) is used as a metal precursor gas, and ozone (Ozone) as an oxidant. ) At a temperature between 350 ° C. and 500 ° C. using gas. At this time, the aluminum oxide film 102 is deposited at a rate at which about 0.07 nm is deposited during one cycle consisting of a metal precursor gas inlet, a first purge, an ozone gas inlet, and a second purge.

Referring to FIG. 2B, the aluminum oxide film 102 is nitrided in a nitrogen atmosphere. Specifically, the aluminum oxide film 102 is subjected to NH ₃ plasma treatment for about 40 seconds at a temperature of 750 to 850 ° C. By the plasma treatment, the thickness of the first gate dielectric layer is increased by about 10 [mu] s, and the capacitance density of the entire stacked layer is reduced.

The shift of the flat band voltage of the MOS transistor is changed depending on the process of nitriding the aluminum oxide film 102. That is, a positive fixed charge is generated in the nitrided aluminum oxide film 102a, and the fixed positive charge is offset by a fixed negative charge in the entire dielectric film including a high dielectric material that is subsequently formed. This is shown to have the effect of eliminating the flatband voltage shift.

Referring to FIG. 2C, a hafnium oxide film 104, which is a high dielectric material, is formed on the nitrided aluminum oxide film 102a. The hafnium oxide film 104 has a dielectric constant of 20 or more. The hafnium oxide film 104 may be formed at about 400 ° C. using hafnium tetrachloride as a metal source and using H ₂ O as an oxidizing agent. In addition, the hafnium oxide film 104 may be deposited to a thickness of about 0.5 GPa per cycle. The hafnium oxide film 104 is formed to a thickness of 30 to 50 GPa.

Thereafter, as the gate electrode film 106, a metal film or a polysilicon film is formed. However, since the hafnium oxide film 104 has a relatively low heat (heat of formation) required to react with other materials, the gate electrode film 106 is formed to minimize the reaction with the gate electrode film 106. It is desirable to form at low temperatures. For example, the gate electrode film 106 may be formed of platinum.

Subsequently, a post heat treatment process is performed on the resultant product. For example, the post-heat treatment process may include a source drain activation process after forming a gate electrode.

The electrical properties of the dielectric film formed by the method of the present invention were analyzed. That is, the difference in characteristics of the dielectric film according to the nitriding treatment was compared.

FIG. 3 is a graph showing capacitance equivalent thicknesses (CET) of the dielectric film formed by the embodiment of the present invention and the dielectric film formed by omitting the nitriding treatment. The capacitance equivalent thickness refers to an equivalent oxide thickness considering quantum mechanical effects due to electrons formed in a channel in a transistor.

That is, the dielectric film according to the embodiment of the present invention has a structure in which a nitrided aluminum oxide film / hafnium oxide film is laminated, and another dielectric film shown for comparison has a structure in which an aluminum nitride film / hafnium oxide film not nitrided is laminated. .

In Fig. 3,? Indicates the capacitance equivalent thickness of each dielectric film, and? Indicates the equivalent thickness of the capacitor after the heat treatment of each dielectric film in a nitrogen atmosphere at 800 占 폚.

Referring to FIG. 3, the dielectric equivalent thicknesses of the dielectric films were approximately 23 degrees before the 800 ° C. heat treatment regardless of the nitriding treatment. This means that nitriding the dielectric film does not increase the capacitance equivalent thickness of the dielectric film. However, after the deposited dielectric films were heat-treated in a nitrogen atmosphere at 800 ° C., the capacitance equivalent thickness of the dielectric film of the present invention was about 28 GPa, but the capacitance equivalent thickness of the dielectric film formed by omitting nitriding treatment was about 31 GPa. That is, it can be seen that the change in capacitance equivalent thickness due to the heat treatment of the dielectric film according to the method of the present invention is smaller. By nitriding the dielectric film, nitrogen is bonded to the lower dielectric film in the thin film to prevent mutual diffusion of the lower silicon substrate and the dielectric film, thereby improving thermal stability due to heat treatment.

4 is a graph showing a flat band voltage shift in the dielectric film formed by the embodiment of the present invention and the dielectric film formed by omitting the nitriding process.

In Fig. 4,? Indicates a flat band voltage shift of each dielectric film, and? Indicates a flat band voltage shift after heat treatment of each dielectric film in a nitrogen atmosphere at 800 占 폚.

Referring to FIG. 4, it can be seen that the dielectric film according to the embodiment of the present invention has a relatively low flat band voltage shift after the dielectric film is deposited and after the subsequent heat treatment of the dielectric film. When the shift of the flat band voltage is low, there is an effect that the leakage current is reduced. This means that charge generation is minimized. In particular, the dielectric film subjected to 800 ° C. heat treatment and nitriding treatment showed a value almost 0.1 V, which is almost identical to the ideal data. From these results, it can be seen that the negative fixed charge occurring at the Al ₂ O ₃ / SiO ₂ and Al ₂ O ₃ / Si interfaces can be reduced by appropriately adding nitrogen.

5 is a graph showing interface trap densities measured in the dielectric film formed by the embodiment of the present invention and the dielectric film formed by omitting nitriding treatment.

In Fig. 5,? Denotes the interface trap density of the dielectric film formed by the embodiment of the present invention, and? Denotes the interface trap density of the dielectric film formed by omitting the nitriding process.

Referring to FIG. 5, the dielectric film according to the embodiment of the present invention has an interface trap density of about 1/10 of the dielectric film omitting the nitriding treatment near the mid-gap energy. This is an improvement on the high dielectric film / Si stack showing high interface traps. This is considered to be due to the improvement of interfacial properties due to the proper nitriding effect, which also shows the same result in SiO ₂ / Si.

Fig. 6 is an AES profile showing the components of the dielectric film formed by the embodiment of the present invention and the dielectric film formed by omitting the nitriding process.

In FIG. 6, dotted lines are components of the dielectric film formed according to the embodiment of the present invention, and solid lines are components of the dielectric film formed by omitting nitriding treatment.

Referring to FIG. 6, it can be seen that the dielectric film according to the embodiment of the present invention has a nitrogen content of 2-3%, and evenly distributes nitrogen without piling-up at the interface. have.

As described above, according to the present invention, it is possible to form a dielectric film in which an increase in capacitance equivalent thickness of the film is minimized in a subsequent heat treatment process. In addition, the dielectric film has reduced interface trap density and minimizes flat band shift. In addition, the dielectric layer may prevent diffusion of dopants in the polysilicon layer provided to the gate electrode or the lower electrode.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

1 is a cross-sectional view showing a capacitor dielectric film.

2A to 2C are cross-sectional views illustrating a method of forming a dielectric film according to an embodiment of the present invention.

3 is a graph showing the equivalent oxide film thicknesses of the dielectric film formed by the embodiment of the present invention and the dielectric film formed by omitting the nitriding process.

4 is a graph showing a flat band voltage shift in the dielectric film formed by the embodiment of the present invention and the dielectric film formed by omitting the nitriding process.

5 is a graph showing interface trap densities measured in the dielectric film formed by the embodiment of the present invention and the dielectric film formed by omitting nitriding treatment.

Fig. 6 is an AES profile showing the components of the dielectric film formed by the embodiment of the present invention and the dielectric film formed by omitting the nitriding process.

<Explanation of symbols for the main parts of the drawings>

100 substrate 102 aluminum oxide film

102a: nitrided aluminum oxide film 104: hafnium oxide film

Claims (9)

Forming a first gate dielectric layer on the silicon substrate to prevent reaction with silicon; Nitriding the first gate dielectric layer under a nitrogen atmosphere; And And depositing a high dielectric material on the nitrided first gate dielectric layer to form a second gate dielectric layer. The method of claim 1, wherein the first gate dielectric layer comprises SiO ₂ , Al ₂ O ₃ , Y ₂ O ₃ , MgO, SrO, TiO ₂ , La ₂ O ₃ , Ta ₂ O _5, and at least one of the above materials. The gate dielectric film manufacturing method, characterized in that made of a material selected from the group consisting of silicate material. The method of claim 1, wherein the first gate dielectric layer is formed by an atomic layer deposition method. The method of claim 1, wherein the nitriding of the first gate dielectric layer is performed by thermal nitriding or plasma nitriding. The method of claim 1, wherein the nitriding of the first gate dielectric layer is performed in a gas atmosphere including N ₂ , NH ₃ , N ₂ O, or NO. The method of claim 1, wherein the nitriding of the first gate dielectric layer is performed at a temperature of 100 to 1000 ° C. 3. The method of claim 1, wherein the second gate dielectric layer comprises Y ₂ O ₃ , MgO, SrO, TiO ₂ , La ₂ O ₃ , Ta ₂ O ₅ , HfO ₂ , ZrO ₂ , SrO ₂ , SrTiO _3, and one of the materials. A method of manufacturing a gate dielectric film, comprising a material selected from the group consisting of silicate materials comprising at least one. The method of claim 1, wherein the second gate dielectric layer is formed by an atomic layer deposition method. Forming a bottom electrode on the silicon substrate; Forming a first capacitor dielectric layer on the lower electrode to prevent a reaction with the lower electrode; Nitriding the first capacitor dielectric film under a nitrogen atmosphere; Depositing a high dielectric material on the nitrided first capacitor dielectric layer to form a second capacitor dielectric layer; And And forming an upper electrode on the second capacitor dielectric layer.