KR20050058873A - Device of setting test mode and method - Google Patents

Abstract

The present invention discloses a test mode setting apparatus and method. The test mode setting device enters the test setting mode in response to the row address strobe signal, the column address strobe signal, the write enable signal, and the first command signal, and enables the first mode set signal and the second mode set signal. A first test mode entry unit for outputting, the row address strobe signal, the column address strobe signal, the first command signal, and the second command signal in response to a test setting mode, and a third mode set signal and a fourth A second test mode entry unit for enabling and outputting a mode set signal and a test mode setting code in response to the first, second, third, and fourth mode set signals, and corresponding to the test mode setting code And a test mode setting unit for setting a test mode. Therefore, the number of cases in the test mode is extended.

Description

Device and setting of test mode {Device of setting test mode and method}

The present invention relates to a test method for a semiconductor memory device, and more particularly, to an apparatus and method for setting a test mode for extending a test mode.

In general, a test for detecting a specific failure of a semiconductor memory device is not performed in a normal mode, but in a special test mode that detects a corresponding failure best. To this end, a test mode setting device (MRS) is set in the semiconductor memory device to set a test mode of the semiconductor memory device.

The test mode setting device includes various options such as CAS (Column Address Strobe) latency, burst type, burst length, and the like corresponding to each of the plurality of test modes used by the semiconductor memory device. Program and save. When a command for setting a specific test mode is input from the outside, the test mode corresponding to the input command is identified, and a test mode setting signal (Test_sig) is generated to allow the semiconductor memory device to be set to the identified test mode. Give it.

1 is a block diagram of a test mode setting apparatus according to the related art.

Referring to FIG. 1, the conventional test mode setting device 1 includes a test mode entry unit 11 and a test mode setting unit 12.

The test mode entry part 11 may be a command generated and transmitted from a system (not shown). When the (Row Address Strobe) signal, the CAS signal, and the WE (Write Enable) signal are input in the WCBR (Write and CAS Before RAS) cycle, the test mode setting unit 12 generates a mode set signal (MOSET) for selecting a test mode. Send it to).

The test mode setting unit 12 acquires a test mode setting code in response to the mode set signal MOET generated by the test mode entry unit 11, and determines a test mode corresponding to the obtained test mode setting code. In addition, the semiconductor memory device outputs a test mode setting signal (Test_sig) for setting the checked test mode.

The test mode setting code may be obtained by using a combination of addresses input through the address pin or a combination of data input through the data pin. Here, the test mode setting code may be obtained through a combination of addresses input through the address pin. The case will be described as an example.

FIG. 2 is a timing diagram of signals used by the test mode setting apparatus of FIG. 1 to set a test mode.

The mode set signal (MOSET) The signal, the CAS signal, and the WE signal respond to the reception of the WCBR (Write and CAS Before RAS) cycle. The signal is enabled when a specific test mode is to be set.

More specifically, the mode set signal (MOSET) is when the WE signal has a high level and the CAS signal has a high level, If the signal has a falling edge region, it is enabled to transition from low level to high level, if the WE signal has low level and the CAS signal has low level, If the signal has a rising edge region, it is disabled again and transitions from a high level to a low level.

The test mode setting unit 12 acquires a combination of addresses input in the rising edge and the falling edge regions of the mode set signal MOET, respectively, and identifies a test mode corresponding to the combination of addresses acquired in each edge portion. Generates and outputs a test mode setting signal (Test_sig) for setting the identified test mode.

Table 1 shows the number of test modes in which the conventional test mode setting unit 12 of FIG. 1 can receive and set a combination of a mode set signal and an address.

As shown in Table 1, the test mode setting apparatus of FIG. 1 obtains a combination of addresses in four cases by acquiring a combination of addresses in each of the rising and falling edge regions of the mode set signal. Could be set.

That is, the conventional test mode setting device can set the test mode having the number of cases of " bit number N of address signals 2 " when receiving an N-bit address signal.

Due to the development of the technology of the semiconductor memory device, one semiconductor memory device performs more operations, thereby increasing the test mode for properly testing each operation of the semiconductor memory device.

However, in the related art, even when the rising edge or the falling edge of the mode set is used, there is a problem in that the number of test modes can be extended to only the number of bits N 2 of the address signal.

It is an object of the present invention to provide a test mode setting apparatus and method for extending the number of cases of a test mode by using various kinds of command signals.

The test mode setting apparatus of the present invention for achieving the above object generates a first mode set signal and a second mode set signal in response to a row address strobe signal, a column address strobe signal, a write enable signal, and a first command signal. Generating a third mode set signal and a fourth mode set signal in response to the first test mode entry unit, the row address strobe signal, the column address strobe signal, the first command signal, and the second command signal Outputting a second test mode entry unit and a test mode setting code in response to an edge of the first, second, third, and fourth mode set signals, and obtaining the first, second, third, and fourth test codes; And a test mode setting unit for setting a test mode corresponding to each of the modeset signals.

The test mode setting method of the present invention for achieving the above object is to enable a first mode set signal in response to a write enable signal, a column address strobe signal and a row address strobe signal, the enabled first mode set Enabling the second mode set signal in response to the signal and the first command signal, enabling the third mode set signal in response to the second command signal, the column address strobe signal, and the row address strobe signal, Enabling a fourth mode set signal in response to the enabled third mode set signal and the first command signal, and responding to an edge of each of the first, second, third, and fourth mode set signals; Acquiring a test mode setting code, and setting a test mode corresponding to the test mode setting code.

Hereinafter, the test mode setting apparatus and method of the present invention will be described with reference to the accompanying drawings.

3 is a block diagram of an apparatus for setting a test mode according to an embodiment of the present invention.

Referring to FIG. 3, the present invention provides a test mode setting device including a first test mode entry part 21, a second test mode entry part 22, and a test mode setting part 23, which is used in FIG. 1. In addition to the command, additional external command signals (first command signal COM1 and second command signal COM2) are further received as a command for setting the test mode.

As the external command signal (the first command signal COM1 and the second command signal COM2), all signals that can be received through pins that are used in normal operation but not used in the test mode operation can be applied.

For example, as the first and second command signals COM1 and COM2, an address signal received through an address pin that is used in a normal operation but not used in a test mode, or data transmitted or received through a data pin may be applied. have.

The first test mode entry part 21 is Signal, a CAS signal, a WE signal, and a first command signal COM1 as a command for setting a test mode. Signal, CAS signal, WE signal, and first command signal COM1) to enter the test setting mode and enable the first mode set signal MOSET1 and the second mode set signal MOSET2 to enable the test mode setting unit. Transfer to 23.

The second test mode entry section 22 Signal, a CAS signal, a first command signal COM1, and a second command signal COM2 as a command for setting a test mode, Signal, the CAS signal, the first command signal COM1, and the second command signal COM2, enter the test setting mode and enable the third mode set signal MOET3 and the fourth mode set signal MOET4. To the test mode setting unit 23.

At this time, the second command signal COM2 is a signal that performs the same role as the WE signal transmitted to the first test mode entry part 21, and the second test mode entry part 22 is the second command signal COM2. Recognizes the same as the WE signal of the first test mode entry unit 21 and performs a test mode setting operation.

The test mode setting unit 23 addresses the rising edge area and the falling edge area of each of the modeset signals MOET1, MOSET2, MOSET3, and MOSET4 transmitted from the first or second test mode entry parts 21 and 22. Obtain a combination of.

As shown in Table 2, the combination of the acquired addresses, the logic states of the enabled specific mode set signals (MOSET1, MOSET2, MOSET3, MOSET4) and the specific mode set signals (MOSET1, MOSET2, MOSET3, MOSET4) Or a test mode to be set based on the falling edge) and outputs a test mode setting signal (Test_sig) for setting the semiconductor memory device to the identified test mode.

Table 2 shows the number of test modes in which the test mode setting unit 23 of FIG. 3 can receive and set a combination of mode set signals MOET1, MOSET2, MOSET3, and MOSET4 and an address.

As shown in Table 2, the test mode setting apparatus of FIG. 3 adds the first command signal COM1 and increases the number of mode set signals to four by using the second command signal COM2 instead of the WE signal. The combination of addresses can be obtained in the rising edge and falling edge regions of each of the four mode set signals, thereby extending the number of test modes that can be set to 16.

Hereinafter, a test mode setting method of the test mode setting apparatus of FIG. 3 will be described with reference to a timing diagram of signals used to set the test mode in the present invention of FIG. 4.

First, when the semiconductor memory device operates in the normal mode, The signal goes to the high level, the CAS signal to the low level, the WE signal to the low level, the first command signal COM1 to the low level, and the second command signal COM2 to the low level. 21 and the second test mode entry 22.

Accordingly, the first test mode entry part 21 and the second test mode entry part 22 in the normal mode have the first mode set signal MOET1, the second mode set signal MOET2, and the third mode having a low level. The set signal MOET3 and the fourth mode set signal MOET4 are outputted.

Subsequently, a WE signal having a high level is input so that the semiconductor memory device is set and operated in a specific test mode, followed by a CAS signal having a high level. When the signal transitions from the high level to the low level, the first test mode entry part 21 transitions the first mode set signal MOSFET1 from the low level to the high level.

Accordingly, when the first mode set signal MOSFET1 has a rising edge, the test mode setting unit 23 acquires and sets a combination Arf of an address input in the rising edge region of the first mode set signal MORTI1. And then outputs a test mode setting signal (Test_sig) corresponding to the identified test mode.

The first test mode entry part 21 may output the second mode set signal MOET2 when the first command signal COM1 transitions from the low level to the high level when the first mode set signal MOET1 has a high level. Transition from low level to high level.

When the second mode set signal (MOSET2) has a rising edge. The test mode setting unit 23 acquires a combination of the addresses Asr input from the rising edge region of the second mode set signal MOET2, identifies a test mode to be set, and a test mode setting signal corresponding to the identified test mode. Print (Test_sig).

When the first command signal COM1 having the high level transitions to the low level again, the first test mode entry part 21 transitions the second mode set signal MOET2 from the high level to the low level and sets the test mode. The unit 23 acquires the combination of the addresses Asf inputted from the falling edge region of the second mode set signal MOET2, determines a test mode to be set, and a test mode setting signal Test_sig corresponding to the identified test mode. Will output

The first test mode entry part 21 is When the signal transitions from the low level to the high level again, the first mode set signal MOET1 having the high level is transitioned to the low level. Then, the test mode setting unit 23 acquires a combination (Arr) of addresses input in the falling edge region of the first mode set signal MOET1, determines a test mode to be set, and sets a test mode corresponding to the identified test mode. Outputs the signal Test_sig.

In the same way, the second test mode entry part 22 may be connected to the second command signal COM2 and the CAS signal. A signal and a first command signal COM1 are inputted to transition a logic state of the third mode set signal MOET3 and the fourth mode set signal MOET4, and the test mode setting unit 23 is input at each edge region. The test mode is determined by acquiring a combination of the addresses (Arf, Arr, Asr, and Asf), and the test mode setting signal Test_sig corresponding to the identified test mode is output.

As described above, the test mode setting apparatus of FIG. 3 adds the first command signal COM1 and enables the second command signal COM2 to be used in place of the WE signal, thereby increasing the number of possible mode set signals, A combination of addresses input in the rising edge and falling edge regions of each mode set signal is obtained.

The combination of the obtained address, the type of the mode set signal that is enabled and transmitted from the first test mode entry part 21 or the second test mode entry part 22, and the logic state of the transmitted mode set signal (falling edge or The rising edge) is used as a criterion to determine the test mode code to be set.

Accordingly, the number of test modes that the test mode setting apparatus can identify and set by using the 2-bit address signal Add, the first command signal COM1, and the second command signal COM2 is "16". Extends to.

In the present invention, only one second command signal is added instead of serving as a WE signal, but it may be extended to a plurality if necessary.

In addition, although only one first command signal for generating the second mode set signal and the fourth mode set signal by increasing the intermediate edge is added, it may be extended to a plurality as necessary.

Therefore, according to the technique of the present invention, when the number of second command signals added for use instead of the WE signal is p and the number of added first command signals for increasing the number of intermediate edges is q, a test that can be set For mode, set the number to "(number of bits in the address signal ((N) 2) (p +1) (q + 1) ".

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and modified within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. It will be appreciated that it can be changed.

Therefore, the test mode setting apparatus and method of the present invention extends the number of cases of the test mode by using external command signals that are used in normal operation but not used in the test mode.

1 is a block diagram of a test mode setting apparatus according to the related art.

FIG. 2 is a timing diagram of signals used by the test mode setting apparatus of FIG. 1 to set a test mode.

3 is a block diagram of an apparatus for setting a test mode according to an embodiment of the present invention.

4 is a timing diagram of signals used by the test mode setting apparatus of FIG. 3 to set a test mode.

Claims (13)

A first test mode entry unit configured to generate and output a first mode set signal and a second mode set signal in response to a row address strobe signal, a column address strobe signal, a write enable signal, and a first command signal; A second test mode entry unit configured to generate and output a third mode set signal and a fourth mode set signal in response to the row address strobe signal, the column address strobe signal, the first command signal, and the second command signal; And Acquire a test mode setting code in response to an edge of the first, second, third, and fourth mode set signals, and determine a test mode corresponding to each of the first, second, third, and fourth modeset signals. A test mode setting device including a test mode setting unit for setting. The method of claim 1, wherein the first test mode entry section Enable and output the first mode set signal in response to the row address strobe signal, the column address strobe signal, and the write enable signal, and respond to the first command signal when the first mode set signal is enabled And enabling the second mode set signal to be outputted. The method of claim 1, wherein the second test mode entry section Enable and output the third mode set signal in response to the row address strobe signal, the column address strobe signal, and the second command signal, and respond to the first command signal when the third mode set signal is enabled The test mode setting device, characterized in that for enabling the output of the fourth mode set signal. The method of claim 1, wherein the second test mode entry section And recognizing and operating the second command signal as the write enable signal. The method of claim 1, wherein the first command signal is The test mode setting device, characterized in that the command signal received through an external pin that is used in the normal mode but not used in the test mode. The method of claim 1, wherein the second command signal is The test mode setting device, characterized in that the command signal received through an external pin that is used in the normal mode but not used in the test mode. The method of claim 1 wherein the edge is A test mode setting device, characterized in that the rising edge and falling edge. Enable the first mode set signal in response to the write enable signal, the column address strobe signal, and the row address strobe signal, and generate the second mode set signal in response to the enabled first mode set signal and the first command signal. Enabling; Enable a third mode set signal in response to a second command signal, the column address strobe signal, and the row address strobe signal, and enable a fourth mode in response to the enabled third mode set signal and the first command signal Enabling the set signal; And Obtaining a test mode setting code in response to an edge of each of the first, second, third, and fourth mode set signals, and setting a test mode corresponding to the test mode setting code. How to set test mode. The method of claim 8, wherein the enabling of the first mode set signal and the second mode set signal comprises: Transitioning the first mode set signal from a low level to a high level if the write enable signal has a high level and the column address strobe signal has a high level and the low address strobe signal transitions from a high level to a low level; Translating the second mode set signal from the low level to the high level when the first mode set signal has a high level and the first command signal transitions from the low level to the high level; Translating the second mode set signal from the high level to the low level when the first mode set signal has a high level and the first command signal transitions from the high level to the low level; And Transitioning the first mode set signal from a high level to a low level if the write enable signal has a low level and the column address strobe signal has a low level and the low address strobe signal transitions from a low level to a high level; Characterized in the test mode setting method. 9. The method of claim 8, wherein enabling the third and fourth mode set signals Translating a third mode set signal from a low level to a high level when the second command signal has a high level and the column address strobe signal has a high level and the low address strobe signal transitions from a high level to a low level; Transitioning a second mode set signal from a low level to a high level when the first command signal transitions from a low level to a high level when the third mode set signal is at a high level; Translating a second mode set signal from a high level to a low level when the first command signal transitions from a high level to a low level when the third mode set signal is at a high level; And Transitioning a third mode set signal from a high level to a low level if the second command signal has a low level and the column address strobe signal has a low level and the low address strobe signal transitions from a low level to a high level; Test mode setting method, characterized in that. The method of claim 8, wherein the first command signal is The test mode setting method, characterized in that the command signal received through an external pin that is used in the normal mode but not used in the test mode. The method of claim 8, wherein the second command signal is The test mode setting method, characterized in that the command signal received through an external pin that is used in the normal mode but not used in the test mode. The method of claim 8, wherein the edge is A test mode setting method characterized by being a rising edge and a falling edge.