KR20050050702A - A burn-in method for testing wafer - Google Patents

Abstract

The wafer burn-in test method according to the present invention includes applying a plurality of burn-in test voltages to a semiconductor memory device on a wafer through a plurality of pads, and selectively varying the plurality of burn-in test voltages to burn-in stress in the semiconductor memory device. Controlling the voltage difference.

Description

A burn-in method for testing wafer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer burn-in test method, and more particularly, to a method of burn-in test of a memory cell array of a semiconductor memory device in a wafer state.

In general, the burn-in test is performed by operating a semiconductor device (here, a memory device) at a high temperature and a high voltage to test its reliability. This burn-in test is generally performed after packaging a semiconductor device.

Recently, however, for customers who want to receive a product (semiconductor memory device) in a wafer state, a burn-in test with a probe in a wafer state is increasing.

However, when the burn-in test is performed at the wafer stage, a predetermined stress voltage should be applied to each of the unit cells constituting the memory cell array. In the conventional case, design problems (for example, difficulty in layout and chip addition) Due to the increase in size, a method of applying a specific stress voltage to each node of the memory cell has not been proposed, and as a result, the ability to remove an initial defect that may occur at a specific portion of the memory cell is often inferior.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-described problem, and is intended to provide a burn-in test method in a wafer state in which a predetermined stress voltage can be applied to each portion of a memory cell.

The wafer burn-in test method according to the present invention includes applying a plurality of burn-in test voltages to a semiconductor memory device on a wafer through a plurality of pads, and selectively varying the plurality of burn-in test voltages to burn-in stress in the semiconductor memory device. Controlling the voltage difference.

The burn-in test may be performed in a state in which a plurality of word lines of the memory cell array constituting the semiconductor memory device are all enabled.

The burn-in test may be performed while alternately enabling odd word lines and even word lines among a plurality of word lines of the memory cell array constituting the semiconductor memory device.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 illustrates a unit cell forming a memory cell array of a semiconductor memory device.

In Fig. 1, numeral 101 denotes a bit line, numeral 102 denotes a cell transistor and numeral 103 denotes a cell capacitor. In addition, Vblp represents a precharge voltage applied to the bit line, VPP represents a word line voltage applied to the cell transistor, Vcp represents a cell plate voltage, and Vsn represents a voltage of a node where charge is stored. ST1, ST2, and ST3 represent stress voltage differences between nodes, respectively. That is, it shows the stress voltage difference between the nodes generated under the voltage conditions of Table 1 to be described later.

Table 1 shows the burn-in test conditions for the memory cell array.

TABLE 1

group mode VPP VCORE VCP VBLP G1 cell to cell 5.6 V 2.0V VCORE / 2 2.9 V G2 ONO mode 5.6 V 2.0V VSS 0V or 2.0V

In Table 1, group G1 represents a burn-in test condition of a cell to cell mode in which odd word lines and even word lines of a memory cell array are alternately enabled, and group G2 represents a memory. This represents a burn-in test condition in ONO mode where all word lines in the cell array are enabled at the same time. The high voltage VPP represents the voltage level applied to the word line, and the core voltage VCORE is applied to the memory cell capacitor applied to the plate of the memory cell capacitor and the voltage for the operation of the peripheral circuit for this series of driving. The voltage VCP indicates the cell plate voltage of the capacitor, and the voltage VBLP is the precharge voltage applied to the bit line as the precharge voltage of the bit line, and at the same time, the voltage writing high data to the cell. Indicates. For reference, in order to perform each of the burn-in test procedures described above, it is preferable to add a separate circuit for enabling word lines as a whole or as a whole.

As shown in Table 1, the burn-in test conditions for the cell-to-cell mode of group G1 are 5.6V for high voltage (VPP), 2.0V for core voltage (VCORE), VCORE / 2 for voltage (VCP), and bits. The line precharge voltage VBLP was set at 2.9V. The burn-in test condition of the group G2 in the ONO mode was set to 5.6V for the high voltage VPP, 2.0V for the core voltage VVC, and 2.0V for the voltage VCP, and the bit line precharge voltage VBLP. ) Was tested by applying 0V and 2.0V respectively. At this time, each voltage was applied through a corresponding pad, and the ambient temperature was about 100 ⁰ C during the test. As such, the wafer burn-in test of the present invention performs a test on the memory cell under voltage conditions as shown in Table 1, so that the stress voltage applied to the memory cell can be transferred to each part of the cell.

In the burn-in test in the case of the cell-to-cell mode, an effect of applying stress to ST1, ST2, and ST3 shown in FIG. 1 can be obtained. In the burn-in test in the ONO mode, when the voltage VBLP is 0 V, stress is applied to ST2 and ST3. When the voltage VBLP is 2.0 V, stress is applied to ST1. It is effective. Therefore, it can be seen that by selecting various burn-in voltages, a section in which stress is applied can be variously selected, and a burn-in test of the memory device can be easily performed in a wafer state.

After performing the burn-in test in the wafer state according to the present invention, it is generally subjected to the first probe test and repair process and the second probe test and package process. Therefore, a product with a very low defective rate can be delivered to the customer.

As can be seen from the above, when the wafer is burned-in under the conditions of the present invention, the following effects can be obtained.

1) After the burn-in test is performed on the wafer state, the probe test and repair process and the second probe test and package process are performed. Thus, unlike the conventional case, the package yield is increased, and the economic effect is cumulative. To increase.

2) cumulative as a result of 1)

3) Wafer beads can be made by producing KGD (Known Good Die) materials for the wafer.

1 illustrates a unit cell forming a memory cell array of a semiconductor memory device.

Claims (3)

In the wafer burn-in test method, Applying a plurality of burn-in test voltages to the semiconductor memory device on the wafer through the plurality of pads; And selectively varying the plurality of burn-in test voltages to control the burn-in stress voltage difference in the semiconductor memory device. The method of claim 1, And performing the burn-in test with all word lines of the memory cell array constituting the semiconductor memory device enabled. The method of claim 1, And performing the burn-in test while alternately enabling odd word lines and even word lines among a plurality of word lines of a memory cell array constituting the semiconductor memory device.