JP2965881B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to screening for a transfer gate of a memory cell when screening a dynamic RAM (hereinafter referred to as DRAM), for example, in a wafer state. The present invention relates to a circuit for applying a voltage stress by accelerating from a normal use.

[0002]

2. Description of the Related Art In general, when a semiconductor device is manufactured and shipped, in order to ensure the reliability of the device, a potential defect of the device is exposed so that a non-defective device is not deteriorated or defective, and the defective device is removed. Perform screening. As a screening method, burn-in capable of simultaneously realizing electric field acceleration and temperature acceleration is often used. In this burn-in, by operating the device with the voltage higher than the actual operating voltage and the temperature higher than the actual operating temperature, the device experiences a stress in a short time more than the initial failure period under the actual operating condition, Devices that may cause an initial operation failure are selected and screened before shipment. As a result, it is possible to efficiently remove a device that may cause an initial operation failure and to increase the reliability of the product.

Conventionally, when burning in a DRAM,
A method is used in which scanning is performed in the order of addresses and word lines are sequentially accessed. In this case, regarding a transfer gate transistor (hereinafter, referred to as a cell transistor) of a memory cell in which a gate is connected to a word line, voltage stress is applied much less frequently than a transistor in a peripheral circuit. For example, for a 4 mega DRAM, the word line is 409
Although there are six, only four of them are selected in one cycle.
It is completed by performing four cycles. Therefore, the gate of the cell transistor is subjected to voltage stress only for a time period of 1024 times shorter than that of the transistor of the peripheral circuit, and the substantial time during which the maximum electric field is applied is short. And

Further, in recent DRAMs, it is general that half of the power supply voltage (Vcc / 2) is applied to an electrode of a capacitor of a memory cell. For this reason, even if the insulating film of the capacitor has a small thickness, it is relaxed in terms of the electric field, so that there is little problem in reliability. On the other hand, since a boosted potential (for example, in the vicinity of 1.5 × Vcc) is applied to the gate oxide film of the cell transistor when the cell transistor is selected, a severe electric field is applied to the gate oxide film even if the film thickness is large. It is likely to be a sexual problem. Therefore, at the time of the burn-in of the DRAM, particularly, it is desired to actively screen the cell transistor to which the boosted potential is applied to the gate.

As described above, in order to solve the problem that the voltage stress is applied only infrequently to the cell transistors that are to be actively screened, one of the inventors of the present application has proposed that all of the cell transistors be screened at the time of failure screening. A semiconductor memory device capable of simultaneously applying voltage stress to a word line or to a number of word lines selected during normal operation and improving the efficiency of stress application to a cell transistor has been proposed. Japanese Patent Application No. 1-169631).

As a result, in the case of the DRAM, the screening for the failure of the transfer gate of the memory cell is at a level at which the failure sufficiently converges, and the DRA of 1 Meg
Bit defects that occupy the majority of defects in M and 4-mega DRAMs can be quickly converged, and screening efficiency can be significantly improved.

In the semiconductor memory device according to the above proposal, specific examples of means for simultaneously applying a voltage stress to the word lines of the DRAM include: (a) As shown in FIG. To turn on an N-channel MOS transistor (hereinafter referred to as an NMOS transistor) 12 for driving a word line, and to provide a desired voltage applied externally to the pad 18 in a DC (direct current) or AC (alternating current) manner. Stress above NM
Configuration in which voltage is applied to the gate of cell transistor 15 via OS transistor 12 and word line WL, (b) FIG.
As shown in the figure, a switching NMOS transistor controlled to be turned on by a gate voltage given from a pad 26 at the time of screening for a defect is provided at the other end of the word line WL having one end connected to the word line driving circuit. 2
5 is connected, and a desired voltage stress externally applied to the pad 27 is applied to the gate of the cell transistor 15 via the switching transistor 25 and the word line WL.

[0008]

As described above, in a currently proposed semiconductor memory device, a desired stress voltage is applied to a pad at the time of screening a DRAM for defects.
When the voltage is applied to the NMOS transistor for driving the word line and the gate of the cell transistor via the word line, the gate node of the NMOS transistor for driving the word line is in a floating state and the level is lowered by leakage. In addition, there is a possibility that the DC-like voltage stress in the word line portion decreases. In addition, when the voltage stress is applied in an AC manner, there is a time when no stress is applied, and the efficiency of the stress application time is reduced.

A switch NMO connected to the other end of the word line by applying a desired stress voltage to the pad.
When voltage is applied to the gate of a cell transistor via an S transistor and a word line, voltage stress is applied without passing through a word line drive circuit. Therefore, a voltage stress test is performed on the cell transistor and the word line drive circuit simultaneously. This cannot be performed, and an NMOS transistor for switching is added for each word line, which causes an increase in the chip area of the memory device.

As described above, conventionally, when a voltage higher than the power supply voltage is applied to the word line, a large number of elements are required, and there is a problem that the chip area cannot be reduced.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device capable of applying a voltage higher than a power supply voltage to a word line and reducing a chip area. Aim.

[0012]

According to the present invention, a plurality of memory cells arranged in a matrix, a plurality of word lines connected to memory cells in the same row, and memory cells in the same column are connected. A plurality of bit lines, a word line drive voltage source including a booster circuit for boosting an externally applied power supply voltage, and outputting a word line drive voltage having the boosted power supply voltage, and a plurality of selecting the plurality of word lines A word line selection circuit;
A plurality of word line driving circuits supplied with corresponding outputs of the plurality of word line selection circuits and driving the plurality of word lines
And multiple address patches to which external address signals are input.
Input to the address pads during normal operation.
The plurality of words according to the external address signal
Supply the internal address signal to the line selection circuit,
At the time of test, according to the external address signal during normal operation
The plurality to select more rows than the selected rows
To supply the internal address signal to the word line selection circuit
A plurality of word line selection circuits, wherein each of the plurality of word line selection circuits is a P-channel type first MOS transistor to which the word line driving voltage is applied to a source when the word line is driven; A plurality of N-channel type transistors whose sources and drains are connected in series between the drain of the transistor and the ground potential and whose gate receives an internal address signal having a voltage amplitude value different from the word line driving voltage are supplied to the gate. And a plurality of MOS transistors, each of the plurality of word line driving circuits having a P-channel type having a source applied with the word line driving voltage and a drain connected to the corresponding word line during word line driving. and third MOS transistors, the source and the drain is connected the gate between the drain and the ground potential of the third MOS transistor Gate of said third MOS transistor
And the common gate is connected to the corresponding gate.
The first MOS transistor in the word line selection circuit
And a fourth MOS transistor of an N-channel type controlled on the basis of the potential of the drain of the first MOS transistor in the plurality of word line selection circuits. The one MOS transistor is controlled by a precharge signal in which one voltage value of the signal is equal to the word line driving voltage.

[0013]

A word line selecting circuit for selecting a word line, and a word line driving circuit for driving a word line to which the output of the word line selecting circuit is supplied are respectively composed of a P-channel type MOS transistor and an N-channel type MOS transistor. With this configuration, the output of the word line selection circuit can be supplied to the word line selection circuit without level conversion using a level conversion circuit, and the power supply voltage output from the word line drive voltage source is stepped up. The use voltage can be directly output to the word line.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a part of a DRAM considered in the course of the present invention. 31 are address bonding pads to which an address signal is inputted from outside the chip, and 32 are stress test signal pads which are not used during normal operation but receive a voltage stress test control signal from outside during a voltage stress test.

The address amplifying circuits 33... Receive correspondingly the address signals from the address pads 31 and output complementary internal address signals. The control circuit 34 has a group of gate circuits connected to the output side of the address amplifier circuits 33... During normal operation, outputs a complementary internal address signal output from the address amplifier circuits 33. During the test, the internal address signal is controlled so as to select more rows than the rows selected according to the external address signal during normal operation. As a configuration example of the control circuit 34,
Inverters 35 and 36 to which complementary internal address signals output from the address amplifier circuits 33 are input, respectively.
A two-input NAND gate 38 that takes NANDs of the output of the inverter 37 and the output of the inverters 35 and 36, respectively. It consists of 39 groups.

The word line selection circuits 40 are constituted by a group of NAND gates, and output a word line selection signal in accordance with the internal address signal from the control circuit 34. The word line driving circuit 41 includes a word line driving voltage source 42 and a word line WL.
And at least one driving MOS transistor 43 connected between the word line selecting circuit 40 and drives the word line WL according to the output signal of the word line selecting circuit 40.

As an example of the word line drive circuit 41, one end is connected to the output terminal of the word line selection circuit 40,
NMOS for barrier with power supply potential Vcc applied to gate
A transistor 44 having a gate connected to the other end of the transistor 44, a source / substrate connected to each other, and a driving PMOS transistor 43 connected between the word line driving voltage source 42 and the word line WL; , Word line W
The pull-down (noise canceling) NMOS transistor 45 connected between L and the ground potential Vss, the gate is connected to the word line WL, the source and the substrate are connected to each other, and the word line driving voltage source 42 Driving PMOS
It comprises a pull-up PMOS transistor 46 connected between the gate of the transistor 43.

In the present embodiment, the word line drive voltage source 42 comprises a booster circuit for boosting a power supply voltage generated inside the memory device (on the DRAM chip), for example, usually applied from outside the chip. It is assumed that the output is commonly supplied to a plurality of word line drive circuits 41 as a word line drive voltage.

In the above-mentioned DRAM, a plurality of dynamic memory cells requiring a refresh operation are arranged in a matrix as usual, word lines are connected to memory cells in the same row, and memory cells in the same column. Is connected to a bit line. In this memory cell, as shown in FIG. 3 to be described later, the gate of the NMOS transistor 15 is connected to the word line WL, the drain is connected to the bit line BL, and the source is connected to one end of the capacitive element 16 for storing information. , And the other end of the capacitive element 16 is connected to the capacitor plate potential.

Next, the operation of the circuit shown in FIG. 1 will be described. In the normal operation, when an address signal is input from the outside to the address amplifying circuit 33, a complementary internal address signal is output, and an arbitrary number of word lines WL corresponding to the logic level combination of the internal address signal are output. The word line selection signal is output, and the word line WL is selected. In this case, in the selected word line drive circuit 41 to which the active level “L” of the word line selection signal is input, the NMOS transistor 45 is turned off and the barrier NM is turned off.
Since the OS transistor 44 is turned on, the gate potential of the driving PMOS transistor 43 is set to the ground potential Vss.
And the word line WL is driven to the "H" level state, and the PMOS transistor 46 for pull-up is turned off since the gate potential (word line potential) is at the "H" level.

In the non-selected word line drive circuit 41 to which the inactive level "H" of the word line selection signal is inputted, the NMOS transistor 45 is turned on and the barrier NMOS transistor 44 is turned off. The PMOS transistor 46 for pull-up is turned on because the gate potential (word line potential) is at the “L” level, and the PMOS transistor 43 for driving is turned off because the gate potential is at the “H” level. Become.

On the other hand, when performing the burn-in of the DRAM, an operating power is supplied to make the DRAM operable, and an "H" level voltage stress test control signal is input to the pad 32. Numeral 34 sets all complementary internal address signals to "H" level, all the output signals of the word line selection circuit 40 to "L" level, and drives all word lines WL.

As described above, according to the DRAM of FIG.
The control circuit 34 selects more rows than the rows selected in accordance with the external address signal during normal operation, based on a voltage stress test control signal input from the outside via the pad 32 not used during normal operation. Since the internal address signal is controlled during the normal operation, the word line drive circuit 41 drives more rows than the row selected in accordance with the input of the external address signal during the normal operation.

As a result, DC-like voltage stress can be simultaneously applied to all the word lines WL or more than the number of word lines WL selected during normal operation via the word line driving circuit 41 at the time of burn-in. Can be significantly improved.

When the cell transistor 15 is an NMOS transistor, a PMOS transistor 43 is used as a word line driving transistor, and the gate node of the PMOS transistor 43 is fixed to the ground potential Vss during a voltage stress test, and the gate of the PMOS transistor 43 is fixed to the ground potential Vss. Since the node is kept stable, there is no drop in the word line potential due to the leakage of the gate node, and the PMOS transistor 43
, A DC-like voltage stress can be stably applied to the word line WL.

Moreover, the control circuit 34 can be realized with a relatively simple circuit configuration, and the increase in the chip area of the storage device due to the addition of the control circuit can be reduced. FIG.
1 shows a configuration of a DRAM according to a first embodiment of the present invention. In this embodiment, a case is shown in which a word line selection circuit 50 composed of a precharge type NAND gate is used, and a CMOS inverter composed of a PMOS transistor 43 and an NMOS transistor 45 is used as the word line drive circuit 51. Therefore, the same reference numerals are given.

The precharge type NAND gate is connected between the word line driving voltage source 42 and the ground potential Vss.
PMOS transistor 52 for precharge and three NMOS transistor group 5 for decoding internal address signal
3 are connected in series, and the PMOS transistor 52 and N
An output node 54 is a connection point in series with the MOS transistor group 53.

That is, the word line selection circuit 50
PMOS to which the word line driving voltage is applied to the source
The source and the drain are connected in series between the transistor 52 and the drain of the PMOS transistor 52 and the ground potential Vss, and the internal address signal is supplied to the gate.
And a plurality of NMOS transistor groups 53. The word line drive circuit 51 includes a PMOS transistor 43 having the source to which the word line drive voltage is applied and the drain connected to the corresponding word line WL,
The NMOS transistor 45 has a source and a drain connected between the drain of the MOS transistor 43 and the ground potential Vss.

The operation of the word line selection circuit 50 is such that the precharge signal becomes active level "L" and the output node 5
4 is precharged to the “H” level, and when all the input internal address signals are at the “H” level, the signal at the output node 54 (word line selection signal) is pulled down to the “L” level. In the word line drive circuit 51, the PMOS transistor 43 / NMOS transistor 45 are turned on in accordance with the “L” / “H” level of the word line selection signal. Note that the PMOS transistor 52 is turned off.
Therefore, the “H” level of the precharge signal
Word line drive applied to the source of OS transistor 52
Of course, the voltage value is set equal to the operating voltage.
is there.

According to the DRAM of FIG. 2, basically the same operation as that of the above-described DRAM of FIG. 1 is possible, and the same effect as that of the DRAM of FIG. 1 is obtained. In this embodiment,
According to this, the level shift elements (MOS transistors 44 and 46) can be omitted as compared with the DRAM of FIG. 1 , so that the chip area can be reduced.

FIG. 3 shows another DRAM conceived in the course of the present invention. In the DRAM shown in FIG. 1, a bit line for connecting each bit line to a desired fixed potential during a voltage stress test is shown. Potential control means is added,
The same parts as those in FIG. 1 are denoted by the same reference numerals.

As an example of the bit line potential control means, a switch NMOS is provided at one end of each bit line.
A transistor 47 is inserted and connected to control each of the switching transistors 47 to an on state when a signal is input from the stress test control signal pad 32, and a desired voltage is applied to one end of each of the switching transistors 47. The bit line voltage application circuit 48 to be connected is connected.

In this case, the signal input from the stress test control signal pad 32 and the bit line precharge are performed so that each of the switch transistors 47 is also used as a bit line precharge transistor used during normal operation. A logic circuit 49 for taking a logical sum with the equalizing signal EQL and applying the logical sum to the gate of each of the switching transistors 47; and as the bit line voltage applying circuit 48, a bit line is connected to the bit line BL during normal operation. A precharge voltage generation circuit for applying a precharge potential VBL (intermediate potential between the power supply potential Vcc and the ground potential Vss, usually Vcc / 2) is used, and the output of the precharge voltage generation circuit is input by a voltage stress test control signal input. Switching circuit for controlling the voltage to a desired voltage (for example, ground potential Vss) It may be configured to operate the switching circuit when a voltage stress test.

According to the DRAM of FIG. 3, basically the same operation as the DRAM of FIG. 1 described above can be performed, and the same effect as that of the DRAM of FIG. 1 can be obtained. BL is a transistor 47 for each switch.
Can be set to, for example, the ground potential Vss, so that a large voltage stress can be applied between the gate and the drain of each cell transistor 15.

FIG. 4 shows another DRAM conceived in the course of the present invention. Compared with the DRAM shown in FIG. 1, the word line drive voltage application pad 61 which is not used during the normal operation and the normal DRAM 61 are used. At the time of operation, the word line driving voltage source 42 generated inside the storage device is selected, and at the time of a voltage stress test, a desired stress voltage applied from the external voltage source via the pad 61 is selected to select the word line driving voltage. And a switching circuit 62 for supplying the same, and the other components are the same.

According to the DRAM of FIG. 4, basically, the same operation as that of the DRAM of FIG. 1 can be performed, and the same effect as that of the DRAM of FIG. 1 can be obtained. In the case where 42 is generated inside the storage device (on the DRAM chip), there is only the ability to drive the number of word lines selected during normal operation, and when all word lines WL are driven, a transient voltage drop occurs. Can be avoided. This makes it possible to immediately apply a DC-like stress to the word line WL via the word line drive circuit 41.

The switching circuit 62 is omitted, and the word line drive voltage application pad 61 is connected to the output node of the word line drive voltage source 42. Even when the word line driving voltage is supplied via the transistor 61, the same effect as that of the DRAM of FIG. 3 can be obtained.

FIG. 5 is a block diagram showing a second embodiment of the present invention.
2 shows a configuration of a RAM. The DRAM of this embodiment is
As in the DRAM of FIG. 2, a case is shown in which a word line selection circuit 50 composed of a precharge type NAND gate is used, and a CMOS inverter is used as a word line drive circuit 51. Others are the same as those in FIG. The same reference numerals are given. The DRAM of FIG. 5 has the same effect as the DRAM of FIG.

FIG. 6 shows a DRAM according to a third embodiment of the present invention.
2 is different from the DRAM of FIG. 2 in that the control circuit 34 on the output side of the address amplifying circuits 33.
The difference is that a control circuit 70 is provided on the output side of the word line selection circuit 50, and the other components are the same, and thus are denoted by the same reference numerals. The control circuit 70 has gate circuits connected to the output side of the word line selection circuit 50, respectively.
The word line selection signal output from the word line selection circuit 50 is output during the normal operation, and the word line selection signal is output during the voltage stress test so as to select more rows than the rows selected according to the external address signal during the normal operation. Is controlled.

As an example of the configuration of the control circuit 70, the stress test control signals of “H” level are commonly connected to the output side of the word line selection circuit 50 and input from the stress test signal pad 32, respectively. NMOS for setting word line select signal to select state (“L” level)
It is composed of a group of transistors 71. The operation of the control circuit 70 is such that during normal operation, the NMOS transistors 71 are in the off state, the word line selection signal is output as it is, and the "H" level voltage stress test control signal is input to the stress test signal pad 32. , NMOS transistor 7
The first group is turned on, and the word line selection signals are all set to “L”.
Level to drive all word lines WL.

According to the DRAM of FIG. 6, basically the same operation as the DRAM of FIG. 2 can be performed, and the same effect as that of the DRAM of FIG. 2 can be obtained. FIG. 7 shows a configuration of a DRAM according to a fourth embodiment of the present invention. The DRAM of this embodiment differs from the DRAM of FIG. 6 in that a control circuit 70 is provided on the output side of the word line selection circuit 50, and the other parts are the same as those in FIG. doing. The DRAM shown in FIG.
The same effect as M can be obtained.

Note that the bit line potential control means as shown in FIG. 3 can also be employed in the DRAMs of FIGS. 2, 4 to 7. Further, in each of the above embodiments, the predetermined voltage is applied from the pad which is not used in the normal operation. However, by providing means for switching the role of the pad between the normal operation mode and the stress test mode, the normal operation is performed. It is also possible to use the same pad as used.

In each of the above embodiments, the pad 32 for stress test control signal or the pad 61 for applying word line drive voltage may be a bonding pad, but is not limited to this, and the DRAM is kept in a wafer state. In the case of burn-in, the structure may be such that a voltage can be applied by contacting the stylus of the tester probe card. In the case of performing burn-in in a state where the DRAM chip is separated from the wafer and then packaged, the packaging is performed. At this time, any structure can be used as long as it can be connected to wiring outside the chip.

When the DRAM is burned in a wafer state, the pad 32 for stress test control signal and the pad 61 for applying word line drive voltage are shared by a plurality of chips, respectively. Wiring for connecting a plurality of chips may be formed on, for example, a dicing line region of a wafer.

Here, an advantage in the case of performing burn-in with the above-mentioned DRAM in a wafer state will be described. As described in the above embodiments, the burn-in efficiency is significantly improved,
Since the time required for burn-in can be significantly reduced,
Simultaneous burn-in of multiple DRAM chips in the wafer state makes it possible to apply voltage stress using a high-temperature prober and probe card, before and after die sorting immediately after the wafer process. Burn-in can be easily performed.

Therefore, it is not necessary to perform a long burn-in in the form of a final product housed in a package after the assembly as is currently performed, or the time can be greatly reduced. In other words, the burn-in device can be reduced in scale, the capital investment of the burn-in device, the installation place and the test time can be saved, and the manufacturing cost of the semiconductor integrated circuit can be greatly reduced.

Of course, a new burn-in device that can apply electrical and thermal stress in the wafer state is required, but this device is much simpler and smaller than the conventional burn-in device, and requires less space. Will be possible. In addition, in the conventional method of burning in at the stage of assembly, it is possible to treat defective products at the wafer stage as defectives. Therefore, it is possible to solve a problem that loss is remarkably large as compared with a defective chip which is processed as a defect at the time of die sorting.

In addition to the die sort, if a process of applying a stress for a certain period of time is inserted and the weak transistor is flipped out before the die sort, the stress is not applied during the die sort, and the tester is stopped. This eliminates the necessity, and enables effective utilization of the equipment.

Further, in the case of a DRAM provided with a redundant circuit, if burn-in in a wafer state is performed before die sorting, it is possible to rescue a portion of the burn-in which has been a defective product in the past. The yield can be expected to be improved, and a significant cost reduction effect can be expected from the viewpoint of reducing defects at a later stage of the process.

The method of supplying the voltage stress test control signal as described above is as follows: (a) As in the above-described embodiment, a signal is input from the outside through a dedicated pad in a wafer state, or during normal operation after packaging. In addition to the method of externally inputting through an unused dedicated terminal, (b) JEDEC (Joint Electr
WCBR mode (WE and CAS bef) standardized by on Devices Engineering Council
ore RAS mode), that is, RAS (Row Address Stor
obe) When the WE (Write Enable) signal and the CAS (Column Address Storobe) signal are activated when the signal is activated, the test mode is entered (Nikkei Microdevices Supplement 1987, NO. (See 183-196) Option to generate on-chip based on address key code input, (c) Any terminal (may be used during normal operation) Voltage in range not used during normal operation (For example, the power supply potential Vcc
Is input when 5 V is applied, and (d) a method of inputting signals to a plurality of terminals used during normal operation in an order relationship not used during normal operation.

In the above embodiment, a voltage stress test at the time of burn-in has been described as an example. However, it goes without saying that the present invention is also effective when a voltage stress test is performed irrespective of temperature acceleration.

[0052]

As described above, according to the present invention, it is possible to provide a semiconductor memory device capable of applying a voltage higher than a power supply voltage to a word line and reducing a chip area.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a part of a semiconductor memory device considered during the present invention.

FIG. 2 is a circuit diagram showing a semiconductor memory device according to a first embodiment of the present invention.

FIG. 3 is a diagram showing a part of another semiconductor memory device considered during the present invention;

FIG. 4 is a diagram showing a part of another semiconductor memory device considered during the present invention;

FIG. 5 is a circuit diagram showing a semiconductor memory device according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a semiconductor memory device according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a part of a semiconductor memory device currently proposed.

FIG. 9 is a circuit diagram showing a part of a semiconductor memory device which is also currently proposed.

[Explanation of symbols]

15: Cell transistor (NMOS transistor), W
L: word line, BL: bit line, 31: bonding pad for address, 32: pad for stress test signal, 3
3 ... Address amplification circuit, 34 ... Control circuit, 40, 50 ...
Word line selection circuit, 41, 51 ... word line drive circuit, 4
2: Word line drive voltage source, 43: Word line drive MO
S transistor (PMOS transistor), 48: bit line voltage application circuit, 61: pad for applying word line drive voltage, 62: switching circuit, 70: control circuit.

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁶ Identification symbol FI G01R 31/28 B (56) References JP-A-2-240897 (JP, A) JP-A-62-20198 (JP, A) JP-A-63-292485 (JP, A) JP-A-63-133391 (JP, A) JP-A-64-52300 (JP, A) JP-A-62-150600 (JP, A) (58) (Int.Cl. ⁶ , DB name) G11C 29/00 G11C 11/407 G01R 31/28 G01R 31/30 H01L 21/66

Claims (2)

(57) [Claims] A plurality of memory cells arranged in a matrix; a plurality of word lines connected to memory cells in the same row; a plurality of bit lines connected to memory cells in the same column; A word line drive voltage source that includes a booster circuit that boosts a given power supply voltage and outputs a word line drive voltage that has a boosted power supply voltage; a plurality of word line selection circuits that select the plurality of word lines; A plurality of word line driving circuits supplied with corresponding outputs of a plurality of word line selection circuits and driving the plurality of word lines
And multiple address pads to which external address signals are input
When, is input to the plurality of address pads during normal operation
Selecting the plurality of word lines according to the external address signal
Supply an internal address signal to the circuit and perform a voltage stress test.
Selected during normal operation according to the external address signal.
The multiple words to select more rows than
Address system that supplies the internal address signal to the gate line selection circuit
A plurality of word line selection circuits, each of which has a source to which the word line driving voltage is applied during word line driving.
A channel-type first MOS transistor, and a source / drain connected in series between a drain of the first MOS transistor and a ground potential, and a voltage amplitude value different from the word line driving voltage. A plurality of N-channel type second MOS transistors whose address signals are supplied to a gate; wherein each of the plurality of word line driving circuits has a source to which the word line driving voltage is applied when the word line is driven, A third MOS transistor of a P-channel type connected to the corresponding word line, a source / drain connected between a drain of the third MOS transistor and a ground potential, and a gate connected to the third MOS transistor of
Gate and the common gate
The first MOS transistor in the word line selecting circuit
A fourth MOS transistor of an N-channel type controlled based on the potential of the drain of the first MOS transistor. The gates of the first MOS transistors in the plurality of word line selection circuits are connected in common. First MO
The S transistor is controlled by a precharge signal in which one voltage value of the signal is equal to the word line driving voltage.
A semiconductor memory device characterized by being performed . 2. The address control circuit according to claim 1 , wherein said external address signal is input to said plurality of address pads.
And outputs complementary internal address signals.
And a plurality of address amplifier circuits for controlling the voltage stress test
And a stress test signal pad to which the signal is input and connected to the output sides of the plurality of address amplifier circuits, respectively.
During normal operation.
Output the complementary internal address signal to
During the test, the complementary internal address signal is
Normal operation according to the voltage stress test control signal.
From the row selected at the time of operation according to the external address signal
Outputs the internal address signal to select many rows
And a gate circuit group that performs
2. The semiconductor memory device according to claim 1, wherein: