KR20050045445A - Driving circuit of liquid crystal display device - Google Patents

Abstract

The present invention relates to a driving circuit of a liquid crystal display device in which a voltage required for driving a TFT is selectively applied regardless of the type of liquid crystal panel so as to be shared by workers, and a plurality of gate lines and data lines are perpendicular to each other. A liquid crystal panel having pixel regions for each crossing point, a gate driver for sequentially driving gate lines of the liquid crystal panel, a data driver for supplying video data to data lines of the liquid crystal panel, and the gate driver And a switching unit configured to output one of different first and second voltages to the gate line in response to a gate driving pulse signal of the gate driver.

Description

Driving circuit of liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit of a liquid crystal display device, and more particularly, to a driving circuit of a liquid crystal display device that enables common use for each worker.

In general, a liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal.

Among the liquid crystal display devices, an active matrix type in which switching elements are provided for each liquid crystal cell is suitable for displaying a moving image. In an active matrix liquid crystal display device, a thin film transistor (hereinafter, referred to as TFT) is mainly used as a switching element.

Hereinafter, a driving circuit of a liquid crystal display according to the prior art will be described with reference to the accompanying drawings.

1 is an exploded perspective view illustrating a part of a general liquid crystal display device.

As shown in FIG. 1, the lower substrate 1 and the upper substrate 2 bonded to each other with a predetermined space, and the liquid crystal layer 3 injected between the lower substrate 1 and the upper substrate 2 are composed of. It is.

More specifically, the lower substrate 1 has a plurality of gate lines 4 arranged in one direction at regular intervals to define the pixel region P, and in a direction perpendicular to the gate lines 4. A plurality of data lines 5 are arranged at regular intervals, and pixel electrodes 6 are formed in each pixel region P where the gate lines 4 and the data lines 5 intersect, and each of the gate lines The thin film transistor T is formed at the portion where (4) and the data line 5 intersect.

The upper substrate 2 includes a black matrix layer 7 for blocking light in portions other than the pixel region P, an R, G, and B color filter layer 8 for expressing color colors, and an image. The common electrode 9 is formed to implement the.

The thin film transistor T may include a gate electrode protruding from the gate line 4, a gate insulating film (not shown) formed on a front surface, an active layer formed on the gate insulating film above the gate electrode, and the data. A source electrode protruding from the wiring 5 and a drain electrode are provided so as to face the source electrode.

The pixel electrode 6 uses a transparent conductive metal having a relatively high light transmittance, such as indium-tin-oxide (ITO).

In the liquid crystal display device configured as described above, the liquid crystal layer 3 positioned on the pixel electrode 6 is aligned by a signal applied from the thin film transistor T, and the liquid crystal layer 3 is aligned with the alignment degree of the liquid crystal layer 3. Accordingly, the image can be expressed by controlling the amount of light passing through the liquid crystal layer 3.

As described above, the liquid crystal panel drives the liquid crystal by an electric field applied up and down, and has excellent characteristics such as transmittance and aperture ratio, and the common electrode 9 of the upper substrate 2 serves as a ground to discharge static electricity. It is possible to prevent the destruction of the liquid crystal cell.

2 is a schematic diagram illustrating a driving circuit of a general liquid crystal display device.

As shown in FIG. 2, the plurality of gate lines G and the data lines D are arranged in a direction perpendicular to each other and have a matrix-shaped pixel region, and the liquid crystal panel 21 is disposed on the liquid crystal panel 21. The driving circuit unit 22 supplies a driving signal and a data signal, and a backlight 28 providing a constant light source to the liquid crystal panel 21.

Here, the driving circuit part 22 may be gated to the data driver 21b for inputting a data signal to each data line D of the liquid crystal panel 21 and the gate line G of the liquid crystal panel 21. A gate driver 21a for applying a driving pulse signal, display data R, G, and B input from the driving system 27 of the liquid crystal panel, vertical and horizontal synchronization signals Vsync, Hsync, and a clock signal DCLK. A timing controller that receives a control signal and formats and outputs each display data, a clock, and a control signal at a timing suitable for each data driver 21b and the gate driver 21a of the liquid crystal panel 21 to reproduce a screen. 23), the power supply unit 24 for supplying the required voltage to the liquid crystal panel 21 and the respective parts, and digital data input from the data driver 21b by receiving power from the power supply unit 24. A constant voltage VDD and a gate high voltage used in the liquid crystal panel 21 using the gamma reference voltage unit 25 for supplying a reference voltage necessary for conversion into log data, and a voltage output from the power supply unit 24. And a DC / DC converter 26 for outputting VGH, a gate low voltage VGL, a reference voltage Vref, a common voltage Vcom, and an inverter 29 for driving the backlight 28. It is composed.

The operation of the driving circuit of the conventional liquid crystal display device configured as described above is as follows.

That is, the timing controller 23 inputs control signals such as display data (R, G, B) and vertical and horizontal synchronization signals (Vsync, Hsync) and a clock signal (DCLK) input from the driving system 27 of the liquid crystal panel. In response, the data driver 21b and the gate driver 21a of the liquid crystal panel 21 provide each display data, a clock, and a control signal at a timing suitable for reproducing the screen, so that the gate driver 21a provides the liquid crystal. A gate driving pulse signal is applied to each gate line G of the panel 21, and the data driver 21b inputs a data signal to each data line D of the liquid crystal panel 21 in synchronization with the gate driving pulse signal. Display the video signal.

At this time, the backlight 28 provides a backlight having a constant brightness regardless of the brightness of the input video signal.

3 is a schematic diagram illustrating a driving circuit of a conventional liquid crystal display, and FIG. 4 is a timing diagram illustrating a gate driving pulse signal output from the gate driver of FIG. 3.

As shown in FIG. 3, a liquid crystal panel 31 having a plurality of pixel regions at intersections of a plurality of gate lines GL and data lines DL, and a data line DL of the liquid crystal panel 31. The data driver 32 provides an image signal to each pixel area through the gate driver 33, and a gate driver 33 which sequentially selects and drives the gate line GL of the liquid crystal panel 31.

The pixel region includes a thin film transistor T having a gate terminal connected to the gate line GL and a source terminal connected to the data line DL, and a storage capacitor connected in parallel with the drain terminal of the thin film transistor T, respectively. Cst) and liquid crystal capacitors (Cls).

The operation of the driving circuit of the conventional liquid crystal display device configured as described above is as follows.

First, when all data values output from the data driver 32 are applied to the data lines # D1, # D2, ..., #Dn, a gate driving pulse signal from the gate driver 33 is applied to each gate line #. High voltages VGH are sequentially applied to each of G1, # G2, ..., #Gn.

In this case, the low voltage VGL is applied to the gate line to which the high voltage VGH is not applied, and the data applied to the data line is not output since the thin film transistor connected to the gate line does not operate.

That is, the data driver 32 sequentially receives a video signal of one pixel and outputs a video signal corresponding to a data line. The gate driver 33 sequentially selects one gate line from among a plurality of gate lines by outputting a gate driving pulse signal.

Subsequently, the plurality of thin film transistors T connected to the selected gate line are turned on and the video signals stored from the data driver 32 are applied to the drain terminals of the thin film transistors T, thereby displaying the video signals on the liquid crystal panel 31. do. Thereafter, the above operation is repeated to display the video signal on the liquid crystal panel 31.

The output voltage of the gate driver 33 is the same as the voltage input to the gate line GL of the liquid crystal panel 31.

Here, the high voltage VGH of the gate driving pulse signal output from the gate driver 33 is about 15-20V, and the low voltage VGL uses -5V. This depends on the characteristics of the liquid crystal panel 31, and also slightly differs depending on the circuit manufacturer.

However, the driving circuit of the conventional liquid crystal display device as described above has the following problems.

That is, since the output voltage of the gate driving circuit is the same as the input voltage of the gate line of the liquid crystal panel, the voltage driving the TFT of the liquid crystal panel varies slightly depending on the characteristics of the liquid crystal panel and the makers of the various circuits, thereby making it impossible to use the gate voltage. Do. At this time, the gate high voltage VGH of the gate driving circuit is about 15 to 20V, and the gate low voltage VGL is -5V.

The present invention has been made to solve the above problems, by applying a voltage for driving the thin film transistor (TFT) of the liquid crystal panel from the outside of the gate driving circuit selects only the voltage required for driving the TFT regardless of the type of liquid crystal panel It is an object of the present invention to provide a driving circuit of a liquid crystal display device which is applied by the operator to enable common use for each worker.

The driving circuit of the liquid crystal display according to the present invention for achieving the above object is a liquid crystal panel having a plurality of gate lines and data lines arranged in a direction perpendicular to each other having a pixel region for each intersection point, the gate of the liquid crystal panel A gate driver for sequentially driving the lines, a data driver for supplying video data to the data lines of the liquid crystal panel, and an output terminal of the gate driver and input from the outside according to a gate driving pulse signal of the gate driver And a switching unit for outputting any one of different first and second voltages to the gate line.

Hereinafter, a driving circuit of the liquid crystal display according to the present invention will be described with reference to the accompanying drawings.

5 is a schematic configuration diagram showing a driving circuit of the liquid crystal display according to the present invention.

As illustrated in FIG. 5, a plurality of gate lines GL and data lines DL are arranged in a direction perpendicular to each other to have a pixel region for each crossing point, and the liquid crystal panel 51 of the liquid crystal panel 51. A gate driver 52 which receives a control signal from each outside on each gate line GL and sequentially outputs a gate driving pulse signal, and is formed between an output terminal of the gate driver 52 and each gate line GL, And a switching unit 53 for applying one of different input first and second voltages to the gate line GL according to the gate driving pulse signal.

Here, the switching unit 53 has a gate terminal connected to the gate driving pulse signal output from the gate driver 52 in common, a source terminal connected in common, and a different first voltage (positive voltage) to each drain terminal. VGH and a second voltage (negative voltage) VGL are applied to the PMOS transistor 53a and the NMOS transistor 53b.

In addition, the drain terminal of the PMOS transistor 53a is connected to the second voltage VGL, and the drain terminal of the NMOS transistor 53b is connected to the first voltage VGH.

Here, the liquid crystal panel 51 is a liquid crystal is injected between the two glass substrate, the gate line GL and the data line DL is formed on the lower glass substrate to be orthogonal to each other. A thin film transistor T for selectively supplying an image input from the data line DL to the storage capacitor Cst and the liquid crystal capacitor Clc is formed at an intersection of the gate line GL and the data line DL. do.

Meanwhile, the non-described data driver 54 is for supplying video data to the data lines DL of the liquid crystal panel 51. The data driver 54 converts the digital video data into analog data to the data lines DL by one line. Will be supplied.

In the driving circuit of the liquid crystal display according to the present invention configured as described above, the PMOS transistor 53a is turned on in response to a gate driving pulse signal to output a negative voltage VGL to the gate line GL, and the NMOS transistor 53b. Is turned on to apply a positive voltage VGH to the gate line GL.

6 is a waveform diagram illustrating driving of a switching unit according to a gate driving pulse signal output from a gate driver.

As shown in FIG. 6, only the positive voltage VGH and the negative voltage VGL input from the outside through the PMOS transistor 53a and the NMOS transistor 53b constituting the switching unit 53 are selectively gated. It is applied to the gate terminal of the thin film transistor T connected to the GL.

First, when the gate driving pulse signal # G1 of the gate driver 52 is high, the PMOS transistor 53a is turned off and the NMOS transistor 53b is turned on so that the first voltage VGH is a positive voltage. It is applied to this gate line GL.

On the contrary, when the gate driving pulse signal # G1 of the gate driver 52 is low, the NMOS transistor 53b is turned off and the PMOS transistor 53a is turned on, so that the second voltage VGL is a negative voltage. It is applied to this gate line GL.

Subsequently, when the next gate driving pulse signal # G2 of the gate driver 52 is applied, the NMOS transistor 53b and the PMOS transistor 53a are selectively turned on so that the first voltage VGL and the negative voltage, which are positive voltages, are selectively turned on. The second voltage VGL is applied to the gate line GL.

Therefore, although the voltage and method applied to each gate line GL are the same as in the related art, the output of the gate driving pulse signals # G1, # G2, ..., #Gn output from the gate driver 52 turns on the thin film transistor. Only a level that can be turned on / off is required, which simplifies IC manufacturing and can be used in common.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

As described above, the driving circuit of the liquid crystal display according to the present invention has the following effects.

First, by outputting only the positive and negative driving voltages of the output voltages of the gate driving circuits, voltages varying depending on the characteristics of the liquid crystal panel and the makers of the circuits can be shared.

Second, the manufacturing process of the driving circuit can be simplified by not using a high voltage to drive the TFT.

Third, since the gate driving circuit can be shared among circuit makers, the cost of the driving circuit can be reduced.

1 is an exploded perspective view showing a part of a general liquid crystal display device

2 is a schematic diagram illustrating a driving circuit of a general liquid crystal display device;

3 is a schematic configuration diagram showing a driving circuit of a conventional liquid crystal display device;

4 is a timing diagram illustrating a gate driving pulse signal output from the gate driver of FIG. 3.

5 is a schematic configuration diagram showing a driving circuit of a liquid crystal display according to the present invention.

6 is a waveform diagram illustrating driving of a switching unit according to a gate driving pulse signal output from a gate driver;

Explanation of symbols for the main parts of the drawings

51 liquid crystal panel 52 gate driver

53: switching unit 54: data driver

Claims (3)

A liquid crystal panel in which a plurality of gate lines and data lines are arranged in a direction perpendicular to each other and having pixel regions at each crossing point; A gate driver for sequentially driving gate lines of the liquid crystal panel; A data driver for supplying video data to data lines of the liquid crystal panel; And a switching unit configured at an output terminal of the gate driver and outputting one of different first and second voltages to the gate line in response to a gate driving pulse signal of the gate driver. Drive circuit of the device. The NMOS transistor of claim 1, wherein the switching unit comprises a PMOS transistor and an NMOS transistor connected to a gate terminal in common with the gate driving pulse signal, a source terminal as a common output terminal, and each drain terminal connected to a first voltage and a second voltage. A driving circuit for a liquid crystal display device, characterized in that. The driving circuit of claim 1, wherein the drain terminal of the PMOS transistor is connected to a second voltage, and the drain terminal of the NMOS transistor is connected to a first voltage.