KR20050040962A - Plasma display panel - Google Patents

Abstract

The present invention discloses a plasma display panel. According to the present invention, a front substrate provided with sustain electrodes arranged at a predetermined interval; A front dielectric layer filling the sustain electrodes; A rear substrate disposed to face the front substrate and provided with address electrodes formed in a direction crossing the sustain electrodes; A back dielectric layer filling the address electrodes; Barrier ribs formed between the front substrate and the rear substrate to partition discharge spaces; Red, green, and blue phosphor layers formed in the discharge spaces, wherein the front dielectric layer is formed by sequentially stacking first, second, and third dielectric layers having different dielectric constants from the front substrate, and the front dielectric layer is red. In the red, green, and blue discharge spaces in which the phosphor layers of green and blue are formed, the thicknesses of the front dielectric layers corresponding to the respective regions are different from each other.

Description

Plasma display panel {Plasma display panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel. The present invention relates to a plasma display panel having an improved structure so as to optimize address voltage margins of red, green, and blue phosphors, and to secure breakdown voltages.

In general, a plasma display panel applies a predetermined voltage to an electrode while a gas is charged between two electrodes installed in an enclosed space so that a glow discharge occurs and the ultraviolet rays generated during the glow discharge are generated. As a result, the phosphor layer formed in a predetermined pattern is excited to form an image.

The plasma display panel is classified into a direct current type, an alternating current type, and a mixed type according to a driving method. And, depending on the electrode structure, it is divided into having at least two electrodes required for discharge and having three electrodes. In the case of the direct current type, an auxiliary anode is added to induce the auxiliary discharge. In the case of the alternating current type, an address electrode is introduced to separate the selective discharge and the sustain discharge to improve the address speed.

In addition, the AC type may be classified into a counter electrode and a surface discharge electrode structure according to the arrangement of the electrodes for discharging. In the case of the counter electrode structure, the two sustain electrodes forming the discharge are respectively the front substrate and the back substrate. The surface discharge type electrode structure is a structure in which the discharge is formed on one plane of the substrate because two sustain electrodes forming the discharge are positioned on the same substrate.

An example of a conventional plasma display panel is shown in FIG. 1.

Referring to the drawings, the front substrate 11 is positioned on the upper side of the plasma display panel 10, and the lower surface of the front substrate 11 has a constant width and height, and a pair of holding electrodes each consisting of a common electrode and a scan electrode. Electrodes 12 are formed.

Bus electrodes 13 for applying a voltage are formed on the bottom surfaces of the sustain electrodes 12, respectively. The sustain electrodes 12 and the bus electrodes 13 are embedded by a transparent front dielectric layer 14, and a protective layer 15 is formed on a bottom surface of the front dielectric layer 14. Here, the front dielectric layer 14 is formed on the front substrate 11 with a uniform thickness.

In addition, the rear substrate 21 of the front substrate 11 is disposed to face each other, and the address electrodes 22 having a predetermined width and height are formed on the rear substrate 21. The address electrodes 22 are embedded by the back dielectric layer 23.

In addition, barrier ribs 24 are formed on the rear dielectric layer 23 to partition discharge spaces 25 and prevent cross-talk between adjacent discharge spaces 25. Discharge gas is filled in the discharge spaces 25, and a phosphor layer 26 is formed as one of red, green, and blue phosphors in each of the discharge spaces 25 to implement a color.

On the other hand, the threshold voltage of the address voltage is different depending on the color of the phosphor, because the energy required to generate light in the phosphor is different depending on the color of the phosphor.

Typically, the same address voltage is applied for addressing irrespective of the color of the phosphor, so that the address voltage margin is different for each phosphor. When the address voltage is applied based on the phosphor having the smallest address voltage margin, an unnecessary high address voltage is applied to the remaining phosphor layers, resulting in an increase in power consumption due to an excessive load on the driving circuit. .

In this regard, there is a plasma display panel disclosed in Japanese Patent Laid-Open No. 8-250029. According to the disclosed structure, the dielectric thickness in the non-discharge region where the bus electrode is disposed is increased to be larger than the dielectric thickness in the discharge region, thereby suppressing the discharge into the bus electrode, thereby reducing the load on the driving circuit and reducing power consumption while discharging It is designed to increase efficiency.

The present invention is to solve the above problems, by configuring the front dielectric layer different thickness and dielectric constant of the front dielectric layer for each discharge space of red, green, and blue, to optimize the address voltage margin for each phosphor to reduce the load of the driving circuit It is an object of the present invention to provide a plasma display panel capable of securing a predetermined withstand voltage and reducing power consumption.

Plasma display panel according to the present invention for achieving the above object,

A front substrate provided with sustain electrodes arranged at predetermined intervals;

A front dielectric layer filling the sustain electrodes;

A rear substrate disposed to face the front substrate, the rear substrate having address electrodes formed in a direction crossing the sustain electrodes;

A back dielectric layer filling the address electrodes;

Barrier ribs formed between the front substrate and the rear substrate to partition discharge spaces;

And red, green, and blue phosphor layers formed in the discharge spaces.

The front dielectric layer is formed by sequentially stacking first, second, and third dielectric layers having different dielectric constants from the front substrate, and the front dielectric layer is formed of red, green, and blue phosphor layers in which the red, green, and blue phosphor layers are formed. The thicknesses of the front dielectric layers corresponding to the respective areas of the discharge spaces are formed to be different from each other.

The thickness of the front dielectric layer in a region corresponding to each of the red, green, and blue discharge spaces is preferably set in inverse proportion to the threshold voltage of the address voltage for each phosphor of the red, green, and blue colors.

The thickness of the front dielectric layer in each of the regions corresponding to the red, green, and blue discharge spaces is preferably set to optimize the address voltage margin with respect to the remaining phosphors based on the phosphor having the lowest threshold voltage. Do.

Preferably, the dielectric constant of the second dielectric layer is set to be larger than that of the first dielectric layer, and the dielectric constant of the third dielectric layer is set to be larger than that of the second dielectric layer.

Plasma display panel according to the present invention,

A front substrate provided with sustain electrodes arranged at predetermined intervals;

A front dielectric layer filling the sustain electrodes;

A rear substrate disposed to face the front substrate, the rear substrate having address electrodes formed in a direction crossing the sustain electrodes;

A back dielectric layer filling the address electrodes;

Barrier ribs formed between the front substrate and the rear substrate to partition discharge spaces;

And red, green, and blue phosphor layers formed in the discharge spaces.

The front dielectric layer is patterned so that the thickness and dielectric constant of the front dielectric layer corresponding to each upper region thereof are different in red, green, and blue discharge spaces in which the red, green, and blue phosphor layers are formed. do.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 and 3 illustrate a plasma display panel according to a first embodiment of the present invention.

The illustrated plasma display panel 100 basically includes a front substrate 111 made of glass or a transparent material and a rear substrate 121 disposed to face the front substrate 111.

Under the front substrate 111, sustain electrodes 112 and bus electrodes 113 are formed. The sustain electrode 112 may be formed on a bottom surface of the front substrate with a transparent conductive material, for example, an ITO film. Each of the sustain electrodes 112 has a structure in which protrusions are formed to extend from the body portion at predetermined intervals. On the other hand, the sustain electrode is not limited thereto and may be formed in various shapes, for example, may be formed in a strip shape.

The sustain electrodes 112 may include the common electrodes 112a and the scan electrodes 112b. The common electrode 112a and the scan electrode 112b form a pair, and they are alternately arranged. In addition, the protrusions may be disposed to face the common electrode 112a and the scan electrode 112b to be spaced apart from each other by a predetermined discharge gap.

The lower surface of each of the sustain electrodes 112 has a width smaller than that of the sustain electrodes 112, and a bus electrode 113 made of a conductive material is formed in parallel with the sustain electrodes 112. Here, the bus electrode 113 may be formed of a metal material having excellent conductivity, for example, a conductive material mainly composed of silver paste. On the other hand, the bus electrode may be omitted, in this case, the sustain electrode also serves as the bus electrode.

The sustain electrodes 112 and the bus electrodes 113 are buried in the bottom surface of the front substrate 111 by the front dielectric layer 114 according to an aspect of the present invention. Details of the front dielectric layer 114 will be described later.

Meanwhile, a protective layer 115, for example, a magnesium oxide (MgO) film, is further formed on the bottom surface of the front dielectric layer 114.

In addition, the rear substrate 121 is disposed to face the front substrate 111.

Address electrodes 122 are formed on the top surface of the back substrate 121, and the address electrodes 122 are buried by the back dielectric layer 123.

The address electrodes 122 are formed in a strip shape that intersects the bus electrodes 113 and are spaced apart at predetermined intervals.

Meanwhile, the partition walls 124 are formed on the upper surface of the rear dielectric layer 123 to be spaced apart from each other. The partition walls 124 partition the discharge spaces 130 between the front substrate 111 and the rear substrate 121.

In more detail, the barrier ribs 124 have a predetermined height and width, and are formed in parallel with the address electrodes 122. In addition, one address electrode 122 is disposed between the two partition walls 124. In addition, the common electrode 112a and the scan electrode 112b of the sustaining electrode 112 are formed in each of the discharge spaces 130 to be disposed to have a predetermined discharge gap by the protrusions. Lose. Meanwhile, the barrier ribs are not limited to those shown in the drawing, and may be any structure that can partition the discharge spaces into an array pattern of pixels. For example, the discharge spaces may be partitioned in a matrix by partitions.

The phosphor layers 125 are formed in the discharge spaces 130 partitioned by the partition walls 124, respectively.

The phosphor layer 125 uses red, green, and blue phosphors for color implementation, and red phosphor layer 125R, green phosphor layer 125G, and blue phosphor layer (depending on the color of the phosphor). 125B). Accordingly, the discharge space 130 may also be divided into a red discharge space 130R, a green discharge space 130G, and a blue discharge space 130B. The red, green, and blue discharge spaces 130R, 130G, and 130B are disposed adjacent to each other, as shown in FIG. 3, to form a pair of three colors.

Meanwhile, in the red, green, and blue discharge spaces 130R, 130G, and 130B divided by the color of the phosphor as described above, according to one feature of the present invention, the red, green, and blue discharge spaces are provided. The thickness of the front dielectric layer 114 located in each upper region of the 130R, 130G, and 130B is formed differently. For convenience of description, the front dielectric layer corresponding to the red discharge space 130R is called the red front dielectric layer 114R, and the front dielectric layer corresponding to the green discharge space 130G is called the green front dielectric layer 114G. When the front dielectric layer corresponding to the blue discharge space 130B is the blue front dielectric layer 114B, the red front dielectric layer 114R, the green front dielectric layer 114G, and the blue front dielectric layer 114B are used. In each of the thicknesses are different from each other.

In general, the thinner the thickness of the front dielectric layer 114 is advantageous to discharge, and has a characteristic of lowering the threshold voltage of the address voltage required to excite the phosphor.

Therefore, by using this characteristic, it is possible to optimize the address voltage margin for each color of the phosphor. Here, the address voltage margin of the phosphor may be defined as the difference between the address voltage and the threshold voltage of the minimum address voltage capable of exciting the phosphor.

For example, when the threshold voltage of the address voltage is small in the order of the red phosphor, the green phosphor, and the blue phosphor, the threshold voltages of the red phosphor and the green phosphor are based on the blue phosphor having the lowest threshold voltage. When each is lowered, all of the phosphors can be excited even if the address voltage is lower than the conventional one based on the blue phosphor. Therefore, the address voltage margin can be optimized for each color of the phosphor with respect to the applied address voltage.

In order to optimize the address voltage margin for each color of the phosphor as described above, as shown in FIGS. 3 and 4, the thickness of the green front dielectric layer 114G is made thin, based on the thickness of the blue front dielectric layer 114B. The thickness of the front dielectric layer 114R is the thinnest.

More specifically, the front dielectric layer 114 has a structure in which the first, second and third dielectric layers 141, 142 and 143 are sequentially stacked from the front substrate 111, and have red, green, and blue discharges. The stacked structure is different for each area corresponding to the spaces 130R, 130G, and 130B. Accordingly, patterns of the front dielectric layer 114 corresponding to the red, green, and blue discharge spaces 130R, 130G, and 130B are respectively formed.

As shown, the red front dielectric layer 114R includes only the first dielectric layer 141, and the green front dielectric layer 114G includes the first and second dielectric layers 141 and 142 stacked thereon. The blue front dielectric layer 114B has a structure in which first, second and third dielectric layers 141, 142 and 143 are stacked.

An example of a method of forming the front dielectric layer 114 with respect to the front substrate 111 will be described below.

First, the thickness of the front dielectric layer 114 is set for each of red, green, and blue phosphors, and based on this, the height is uniform on the bottom surface of the front substrate 111 by the thickness corresponding to the set thickness of the front dielectric layer 114R for red. The first dielectric layer 141 is formed. After the first dielectric layer 141 is formed as described above, the second dielectric layer 142 is stacked on the first dielectric layer 141 at a uniform height corresponding to the thickness of the set green front dielectric layer 114G. Next, the second dielectric layer has a uniform height with respect to the region corresponding to the thickness of the set red front dielectric layer 114R and the region corresponding to the upper region of the red discharge space 130R and the upper surface of the partition walls 124. By stacking the third dielectric layer 143 with respect to 142, the front dielectric layer 114 according to an embodiment of the present invention may be formed.

By having the front dielectric layer 114 having a different thickness of the front dielectric layer 114 as described above, the threshold voltages of the remaining phosphors are appropriately adjusted based on the threshold voltage of the lowest phosphor in the address voltage. This makes it possible to apply a lower address voltage than before.

In general, the threshold voltage of the address voltage is closely related to the dielectric constant as well as the thickness of the front dielectric layer. That is, the higher the dielectric constant, the lower the threshold voltage of the address voltage. Therefore, when the front dielectric layer is formed of a dielectric having a high permittivity using this tendency, the threshold voltage of the address voltage for all the phosphors can be lowered, so that a lower address voltage can be applied. However, the higher the dielectric constant, the more favorable for the address voltage, but the withstand voltage tends to be lowered, so that the phenomenon that the front dielectric layer is destroyed during discharge may occur, thereby limiting the dielectric constant. In addition, as the thickness of the front dielectric layer becomes thinner, the withstand voltage tends to be lowered. Therefore, the thickness and the dielectric constant of the front dielectric layer should be optimally set to favor both the address voltage and the withstand voltage.

For the above reason, as an example of the present invention, in the first, second and third dielectric layers 141, 142 and 143 constituting the front dielectric layer 114, the first dielectric layer 141 and the second dielectric layer 142. ), Each of the dielectric constants may be set in the order of the third dielectric layer 143.

In more detail, since the red front dielectric layer 114R is formed to be the thinnest with only the first dielectric layer 141, the threshold voltage of the address voltage is lowered, so that the withstand voltage of the red over front dielectric layer 114R is the lowest. The lowering of the withstand voltage can be compensated by setting the dielectric constant of the first dielectric layer 141 to the lowest. When the dielectric constant of the first dielectric layer 141 is set to the lowest, the first dielectric layer is increased even though the threshold voltage of the address voltage is slightly increased. The withstand voltage of 141 may be increased. In this case, the dielectric constant of the first dielectric layer 141 may be set to an optimal value to favor both the address voltage and the withstand voltage.

In addition, the green front dielectric layer 114G is laminated with the first and second dielectric layers 141 and 142 and is thicker than the red front dielectric layer 114R. This is somewhat disadvantageous in terms of voltage, which can be compensated for by setting the dielectric constant of the second dielectric layer 142 higher than that of the first dielectric layer 141. That is, when the dielectric constant of the second dielectric layer 142 is set higher than the dielectric constant of the first dielectric layer 141, the withstand voltage is slightly lowered, but the threshold voltage of the address voltage can be reduced. In this case, the dielectric constant of the second dielectric layer 142 may be set to an optimal value to favor both the address voltage and the withstand voltage.

Similarly, the blue front dielectric layer 114B is laminated with the first, second and third dielectric layers 141, 142 and 143, and is thicker than the red front dielectric layer 114R and the green front dielectric layer 114G. Is more advantageous in terms of withstand voltage, but somewhat disadvantageous in terms of threshold voltage of the address voltage, which can be compensated by setting the dielectric constant of the third dielectric layer 143 to be higher than that of the second dielectric layer 142. In this case, the dielectric constant of the third dielectric layer 143 may be set to an optimal value to favor both the address voltage and the withstand voltage.

By setting the thickness and the dielectric constant of the front dielectric layer 114 as described above, it is possible to optimize the address voltage margin for each phosphor to reduce the load of the driving circuit and power consumption. In addition, it is possible to sufficiently ensure the withstand voltage of the front dielectric layer 114 corresponding to each phosphor.

4 shows a plasma display panel according to a second embodiment of the present invention. Like reference numerals in the drawings depicted above indicate like elements having the same function. Therefore, the detailed description of the same member is omitted in this embodiment, and the difference from the above-described first embodiment will be described in detail.

Referring to the drawings, in the plasma display panel 200 according to the present embodiment, the front dielectric layer 214 has a front dielectric layer in regions corresponding to the red, green, and blue discharge spaces 130R, 130G, and 130B, respectively. Each thickness of 214 is patterned differently. That is, the front dielectric layer 214 is formed to have a different thickness in each of the red front dielectric layer 214R, the green front dielectric layer 214G, and the blue front dielectric layer 214B. Unlike the above, the red front dielectric layer 214R, the green front dielectric layer 214G, and the blue front dielectric layer 214B are not stacked, respectively, but have a single layer.

When the threshold voltage of the address voltage is small in order of red phosphor, green phosphor, and blue phosphor, for example, red front dielectric layer 214R, green front dielectric layer 214G, and blue front dielectric layer 214B. It is preferable that the thickness is gradually increased.

According to one aspect of the present invention, the red front dielectric layer 214R, the green front dielectric layer 214G, and the green front dielectric layer 214B have different thicknesses, and the red front dielectric layer ( 214R, the blue front dielectric layer 214G, and the green front dielectric layer 214B are each made of a dielectric having different dielectric constants. In this case, the red front dielectric layer 214R, the green front dielectric layer 214G, and the blue front dielectric layer 214B are in proportion to the thickness of the red front dielectric layer 214R and the green front dielectric layer 214G. It is preferable that the dielectric constant increases in the order of the blue front dielectric layer 214B.

More specifically, since the red front dielectric layer 214R is formed to be the thinnest, the threshold voltage of the address voltage is lowered, which causes the withstand voltage to be the lowest. Can be. At this time, the dielectric constant of the red front dielectric layer 214R should be set to an optimal value to favor both the address voltage and the withstand voltage.

In addition, the green front dielectric layer 214G is thicker than the red front dielectric layer 214R, which is more advantageous in terms of withstand voltage, but is somewhat disadvantageous in terms of threshold voltage of the address voltage. To compensate for this, the dielectric constant of the green front dielectric layer 214G may be set higher than the dielectric constant of the red front dielectric layer 214R. When this is set, the withstand voltage may be slightly lowered, but the threshold voltage of the address voltage may be reduced. Will be. At this time, the dielectric constant of the green front dielectric layer 214G may be set to an optimal value to favor both the address voltage and the withstand voltage.

Similarly, the blue front dielectric layer 214B is thicker than the red front dielectric layer 214R and the green front dielectric layer 214G, which is more advantageous in terms of withstand voltage, but somewhat disadvantageous in terms of threshold voltage of the address voltage. However, this may be compensated by setting the dielectric constant of the blue front dielectric layer 214B to be higher than that of the green front dielectric layer 214G. At this time, the dielectric constant of the blue front dielectric layer 214B may be set to an optimal value to favor both the address voltage and the withstand voltage.

By optimizing the address voltage margin for each phosphor by setting the thickness and dielectric constant of the front dielectric layer 214 as described above, even if the address voltage is applied based on the phosphor having the smallest address voltage margin, it is not necessary for the remaining phosphor layers. Therefore, a high address voltage is not applied. Therefore, as compared with the related art, it is possible to reduce the load of the driving circuit and reduce the power consumption. In addition, it is possible to sufficiently secure the withstand voltage of the front dielectric layer 214 corresponding to each phosphor.

Meanwhile, in the above-described embodiments, the threshold voltage of the address voltage is illustrated in the order of the red phosphor, the green phosphor, and the blue phosphor. In the case where the address voltage is different for each phosphor according to the phosphor material, as described above, Changes will be made based on the content.

As described above, in the plasma display panel according to the present invention, the front dielectric layer thickness and the dielectric constant corresponding to each upper region of the red, green, and blue discharge spaces are configured differently, thereby optimizing the address voltage margin for each phosphor and withstanding voltage. Can be secured. Since a lower address voltage can be applied than before, the load of the driving circuit can be reduced, and the power consumption can be reduced.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Could be. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

1 is a partial cross-sectional view of a conventional plasma display panel.

2 is an exploded perspective view of the plasma display panel according to the first embodiment of the present invention;

3 is a partial cross-sectional view of the plasma display panel of FIG.

4 is a partial cross-sectional view of a plasma display panel according to a second embodiment of the present invention.

<Brief description of the major symbols in the drawings>

111. Front substrate 112. Holding electrode

113.Bus electrode 114,214.Front dielectric layer

121.Rear substrate 122.Address electrode

123. back dielectric layer 124 bulkhead

125. Phosphor layer 130. Discharge space

141. First dielectric layer 142 Second dielectric layer

143. 3rd dielectric layer

Claims (10)

A front substrate provided with sustain electrodes arranged at predetermined intervals; A front dielectric layer filling the sustain electrodes; A rear substrate disposed to face the front substrate, the rear substrate having address electrodes formed in a direction crossing the sustain electrodes; A back dielectric layer filling the address electrodes; Barrier ribs formed between the front substrate and the rear substrate to partition discharge spaces; And red, green, and blue phosphor layers formed in the discharge spaces. The front dielectric layer is formed by sequentially stacking first, second, and third dielectric layers having different dielectric constants from the front substrate, and the front dielectric layer is formed of red, green, and blue phosphor layers in which the red, green, and blue phosphor layers are formed. And a thickness of the front dielectric layer corresponding to each area of the discharge spaces is different from each other. The method of claim 1, And a thickness of the front dielectric layer in a region corresponding to each of the red, green, and blue discharge spaces is inversely proportional to a threshold voltage of the address voltage of each of the red, green, and blue phosphors. The method of claim 1, The thickness of the front dielectric layer in the regions corresponding to the red, green, and blue discharge spaces is set so that the address voltage margin is optimized for the remaining phosphors based on the phosphor having the lowest threshold voltage of the address voltage. Plasma display panel. The method according to any one of claims 1 to 3, And a dielectric constant of the second dielectric layer is greater than that of the first dielectric layer, and a dielectric constant of the third dielectric layer is larger than that of the second dielectric layer. The method of claim 1, And a protective layer is formed on the lower surface of the front dielectric layer. A front substrate provided with sustain electrodes arranged at predetermined intervals; A front dielectric layer filling the sustain electrodes; A rear substrate disposed to face the front substrate, the rear substrate having address electrodes formed in a direction crossing the sustain electrodes; A back dielectric layer filling the address electrodes; Barrier ribs formed between the front substrate and the rear substrate to partition discharge spaces; And red, green, and blue phosphor layers formed in the discharge spaces. The front dielectric layer is patterned so that the thickness and dielectric constant of the front dielectric layer corresponding to each upper region thereof are different in red, green, and blue discharge spaces in which the red, green, and blue phosphor layers are formed. Plasma display panel. The method of claim 6, And a thickness of the front dielectric layer in a region corresponding to each of the red, green, and blue discharge spaces is inversely proportional to a threshold voltage of the address voltage of each of the red, green, and blue phosphors. The method of claim 6, The thickness of the front dielectric layer in the regions corresponding to the red, green, and blue discharge spaces is set so that the address voltage margin is optimized for the remaining phosphors based on the phosphor having the lowest threshold voltage of the address voltage. Plasma display panel. The method according to any one of claims 6 to 8, And a dielectric constant of the front dielectric layer in a region corresponding to the red, green, and blue discharge spaces is proportional to the thickness in the region. The method of claim 6, And a protective layer is formed on the lower surface of the front dielectric layer.