KR20050033695A - Method for forming capacitor of semiconductor device - Google Patents

Abstract

A method for forming a capacitor of a semiconductor device is provided to stably grown HSGs(Hemispherical Silicon Grains) by using a relatively thick capacitor oxide layer. A silicon substrate(101) with an interlayer dielectric(102) having a landing plug(103) is prepared. An etch stop layer(104) is deposited on the interlayer dielectric. A capacitor oxide layer(105) is formed on the etch stop layer, wherein the thickness of the capacitor oxide layer is 20000-22000Å. By annealing, the thickness of the capacitor oxide layer is thinned to the thickness of 18000-20000Å, and carbons are removed. A trench(106) is formed to expose the landing plug by etching the capacitor oxide layer. A polysilicon layer(107) is deposited on the resultant structure. A lower electrode is formed by growing HSGs(108) on the polysilicon layer.

Description

Method for forming capacitor of semiconductor device

The present invention relates to a method of forming a capacitor of a semiconductor device, and more particularly, to a method of forming a capacitor of a semiconductor device capable of preventing a defect of a capacitor.

As the demand for semiconductor memory devices has soared, various techniques for obtaining high capacity capacitors have been proposed. The capacitor has a structure in which a dielectric film is interposed between capacitor electrodes called so-called storage electrodes and plate electrodes, the capacitance of which is proportional to the surface area of the electrode and the dielectric constant of the dielectric film and inversely proportional to the spacing between the electrodes. Therefore, in order to obtain a high capacity capacitor, it is essential to use a dielectric film having a high dielectric constant, to enlarge the surface area of the electrode, or to reduce the distance between the electrodes.

However, since there is a limitation in reducing the distance between electrodes, that is, the thickness of the dielectric film, researches for manufacturing a high capacity capacitor have been conducted by using a dielectric film having a high dielectric constant or by increasing the surface area of the electrode. . For example, using a tantalum oxide film (Ta ₂ O ₅ ) as the material of the dielectric film is one method of increasing the capacitor capacity by increasing the dielectric constant.

In addition, forming a capacitor electrode with a fin structure, a stack structure, a cylinder structure, and the like is one form of increasing the capacitance of the capacitor by increasing the surface area of the electrode.

In particular, among the above-described structures, since the cylinder structure has an advantage of securing a large electrode area by a relatively simple process, most capacitors are currently manufactured with such a cylinder structure.

In addition, as a technique for widening the surface area of an electrode, a growth process of hemispherical silicon grains (HSG) has recently been performed. The process of growing the hemispherical polycrystalline silicon grain is a process of increasing the surface area of the electrode by heat-treating the polysilicon film used as the material of the electrode to achieve crystal growth.

However, this hemispherical silicon grain process is very sensitive to the surrounding environment, so it is not easy to form an optimum state of hemispherical silicon grain.

In particular, PE-TEOS, which is the capacitor oxide film of the lower electrode that determines the height of the capacitor, for example, where the lower electrode polysilicon film is deposited, contains a carbon group, which prevents the formation of hemispherical silicon grains. Makes the setting of growth conditions difficult. Therefore, after depositing and patterning the capacitor oxide film, annealing is performed at a temperature of 700 ° C. or higher and N 2 atmosphere to remove the carbon group contained in PE-TEOS.

Thereafter, polysilicon, which is a lower electrode, is deposited, and heat treatment is performed to form hemispherical silicon grains. At this time, since the carbon group is removed, an optimal hemispherical silicon grain can be formed.

However, in spite of securing the filling capacity through the optimum hemispherical silicon grain, the filling capacity is not secured by the increase of the filling capacity by the hemispherical silicon grain, which is the PE-TEOS shrinkage by the annealing process, mentioned above. As can be seen, the PE-TEOS, which determines the height of the capacitor, is reduced by 9-11%, and the charge capacity is reduced by 9-11%, so that the charge capacity as intended to form the optimal hemispherical silicon grain cannot be obtained.

Therefore, in order to increase the height of the capacitor by 9 to 11%, the height of the PE-TEOS must be deposited by about 9 to 11% to compensate for shrinkage due to high temperature annealing.

However, PE-TEOS is 18,000 (1.8) ~ 20,000 to secure more than 25 ~ 28fF / Cell charge capacity required for Pseudo SRAM cell process with 0.14㎛ design rule. A height of 2.0 (2.0 μm) or more is required. In this case, an increase in the height of PE-TEOS, a capacitor oxide film material of 9-11%, becomes a burden in an etching process, which is a node formation process of a capacitor.

In the method of forming a capacitor according to the related art, a high temperature annealing process is performed to remove carbon groups contained in a capacitor oxide film that prevents formation of hemispherical silicon grains in order to secure filling capacity. However, such annealing causes the capacitor oxide film to shrink, resulting in a decrease in charge capacity.

Accordingly, an object of the present invention is to provide a method for forming a capacitor of a semiconductor device capable of stably forming polycrystalline silicon without reducing the surface area of the capacitor.

In order to achieve the above object, the present invention provides a step of providing a silicon substrate having an interlayer insulating film having a landing plug; Depositing an etch stop layer on the interlayer insulating layer including the plug; Forming a capacitor oxide film on the etch stop layer to a thickness of 20000 to 22000 kPa; Annealing the capacitor oxide film to remove carbon and simultaneously shrinking the thickness of the capacitor oxide film to a thickness of 18000 to 20000 kPa; Etching the capacitor oxide layer to form a trench that exposes the landing plug; Depositing a polysilicon film on the substrate resultant; Removing a polysilicon layer on an upper layer between the landing plugs: growing a hemispherical silicon grain on the polysilicon layer to form a lower electrode; Provided is a method of forming a capacitor in a semiconductor device comprising the step of sequentially forming a dielectric film and the upper electrode on the lower electrode.

Here, the annealing of the capacitor oxide film is carried out for 10 to 60 minutes at a temperature of 650 ~ 800 ℃, N2 atmosphere.

(Example)

1A to 1E are cross-sectional views for each process for explaining a method of forming a capacitor according to the present invention.

First, as shown in FIG. 1A, bit lines (not shown) including spacers (not shown) are formed on a silicon substrate 101 through a known manufacturing process, and then silicon on which the bit lines are formed is formed. An interlayer insulating film 102 is formed on the substrate 101, and a predetermined portion of the interlayer insulating film 102 is etched to form a contact hole defining an area in which a capacitor plug is to be formed by etching a portion of the interlayer insulating film 102. After that, a capacitor landing plug 103 is formed in the contact hole. Thereafter, a nitride film as a material of the anti-etching film 104 is formed on the interlayer insulating film 103 including the capacitor landing plug 203 to a thickness of 300 to 700 kPa at a temperature of 650 to 770 ° C.

Next, a PE-TEOS film is formed on the nitride film 104 as a capacitor oxide film 105 material. At this time, the thickness of the capacitor oxide film 105 is formed to be 9 to 11% thicker than the usual thickness, for example, 18000 ~ 20000Å in consideration of the subsequent annealing process.

Therefore, the thickness of the capacitor oxide film 105 is 19800-22000 kPa.

Referring to FIG. 1B, the capacitor oxide film 105 is annealed in an N 2 atmosphere at a temperature of 650 to 800 ° C. for 10 to 60 minutes. Accordingly, the carbon group of the capacitor oxide film is removed, and the capacitor oxide film is contracted in height to have a thickness of 18000 to 20000 kPa.

Here, the purpose of the annealing process is to remove the carbon group of the capacitor oxide film 105 in the process of growing the subsequent hemispherical silicon grains by the annealing because the carbon group interferes with the growth, and the annealing process is characterized in that Since it is 19800-22000 kPa, the etching process is difficult, so that the etching process proceeds prior to the deposition of the polysilicon, which is the next capacitor hard film material, thereby shrinking to a thickness of a common capacitor oxide film to facilitate the subsequent etching process.

Referring to FIG. 1C, a trench 106 may be formed by removing the capacitor oxide layer 105 and the etch stop layer 104 on the landing plug 103 so that the landing plug 103 is exposed. Then, a polysilicon film 107 is formed on the entire substrate.

Referring to FIG. 1D, a photosensitive film is coated to cover the polysilicon film 107, and then the polysilicon film 107 is exposed by etching back the photosensitive film in the top portion between the landing plugs 103. Next, the exposed polysilicon film 107 is removed to insulate the capacitors.

Referring to FIG. 1E, the polysilicon film 107 is heat-treated to grow hemispherical silicon grains 108.

Subsequently, although not shown, a dielectric film and an upper electrode are sequentially formed to form a capacitor of the semiconductor device.

In the conventional capacitor formation process, the carbon group of the capacitor oxide film is removed by annealing for stable growth of the hemispherical silicon grains.

However, the annealing process results in a reduction in the capacitor charge capacity due to the reduction of the capacitor oxide film. In the present invention, the capacitor oxide film is formed thick in consideration of the reduction in the annealing process to form the capacitor without reducing the surface area of the capacitor. It is possible to stably grow subsequent hemispherical silicon grains.

According to the present invention, in consideration of the reduction in the size of the capacitor oxide film due to annealing, by depositing the size of the capacitor oxide film thicker than the normal size, it is possible to stably grow hemispherical silicon grains without reducing the size of the capacitor oxide film.

Therefore, not only the charging capacity of the capacitor is secured but also the capacitor characteristics are improved.

In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

1A to 1E are cross-sectional views of processes for explaining a method of forming a capacitor of a semiconductor device according to the present invention.

* Description of the symbols for the main parts of the drawings *

101 silicon substrate 102 interlayer insulating film

103: landing plug 104: etching prevention film

105: capacitor oxide film 106: trench

107: polysilicon film 108: hemispherical silicon grain

Claims (2)

Providing a silicon substrate having an interlayer insulating film having a landing plug; Depositing an etch stop layer on the interlayer insulating layer including the plug; Forming a capacitor oxide film on the etch stop layer to a thickness of 20000 to 22000 kPa; Annealing the capacitor oxide film to remove carbon and simultaneously shrinking the thickness of the capacitor oxide film to a thickness of 18000 to 20000 kPa; Etching the capacitor oxide layer to form a trench that exposes the landing plug; Depositing a polysilicon film on the substrate resultant; Removing the polysilicon layer on the upper part of the landing plugs: Growing a hemispherical silicon grain on the polysilicon film to form a lower electrode; And sequentially forming a dielectric film and an upper electrode on the lower electrode. The method of claim 1, wherein the annealing of the capacitor oxide layer is performed at a temperature of 650 ° C. to 800 ° C. for 10 to 60 minutes in an N 2 atmosphere.