KR20050022624A - Method of manufacturing flash memory device - Google Patents

Abstract

PURPOSE: A method of manufacturing a flash memory device is provided to improve gate profile and CD(Critical Dimension) distribution within a peripheral region by patterning gates of the peripheral region using a hard mask instead of a photoresist pattern as an etching mask. CONSTITUTION: A first stack type structure and a second stack type structure are formed on a semiconductor substrate(100) with a cell and peripheral region. A stack gate structure composed of a floating gate, a coupling insulator and a control gate is formed within the cell region by patterning the first stack type structure using a first hard mask pattern(124a) as an etching mask. A second hard mask pattern(140a) for covering the stack gate structure and the second stack type structure is formed thereon. A single gate structure is formed within the peripheral region by patterning the second stack type structure using the second hard mask pattern as an etching mask.

Description

Method of manufacturing flash memory device {Method of manufacturing flash memory device}

The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a flash memory device having a memory cell transistor and a peripheral circuit transistor on the same substrate.

Recently, there is an increasing demand for electrically erasable and programmable ROM (EEPROM) or flash memory capable of electrically inputting and outputting data. Flash memory devices can be electrically erased and stored, and data can be preserved even when power is not supplied.

Flash memory devices are classified into NOR type and NAND type according to the structure of the memory cell. Among them, a Noah type flash memory device has a plurality of memory cells composed of a single transistor connected in parallel to one bit line, and has one between a drain connected to a bit line and a source connected to a public source line. It consists of a structure in which only memory cell transistors are connected.

The memory cell gate of the flash memory device has a structure in which a floating gate and a control gate are stacked with an interlayer dielectric layer interposed therebetween. The peripheral circuit gate has a single gate structure like the structure of a conventional semiconductor device.

1 to 5 are cross-sectional views illustrating a manufacturing method of a flash memory device according to the prior art, according to a process sequence.

Referring to FIG. 1, a gate insulating layer 12 and a conductive first polysilicon layer 14 are formed in a memory cell region and a peripheral circuit region on a semiconductor substrate 10 in which an active region is defined by an element isolation region (not shown). Form each. In the memory cell region, the gate insulating layer 12 serves as a tunneling insulating layer.

Then, an ONO (oxide-nitride-oxide) film having a stacked structure of an interlayer dielectric film 16, for example, an oxide film / nitride film / oxide film, on the first polysilicon layer 14 in a memory cell region and a peripheral circuit region, After the conductive second polysilicon layer 18 is sequentially formed, the second polysilicon layer 18 and the interlayer dielectric layer 16 are removed only in the peripheral circuit region by using an etching mask (not shown) covering only the memory cell region. do. As a result, the top surface of the first polysilicon layer 14 is exposed in the peripheral circuit region. Thereafter, the etching mask is removed to expose the top surface of the second polysilicon layer 18 in the memory cell region.

Referring to FIG. 2, a metal silicide layer 20, for example, a tungsten silicide (WSi _x ) layer is formed on a memory cell region and a peripheral circuit region. As a result, in the memory cell region, a laminated structure composed of the first polysilicon layer 14, the interlayer dielectric film 16, the second polysilicon layer 18, and the metal silicide layer 20 is obtained, and thus the peripheral circuit region is obtained. In this case, a laminated structure composed of the first polysilicon layer 14 and the metal silicide layer 20 is obtained.

Thereafter, the first antireflection film 22, the hard mask layer 24, and the second antireflection film 26 are sequentially formed on the memory cell region and the peripheral circuit region. For example, a SiON film is formed as the first antireflection film 22, a silicon oxide film is formed as the hard mask layer 24, and a SiON film is formed as the second antireflection film 26. Here, the first anti-reflection film 22 is an anti-reflection film required for gate patterning of the peripheral circuit region, and the second anti-reflection film 26 is an anti-reflection film required for gate patterning of the memory cell region.

Referring to FIG. 3, a hard mask pattern 24a to be used for gate patterning in the memory cell region is formed using the first photoresist pattern 30.

In more detail, the first photoresist pattern 30 is formed on the second anti-reflection film 26. The first photoresist pattern 30 completely covers the peripheral circuit area, and the second anti-reflection film 26 is exposed in the memory cell area so that the top surface of the second anti-reflection film 26 is exposed in the area where the conductive layer is to be removed. Partially covered.

The second anti-reflection film 26, the hard mask layer 24, and the first anti-reflection film 22 are sequentially etched in the memory cell area using the first photoresist pattern 30 as an etch mask to form a second anti-reflection film pattern. 26a, the hard mask pattern 24a and the first antireflection film pattern 22a are formed.

Referring to FIG. 4, after the first photoresist pattern 30 is removed, gate patterning is performed in the memory cell region using the hard mask pattern 24a as an etch mask. As a result, in the memory cell region, a floating gate composed of the first polysilicon pattern 14a, a coupling insulating layer composed of the interlayer dielectric layer pattern 16a, and the second polysilicon pattern 18a and a metal silicide pattern ( A structure in which control gates composed of 20a) are stacked in sequence is obtained. When the gate patterning, the second anti-reflection film pattern 26a exposed on the upper surface of the memory cell region and the peripheral circuit region is completely removed, and the hard mask pattern 24a is also consumed by a predetermined thickness from the upper surface to reduce the total thickness. Will be lowered.

Referring to FIG. 5, the second photoresist pattern 40 is formed to pattern the peripheral circuit region. The second photoresist pattern 40 completely covers the memory cell region, and partially exposes the hard mask pattern 24a so that the top surface of the hard mask pattern 24a is exposed in the region where the conductive layer is to be removed in the peripheral circuit region. Cover.

Gate patterning is performed in the peripheral circuit area using the second photoresist pattern 40 as an etching mask. As a result, a single gate structure composed of the first polysilicon pattern 16a and the metal silicide pattern 20a in the peripheral circuit region is obtained.

As described above, in the method of manufacturing a flash memory device according to the related art, gate patterning is performed using a hard mask pattern as an etch mask, and gate patterning is performed using a photoresist pattern as an etch mask in a peripheral circuit region. However, since the gate in the peripheral circuit region is basically larger in space between the adjacent gates than the gate width, the process margin is reduced during the photolithography process and a large amount of side slope occurs during dry etching. The result is a weak effect on the gate profile, CD (critical dimension) dispersion, and the like. It is necessary to reduce the thickness of the photoresist pattern in order to improve such photolithography process margin defects, but there is a limit in reducing the thickness of the photoresist pattern in consideration of the etching process margin.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art as described above, and to improve the distribution of gate profile, critical dimension (CD), etc. in the peripheral circuit area without affecting the memory cell area. The present invention provides a method of manufacturing a flash memory device capable of performing gate patterning.

In order to achieve the above object, in the method of manufacturing a flash memory device according to the present invention, a semiconductor substrate having a memory cell region and a peripheral circuit region is located in the memory cell region, and a first conductive layer, an interlayer dielectric layer, and a second conductive layer are sequentially formed. A first laminated structure laminated and a second laminated structure disposed in the peripheral circuit region and including a third conductive layer are formed on the semiconductor substrate. The first stacked structure is patterned in the memory cell region using a first hard mask pattern as an etch mask to form a stack gate structure including a floating gate, a coupling insulating layer, and a control gate. A second hard mask pattern is formed to cover the stack gate structure of the memory cell region and the second stacked structure of the peripheral circuit region. The second stacked structure is patterned in the peripheral circuit area using the second hard mask pattern as an etching mask to form a single gate structure.

Preferably, the first conductive layer of the first laminated structure is composed of a conductive first polysilicon layer, and the second conductive layer of the first laminated structure is a laminate of the conductive second polysilicon layer and the first metal silicide layer. It is composed of a structure. In addition, the interlayer dielectric film of the first laminated structure is composed of a laminated structure of an oxide film / nitride film / oxide film.

Also preferably, the third conductive layer of the second laminated structure may have a laminated structure of the conductive third polysilicon layer and the second metal silicide layer. Here, the first polysilicon layer and the third polysilicon layer may be simultaneously formed, and the first metal silicide layer and the second metal silicide layer may be simultaneously formed.

The first hard mask pattern and the second hard mask pattern may be formed of a silicon oxide layer.

After the stack gate structure is formed, the first hard mask pattern may remain on the stack gate structure and on the second stacked structure at a lower thickness. In this case, the second hard mask pattern is formed on the remaining first hard mask pattern.

The semiconductor substrate may include a source region and a drain region respectively formed between the stack gate structures in the memory cell region, and the second hard mask pattern may cover an upper surface of the semiconductor substrate in the source region and the drain region. Is formed.

In order to form the second hard mask pattern, a second hard mask layer is first formed to completely cover the stack gate structure of the memory cell region and to completely cover the second stacked structure of the peripheral circuit region. Thereafter, the second hard mask layer is patterned only in the peripheral circuit region so as to form the second hard mask pattern partially exposing the third conductive layer. In order to pattern the second hard mask layer, a photoresist pattern is used as an etching mask.

In the forming of the single gate structure, at the same time as the patterning of the second stacked structure, a portion of the second hard mask pattern is consumed to form the remaining portion of the second hard mask pattern on the sidewall of the stack gate structure of the memory cell region. Spacers are formed. The spacer may be formed on an upper surface of the semiconductor substrate corresponding to the drain region.

In the forming of the single gate structure in the peripheral circuit region, a first SiON film formed in the memory cell region and the peripheral circuit region may be used as an anti-reflection film. In this case, the first SiON film is formed under the first hard mask pattern.

In the forming of the stack gate structure in the memory cell region, a second SiON layer formed in the memory cell region and the peripheral circuit region may be used as an anti-reflection film. In this case, the second SiON film is formed on the first hard mask pattern.

According to the present invention, a hard mask is used as an etch mask to perform gate patterning in the peripheral circuit region as well as gate patterning in the memory cell region of the flash memory device. Patterning the gate of the peripheral circuit area using a hard mask does not affect the gate of the memory cell area at all, and there is no need to add a separate photomask compared to the conventional process. In addition, the thickness of the photoresist film can be significantly reduced as compared with the case of patterning the gate of the peripheral circuit region using the photoresist pattern. Thus, it is possible to increase the process margin in the photolithography process, to improve the profile of the gate pattern, and to improve the CD scatter.

Next, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

6 to 12 are cross-sectional views illustrating a manufacturing method of a flash memory device according to a preferred embodiment of the present invention in order of processing. In the present embodiment, a case of a Noah type flash memory device will be described as an example.

Referring to FIG. 6, a gate insulating layer 112 and a conductive first polysilicon layer 114 are formed in a memory cell region and a peripheral circuit region on a semiconductor substrate 100 in which an active region is defined by an element isolation region (not shown). Form each. In the memory cell region, the gate insulating layer 112 serves as a tunneling insulating layer.

Thereafter, an interlayer dielectric layer 116 and a conductive second polysilicon layer 118 are sequentially formed on the first polysilicon layer 114 in the memory cell region and the peripheral circuit region. The interlayer dielectric film 116 is for forming a coupling insulating film in the memory cell region, and is formed of, for example, an ONO film having a stacked structure of an oxide film, a nitride film, and an oxide film. Thereafter, the second polysilicon layer 118 and the interlayer dielectric layer 116 are removed only in the peripheral circuit region using an etching mask (not shown) covering only the memory cell region. As a result, the top surface of the first polysilicon layer 114 is exposed in the peripheral circuit region. Thereafter, the etching mask is removed to expose the top surface of the second polysilicon layer 118 in the memory cell region.

Referring to FIG. 7, the metal silicide layer 120 is formed on the memory cell region and the peripheral circuit region. The metal silicide layer 120 may be formed of, for example, a tungsten silicide (WSi _x ) layer. In this state, in the memory cell region, a laminated structure composed of the first polysilicon layer 114, the interlayer dielectric film 116, the second polysilicon layer 118, and the metal silicide layer 120 is obtained, and a peripheral circuit is obtained. In the region, a laminated structure composed of the first polysilicon layer 114 and the metal silicide layer 120 is obtained.

Thereafter, the first antireflection film 122, the first hard mask layer 124, and the second antireflection film 126 are sequentially formed on the memory cell region and the peripheral circuit region. For example, a SiON film may be formed as the first antireflection film 122, a silicon oxide film may be formed as the first hard mask layer 124, and a SiON film may be formed as the second antireflection film 126. It is not limited to this. Here, the first anti-reflection film 122 is an anti-reflection film required for gate patterning of the peripheral circuit region, and the second anti-reflection film 126 is an anti-reflection film required for gate patterning of the memory cell region.

Here, the thickness T of the first hard mask layer 124 may be formed relatively thinner than that of the prior art. This is because a hard mask is used when gate patterning the peripheral circuit region in a subsequent process. Details thereof will be described later. By making the thickness T of the first hard mask layer 124 thinner, an etching step may be reduced when gate patterning is performed in the memory cell region.

Referring to FIG. 8, a first hard mask pattern 124a to be used for gate patterning in the memory cell region is formed using the first photoresist pattern 130.

In more detail, the first photoresist pattern 130 is formed on the second anti-reflection film 126. The first photoresist pattern 130 completely covers the peripheral circuit area, and the second anti-reflection film 126 is exposed in the memory cell area so that the top surface of the second anti-reflection film 126 is exposed in the area where the conductive layer is to be removed. Partially covered.

Thereafter, the second antireflection film 126, the first hard mask layer 124, and the first antireflection film 122 are sequentially etched in the memory cell area using the first photoresist pattern 130 as an etching mask. The second antireflection film pattern 126a, the first hard mask pattern 124a, and the first antireflection film pattern 122a are formed.

Referring to FIG. 9, after the first photoresist pattern 130 is removed, gate patterning is performed in the memory cell region using the first hard mask pattern 124a as an etch mask. As a result, in the memory cell region, a floating gate composed of the first polysilicon pattern 114a, a coupling insulating layer composed of the interlayer dielectric layer pattern 116a, and the second polysilicon pattern 118a and a metal silicide pattern ( A stack gate structure in which control gates composed of 120a) are sequentially stacked is obtained. During the etching process for the gate patterning, the second anti-reflection film pattern 126a that is exposed on the upper surface of the memory cell region and the peripheral circuit region is completely removed, and the first hard mask pattern 124a is also removed from the upper surface. It is consumed by a predetermined thickness and remains in a state where the total thickness is lowered.

There are two main reasons for patterning using the first hard mask pattern 124a in a memory cell region. First, the gate structure of the memory cell region has a small pitch between the gates because the patterns are densely arranged. Therefore, there is a limit in patterning by using the photoresist pattern as an etching mask. As described above, in order to pattern the photoresist pattern as an etch mask in a memory cell region having a small gate pitch, the thickness of the photoresist pattern must be reduced. However, when the thickness of the photoresist pattern is lowered, the control may include a floating gate including the first polysilicon pattern 114a and a second polysilicon pattern 118a and a metal silicide pattern 120a in a memory cell region. There is a lack of a thickness margin of an etch mask required for dry etching a stack gate structure in which gates are stacked in sequence. Second, when the photoresist pattern is used as an etching mask, standing wave effects due to fluctuations in the thickness of the photoresist pattern, the photoresist pattern is deformed during etching, and the shape of the deformed photoresist pattern is transferred as it is, so that the underlying film is locally Due to the occurrence of a striation (striation) or the like causes a bad gate CD scattering, adversely affects the gate profile. For the above reason, a hard mask pattern is used for gate patterning in the memory cell region. During the etching of the metal silicide layer 120, the second polysilicon layer 118, and the interlayer dielectric layer 116 by using a hard mask pattern, the second anti-reflective layer pattern 126a exposed on the upper surface is completely removed. The first hard mask pattern 124a is also consumed by a predetermined thickness from an upper surface thereof. The first anti-reflection film pattern 126a remaining under the first hard mask pattern 124a is used for anti-reflection during gate patterning in the peripheral circuit region in a subsequent process.

Referring to FIG. 10, a second hard mask layer 140 is formed to pattern the peripheral circuit region. The second hard mask layer 140 may be formed of, for example, a silicon oxide layer. In this case, in order to form the second hard mask layer 140, silicon oxide is deposited on the entire surface of the resultant gate in which the memory cell region is formed. As a result, in the structure of the quinoa flash memory element as described in this embodiment, the semiconductor substrate 100 corresponding to the source region 102 of the memory cell region is adjacent to the source region 102. The space between the gates is relatively narrow so that the space between the gates is completely filled by the second hard mask layer 140. On the other hand, on the surface of the semiconductor substrate 100 corresponding to the drain region 104 of the memory cell region, the space between the two gates adjacent to the drain region 104 is relatively wide so that the space between the two gates is relatively wide. Only part of the second hard mask layer 140 is covered. However, in the present invention, such a configuration is merely an example, and is not limited thereto. That is, according to the design of the memory cell region, part of the space between both gates adjacent to the source region 102 on the surface of the semiconductor substrate 100 in the source region 102, as in the drain region 104, is also provided. Only the second hard mask layer 140 may be covered. In the peripheral circuit region, the second hard mask layer 140 is formed to have a relatively uniform thickness on the first hard mask pattern 124a.

Referring to FIG. 11, a second hard mask pattern 140a to be used for gate patterning in the peripheral circuit region is formed using the second photoresist pattern 150.

In more detail, the second photoresist pattern 150 is formed on the second hard mask layer 140. The second photoresist pattern 150 completely covers the memory cell region, and the second hard mask layer 140 is exposed in the peripheral circuit region so that the top surface of the second hard mask layer 140 is exposed in the region where the conductive layer is to be removed. ) Partially covers. Since the second photoresist pattern 150 has a thickness necessary for patterning a hard mask to be used as an etch mask in the peripheral circuit region, the thickness of the second photoresist pattern 150 is significantly higher than that of the second photoresist pattern 40 described with reference to FIG. 5. Can be lowered.

Thereafter, the second hard mask layer 140, the first hard mask pattern 124a, and the first anti-reflection film pattern 122a are sequentially formed in the peripheral circuit area using the second photoresist pattern 150 as an etching mask. Etching exposes the top surface of the metal silicide pattern 120a in the peripheral circuit region. As a result, a hard mask pattern including the first hard mask pattern 124a and the second hard mask pattern 140a is formed in the peripheral circuit region.

Referring to FIG. 12, after removing the second photoresist pattern 150, a peripheral circuit using the hard mask pattern including the first hard mask pattern 124a and the second hard mask pattern 140a as an etch mask. Gate patterning is performed in the region. As a result, a single gate structure having a laminated structure of the first polysilicon pattern 114a and the metal silicide pattern 120a in the peripheral circuit region is obtained.

During the etching process using the hard mask pattern including the first hard mask pattern 124a and the second hard mask pattern 140a as an etching mask, the second hard mask pattern (in the peripheral circuit region and the memory cell region, respectively) A portion of the 140a is consumed, and on the upper surface of the semiconductor substrate 100 corresponding to the drain region 104 in the memory cell region, a spacer 140b formed of the remaining portion of the second hard mask pattern 140a on the sidewall of the gate. ) Is formed.

In the method of manufacturing a flash memory device according to the present invention, a hard mask is used as an etch mask to perform gate patterning in a peripheral circuit region as well as gate patterning in a memory cell region on a semiconductor substrate. As described above, in the patterning of the gate of the peripheral circuit region by using the hard mask, the gate of the memory cell region is not affected at all, and there is no need to add a separate photomask as compared to the conventional process. By patterning the gate of the peripheral circuit area using a hard mask, the thickness of the photoresist film can be significantly lowered compared to the case of patterning using a photoresist pattern. Thus, it is possible to increase the process margin in the photolithography process, to improve the profile of the gate pattern, and to improve the CD scatter.

In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and changes by those skilled in the art within the scope of the technical idea of the present invention. This is possible.

1 to 5 are cross-sectional views illustrating a manufacturing method of a flash memory device according to the prior art, according to a process sequence.

6 to 12 are cross-sectional views illustrating a manufacturing method of a flash memory device according to a preferred embodiment of the present invention in order of processing.

<Explanation of symbols for the main parts of the drawings>

Reference Signs List 100: semiconductor substrate, 102: source region, 104: drain region, 112: gate insulating film, 114: first polysilicon layer, 114a: first polysilicon pattern, 116: interlayer dielectric film, 116a: interlayer dielectric film pattern, 118: first 2 polysilicon layer, 118a: second polysilicon pattern, 120: metal silicide layer, 120a: metal silicide pattern, 122: first antireflection film, 122a: first antireflection film pattern, 124: first hard mask layer, 124a: First hard mask pattern, 126: second antireflection film, 126a: second antireflection film pattern, 130: first photoresist pattern, 140: second hard mask layer, 140a: second hard mask pattern, 140b: spacer, 150 : Second photoresist pattern,

Claims (19)

A first stacked structure in which the first conductive layer, the interlayer dielectric film, and the second conductive layer are sequentially stacked on the semiconductor cell having a memory cell region and a peripheral circuit region, and sequentially stacked; Forming a second stacked structure comprising a layer on the semiconductor substrate; Patterning the first stacked structure in the memory cell region using a first hard mask pattern as an etch mask to form a stacked gate structure including a floating gate, a coupling insulating layer, and a control gate; Forming a second hard mask pattern covering the stack gate structure of the memory cell region and the second stacked structure of the peripheral circuit region; And patterning the second stacked structure in the peripheral circuit region using the second hard mask pattern as an etch mask to form a single gate structure. The method of claim 1, The first conductive layer of the first laminated structure is composed of a conductive first polysilicon layer, And the second conductive layer of the first stacked structure is formed of a stacked structure of a conductive second polysilicon layer and a first metal silicide layer. The method of claim 1, And the interlayer dielectric film of the first stacked structure is formed of a stacked structure of an oxide film, a nitride film, and an oxide film. The method of claim 2, And the third conductive layer of the second laminated structure is formed of a laminated structure of the conductive third polysilicon layer and the second metal silicide layer. The method of claim 4, wherein And the first polysilicon layer and the third polysilicon layer are formed at the same time. The method of claim 4, wherein And the first metal silicide layer and the second metal silicide layer are formed at the same time. The method of claim 1, And the first hard mask pattern is formed of a silicon oxide film. The method of claim 1, And said second hard mask pattern is formed of a silicon oxide film. The method of claim 1, After the stack gate structure is formed, the first hard mask pattern remains on the stack gate structure and on the second stacked structure at a lower thickness. And the second hard mask pattern is formed on the remaining first hard mask pattern. The method of claim 1, The semiconductor substrate includes a source region and a drain region respectively formed between the stack gate structures in the memory cell region, And the second hard mask pattern is formed to cover the top surface of the semiconductor substrate in the source region and the drain region. The method of claim 1, Forming the second hard mask pattern is Forming a second hard mask layer that completely covers the stack gate structure of the memory cell region and completely covers the second stacked structure of the peripheral circuit region; And patterning the second hard mask layer only in the peripheral circuit region so that the second hard mask pattern partially exposing the third conductive layer is formed. The method of claim 11, The patterning of the second hard mask layer may include using a photoresist pattern as an etch mask. The method of claim 1, In the forming of the single gate structure, at the same time as the patterning of the second stacked structure, a portion of the second hard mask pattern is consumed to form the remaining portion of the second hard mask pattern on the sidewall of the stack gate structure of the memory cell region. Method for manufacturing a flash memory device, characterized in that the spacer is formed. The method of claim 13, The semiconductor substrate includes a source region and a drain region respectively formed between the stack gate structures in the memory cell region, And the spacer is formed on an upper surface of the semiconductor substrate corresponding to the drain region. The method of claim 1, And forming the single gate structure in the peripheral circuit region, using the first SiON film formed in the memory cell region and the peripheral circuit region as an anti-reflection film. The method of claim 15, And the first SiON film is formed under the first hard mask pattern. The method of claim 1, And forming the stack gate structure in the memory cell region using a second SiON film formed in the memory cell region and a peripheral circuit region as an anti-reflection film. The method of claim 17, And the second SiON film is formed on the first hard mask pattern. The method of claim 6, And the first metal silicide layer and the second metal silicide layer are each composed of a tungsten silicide layer.