KR20050022086A - Method for fabricating polysilicon thin film transistor - Google Patents
Method for fabricating polysilicon thin film transistor Download PDFInfo
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- KR20050022086A KR20050022086A KR1020030058731A KR20030058731A KR20050022086A KR 20050022086 A KR20050022086 A KR 20050022086A KR 1020030058731 A KR1020030058731 A KR 1020030058731A KR 20030058731 A KR20030058731 A KR 20030058731A KR 20050022086 A KR20050022086 A KR 20050022086A
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- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000010409 thin film Substances 0.000 title claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 title claims description 15
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000006356 dehydrogenation reaction Methods 0.000 claims abstract description 10
- 239000011521 glass Substances 0.000 claims abstract description 10
- 238000000059 patterning Methods 0.000 claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 2
- 238000002425 crystallisation Methods 0.000 abstract description 15
- 230000008025 crystallization Effects 0.000 abstract description 14
- 230000015572 biosynthetic process Effects 0.000 description 9
- 238000002844 melting Methods 0.000 description 7
- 230000008018 melting Effects 0.000 description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 230000002457 bidirectional effect Effects 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000004941 influx Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
- H01L21/02686—Pulsed laser beam
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
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- General Physics & Mathematics (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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- Optics & Photonics (AREA)
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- Thin Film Transistor (AREA)
Abstract
Description
본 발명은 박막트랜지스터 제조방법에 관한 것으로서, 보다 상세하게는 유리기판위에 증착된 비정질실리콘층으로부터 유리기판의 변형이 일어나지 않는 비교적 저온의 공정을 통하여 다결정실리콘으로 결정화시킬 수 있는 다결정실리콘 박막 트랜지스터 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a thin film transistor, and more particularly, a method for manufacturing a polysilicon thin film transistor which can be crystallized to polycrystalline silicon through a relatively low temperature process in which a glass substrate is not deformed from an amorphous silicon layer deposited on a glass substrate. It is about.
박막트랜지스터 액정 디스플레이가 고밀도, 대면적화되고 디스플레이부분과 구동회로 부분을 동일한 기판위에 제작하기 위하여 박막 트랜지스터의 이동도 증가가 절실시 요구되고 있지만, 비정질 실리콘 박막 트랜지스터로는 잇점을 만족하기가 어렵다.Although thin film transistor liquid crystal displays have high density, large area, and increase in mobility of thin film transistors in order to fabricate display parts and driving circuit parts on the same substrate, it is difficult to satisfy the advantages of amorphous silicon thin film transistors.
이러한 문제점을 효과적으로 해결할 수 있는 방법으로 저온 다결정실리콘 박막 트랜지스터가 많은 주목을 받고 있다.Low temperature polysilicon thin film transistors have attracted much attention as a way to effectively solve this problem.
저온 다결정실리콘 박막 트랜지스터의 제조방법중 현재 가장 널리 사용되고 있는 것은 엑시머 레이저(eximer laser)를 이용한 결정화방법이다. The most widely used low temperature polysilicon thin film transistor manufacturing method is a crystallization method using an excimer laser.
이 방법은 또한 크게 입사빔이 조사되기전 마스크를 통과하여 조사되는 영역을 제어하는 SLS(sequential laterial solidification) 법과, 마스크를 사용하지 않은 기존의 ELA(eximer laser annealing)법으로 분류할 수 있다.This method can also be classified into a sequential laterial solidification (SLS) method that controls the area irradiated through the mask before the incident beam is largely irradiated, and the conventional excimer laser annealing (ELA) method without using the mask.
두가지 방법은 모두 유리기판에 유리기판으로부터 실리콘층으로의 불순물 오염을 방지하기 위한 버퍼층(buffer layer)과 비정질실리콘을 증착한후 비정질 실리콘내의 수소를 제거하기 위한 탈수소 열처리과정후 매우 짧은 시간동안 비정질실리콘 박막이 엑시머 레이저에 노출되므로써 유리기판의 변형을 유발하지 않으면서 비정질실리콘이 액상을 거쳐 결정질 실리콘으로 변태되는 과정으로 이루어져 있다.Both methods deposit a buffer layer and amorphous silicon to prevent impurity contamination from the glass substrate to the silicon layer on the glass substrate, and then, for a very short time after the dehydrogenation heat treatment to remove hydrogen in the amorphous silicon, As the thin film is exposed to the excimer laser, the amorphous silicon is transformed into crystalline silicon through the liquid phase without causing deformation of the glass substrate.
비정질실리콘에 엑시머 레이저를 조사할 경우, 액시머 에너지의 크기에 따라 크게 부분용융영역(partial melting region), 인접 완전 용융영역(near-complete melting region) 및 완전용융영역(complete melting region)의 세부분으로 나뉘어진다.When the excimer laser is irradiated to the amorphous silicon, the details of the partial melting region, the near-complete melting region and the complete melting region largely depend on the amount of the excimer energy. Divided into.
여기서, 그레인의 크기는 인접 완전 용융영역에서 수 μm 정도로 가장 크지만, 약간의 변화에도 그레인 크기가 크게 변화하여 공정마진이 작으므로 ELA법에서는 균일한 그레인을 얻기 위하여 부분 용융영역을 사용하고 있다.Here, the grain size is the largest in the adjacent complete melting region (a few μm), but the grain size is largely changed even with slight changes, so the process margin is small. In the ELA method, the partial melting region is used to obtain uniform grain.
그러나, 이럴 경우 그레인 크기는 최대 수천Å 수준에 불과하므로, 구동회로를 동작시키기에 충분한 이동도를 얻을 수 없다는 단점이 있다.However, in this case, since the grain size is only a few thousand Å at maximum, there is a disadvantage in that sufficient mobility cannot be obtained to operate the driving circuit.
SLS법은 마스크를 사용하여 레이저가 조사되는 영역과 그렇지 않은 영역의 경계를 구분하여 조사되지 않는 비정질 실리콘에서부터 결정화가 시작되어 영역내부로 진행된다.In the SLS method, crystallization starts from amorphous silicon that is not irradiated by using a mask to distinguish the boundary between an area irradiated with a laser and an area that is not.
에너지영역이 완전용융영역이므로 충분한 마진을 갖고 있으나, 도 1에서와 같이, 레이저가 조사되지 않는 영역(A)이 레이저조사영역(B)의 양쪽에 존재하기 때문에 양쪽에서 결정화가 동시에 진행되어 레이저조사영역의 중앙에서 입계가 서로 충돌하게 된다. 이때, 이렇게 입계가 충돌하여 발생하는 돌출부(protrusion)(15)는 트랜지스터 설계시 단일 TFT내에 1개 이상 포함될 수 밖에 없다.Since the energy region is a complete melting region, it has a sufficient margin. However, as shown in FIG. 1, since the region A, which is not irradiated with laser, exists on both sides of the laser irradiation region B, crystallization proceeds simultaneously on both sides, thereby irradiating the laser. At the center of the region, the grain boundaries collide with each other. At this time, one or more protrusions 15 generated by collision of grain boundaries may be included in a single TFT when designing a transistor.
이렇게 TFT내에 돌출부가 존재할 경우, TFT 특성의 저하를 가져 오며 또한 TFT내에 포함되는 돌출부(15)의 개수에 따른 TFT 특성이 불균일하게 되는 문제점이 있다. If the protrusions exist in the TFT as described above, there is a problem in that the TFT characteristics are deteriorated and the TFT characteristics become uneven according to the number of the protrusions 15 included in the TFT.
이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 입계충돌에 의한 돌출부의 발생을 방지하고 진행방향에 네크(neck)를 형성하여 소수의 결정립만이 살아 남아 결정화되도록 하므로써 그레인 크기를 크게 할 수 있는 다결정실리콘 박막트랜지스터 제조방법을 제공함에 그 목적이 있다.Therefore, the present invention has been made to solve the above problems of the prior art, by preventing the generation of protrusions due to intergranular collision and by forming a neck (neck) in the advancing direction so that only a small number of grains survive to crystallize grain size The purpose of the present invention is to provide a polysilicon thin film transistor manufacturing method which can increase the size.
상기 목적을 달성하기 위한 본 발명에 따른 다결정실리콘 박막트랜지스터 제조방법은, 절연성 유리기판상에 버퍼층과 비정질실리콘층을 연속적으로 형성하는 단계;According to an aspect of the present invention, there is provided a method of manufacturing a polysilicon thin film transistor, the method comprising: continuously forming a buffer layer and an amorphous silicon layer on an insulating glass substrate;
상기 비정질실리콘층내의 수소를 제거하는 탈수소 공정을 진행하는 단계;Proceeding with a dehydrogenation process to remove hydrogen in the amorphous silicon layer;
탈수소공정을 진행한후 비정질실리콘층을 선택적으로 패터닝하는 단계; 및Selectively patterning the amorphous silicon layer after the dehydrogenation process; And
패터닝된 비정질실리콘층내에 엑시머 레이저를 조사하여 결정화시키는 단계를 포함하여 구성되는 것을 특징으로한다.Irradiating and crystallizing the excimer laser in the patterned amorphous silicon layer.
(실시예)(Example)
이하, 본 발명에 따른 다결정실리콘 박막트랜지스터 제조방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a polysilicon thin film transistor according to the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명에 따른 다결정실리콘 박막트랜지스터 제조방법에 있어서, 다결정실리콘을 패터닝한 후의 평면도이다.2 is a plan view after patterning the polysilicon in the polysilicon thin film transistor manufacturing method according to the present invention.
도 3은 본 발명에 따른 다결정실리콘 박막트랜지스터 제조방법에 있어서, 엑시머 레이저 조사후의 결정화양상을 나타낸 도면이다.3 is a view showing a crystallization pattern after excimer laser irradiation in the polysilicon thin film transistor manufacturing method according to the present invention.
본 발명에 따른 다결정실리콘 박막트랜지스터 제조방법은, 도 2에 도시된 바와같이, 절연성 유리기판(미도시)상에 버퍼층(미도시)과 비정질실리콘층(33)을 연속적으로 증착한다. 이때, 상기 버퍼층은 고온공정 진행시 유리기판으로부터 비정질실리콘층으로 불순물의 유입을 방지하기 위한 것으로, 그 재질로는 SiO2, SiNx, SiON 등을 사용한다. 또한, 상기 비정질실리콘층(33)은 일반적으로 수백 Å에서 수천 Å의 두께로 증착한다.In the method of manufacturing a polysilicon thin film transistor according to the present invention, as shown in FIG. 2, a buffer layer (not shown) and an amorphous silicon layer 33 are continuously deposited on an insulating glass substrate (not shown). In this case, the buffer layer is to prevent the influx of impurities from the glass substrate to the amorphous silicon layer during the high temperature process, the material is used SiO 2 , SiN x , SiON and the like. In addition, the amorphous silicon layer 33 is generally deposited at a thickness of several hundreds of micrometers to several thousand micrometers.
그다음, 연속해서 증착된 비정질실리콘층(33)내의 수소를 제거하기 위하여 탈수소공정을 진행한다. 이때, 상기 탈수소공정은 N2분위기에서 400∼650℃의 온도범위에서 진행한다.Then, a dehydrogenation process is performed to remove hydrogen in the continuously deposited amorphous silicon layer 33. At this time, the dehydrogenation process is carried out in a temperature range of 400 ~ 650 ℃ in N 2 atmosphere.
이어서, 탈수소 공정후 마스크를 이용하여 비정질 실리콘층(33)을 도 2와 같은 형태로 패터닝한다. 이때, 상기 비정질실리콘층의 패터닝시에 비정질실리콘아일랜드(35)를 형성하고, 아일랜드내부에 비정질실리콘 네크(neck)를 형성한다. 이때, 상기 비정질실리콘 네크의 폭과 길이는 각각 5000Å와 10μm 정도이다. 또한, 상기 비정질실리콘 아일랜드간 간격은 1∼100 μm이다.Subsequently, after the dehydrogenation process, the amorphous silicon layer 33 is patterned in the form as shown in FIG. 2 using a mask. At this time, an amorphous silicon island 35 is formed at the time of patterning the amorphous silicon layer, and an amorphous silicon neck is formed in the island. At this time, the width and length of the amorphous silicon neck is about 5000Å and 10μm respectively. In addition, the interval between the amorphous silicon islands is 1 to 100 μm.
그다음, 상기 비정질 실리콘층(33)을 패터닝한후 엑시머레이저를 조사한다. 이때, 레이저 조사영역(B)의 범위는 도 2에 도시된 바와같이 각각의 실리콘 아일랜드(35)의 한쪽은 비정질실리콘영역내부에, 그리고 반대쪽은 비정질실리콘영역외부에 걸쳐 있으며, 이웃하는 아일랜드와는 겹치지 않는 범위에서 엑시머 레이저를 조사한다. Next, after patterning the amorphous silicon layer 33, the excimer laser is irradiated. At this time, the range of the laser irradiation area B is as shown in Fig. 2, one side of each silicon island 35 is in the inside of the amorphous silicon region, and the other side is outside the amorphous silicon region, and the neighboring islands Irradiate the excimer laser in the non-overlapping range.
이렇게 엑시머 레이저 조사후 결정화(37) 양상을 도 3에 나타내었다. 도 3에서 볼 수 있는 바와같이, 각각의 비정질실리콘 아일랜드(35)에서 비정질실리콘영역외부까지 조사가 끝나면, 비정질실리콘이 전부 용융상태(full-melting)가 되기 때문에, 결정화에 시드(seed)로 작용할 비정질실리콘이 존재하지 않으므로 결정화가 진행되지 않는다.Thus, the crystallization (37) aspect after the excimer laser irradiation is shown in FIG. As can be seen in FIG. 3, after irradiation from each amorphous silicon island 35 to the outside of the amorphous silicon region, the amorphous silicon becomes full-melting, so that it may act as a seed for crystallization. There is no amorphous silicon, so crystallization does not proceed.
따라서, 결정화의 진행방향은 좌에서 우로 한 방향이 되고, 이로 인하여 종래기술에서 문제되었던 양방향 결정화에 의한 돌출부(protrusion)는 발생하지 않는다.Therefore, the advancing direction of the crystallization is from left to right, whereby no protrusion due to bidirectional crystallization, which has been a problem in the prior art, does not occur.
또한, 결정진행방향(C)에 비정질실리콘이 사라져 네크(neck)를 형성한 부분에서 성장하던 입계중 일부만이 네크를 통과하여 성장하므로써 종래기술에서 보다 더 큰 결정립 크기를 얻을 수 있다.In addition, since only a part of the grain boundaries that were grown at the portion where the amorphous silicon disappeared in the crystal progress direction C and formed the neck may grow through the neck, a larger grain size than in the prior art may be obtained.
이렇게 결정화(37)가 완료되면, 이후의 다결정실리콘 박막트랜지스터 제조공정은 상용화된 제조공정과 동일한다. 즉, 활성영역 형성, 게이트절연막 증착, 게이트전극 형성, 오프셋 형성 및 LDD 공정진행, 활성화, 패시베이션 형성, 콘택홀 형성, 소오스/드레인 전극 형성, 보호막 형성, 비아홀 형성, 화소전극 형성의 순으로 진행한다.When the crystallization 37 is completed in this way, the subsequent polysilicon thin film transistor manufacturing process is the same as the commercialized manufacturing process. That is, the active region formation, the gate insulation film deposition, the gate electrode formation, the offset formation and the LDD process, the activation, the passivation formation, the contact hole formation, the source / drain electrode formation, the protective film formation, the via hole formation, and the pixel electrode formation are performed in this order. .
상기에서 설명한 바와같이, 본 발명에 따른 다결정실리콘 박막트랜지스터 제조방법에 의하면, 종래기술과는 달리 액시머 레이저를 이용한 조사전에 비정질실리콘층을 특정형상으로 패터닝하므로써 결정진행 방향을 한 방향으로 진행시켜 종래기술에서 문제시되었던 양방향 결정화에 의한 돌출부의 발생을 제거할 수 있다.As described above, according to the method of manufacturing a polysilicon thin film transistor according to the present invention, unlike the prior art, by advancing the crystal progress direction in one direction by patterning the amorphous silicon layer in a specific shape before irradiation with an aximmer laser, It is possible to eliminate the occurrence of protrusions due to bidirectional crystallization which has been a problem in the technology.
따라서, 박막 트랜지스터의 특성을 향상시킬 수 있으며, TFT내에 돌출부의 함유 개수에 따라 불균일한 특성을 보이던 종래기술과는 달리 균일한 TFT특성을 얻을 수 있다.Therefore, the characteristics of the thin film transistor can be improved, and uniform TFT characteristics can be obtained, unlike the prior art, which exhibited non-uniform characteristics depending on the number of protrusions contained in the TFTs.
또한, 진행방향으로 비정질 실리콘의 네크(neck)를 형성하므로써 계속 성장을 진행할 수 있는 결정립 수를 줄여 종래기술에서 보다 큰 결정립 사이즈를 얻을 수 있을 뿐만 아니라 엑시머 레이저의 조사영역 마진을 넓힘으로써 공정의 안정화를 기대할 수 있다.In addition, by forming a neck of amorphous silicon in the advancing direction, it is possible to reduce the number of grains that can continue to grow, thereby obtaining a larger grain size than in the prior art, and stabilizing the process by expanding the irradiation area margin of the excimer laser. You can expect.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
도 1은 종래기술에 따른 양방향 결정화 진행에 의한 입계충돌 돌출현상을 나타낸 단면사진,1 is a cross-sectional photograph showing a boundary collision protrusion phenomenon by bidirectional crystallization proceeding according to the prior art,
도 2는 본 발명에 따른 다결정실리콘을 패터닝한 후의 평면도,2 is a plan view after patterning the polysilicon according to the present invention,
도 3은 본 발명에 따른 엑시머 레이저 조사후의 결정화양상을 나타낸 도면.3 is a view showing the crystallization pattern after excimer laser irradiation according to the present invention.
[도면부호의설명][Description of Drawing Reference]
33 : 비정질실리콘층 35 : 비정질실리콘 아일랜드33: amorphous silicon layer 35: amorphous silicon island
37 : 결정화 A : 레이저가 조사되지 않은 영역 37: crystallization A: the area not irradiated with laser
B : 레이저조사영역 C : 성장방향B: laser irradiation area C: growth direction
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