KR20050019159A - Method of manufacturing a capacitor having high perceptivity, and the capacitor thereof - Google Patents
Method of manufacturing a capacitor having high perceptivity, and the capacitor thereof Download PDFInfo
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Abstract
Description
본 발명은 반도체 메모리소자에 관한 것으로서, 더욱 상세하게는 반도체소자용 커패시터 유전막의 형성방법 및 그에 의해 형성되는 유전막에 관한 것이다. The present invention relates to a semiconductor memory device, and more particularly, to a method of forming a capacitor dielectric film for a semiconductor device and a dielectric film formed thereby.
DRAM(dynamic random access memory) 반도체 소자가 고집적화 됨에 따라 보다 작은 면적에서 충분한 정전용량을 가지는 커패시터(capacitor)의 개발이 필요하게 되었는데, 지금까지는 산화실리콘(SiO2) 박막화 하거나 또는 커패시터를 스택(stack)하는 등의 3차원구조로 만드는 방법으로 정전용량을 확보하여 왔다. As dynamic random access memory (DRAM) semiconductor devices are highly integrated, it is necessary to develop a capacitor having sufficient capacitance in a smaller area. Until now, a silicon oxide (SiO 2) thin film or a stack of capacitors has been required. The capacitance has been secured by making a three-dimensional structure of the back.
그러나 SiO2의 박막화에는 파괴전압(breakdown voltage)의 저하와 누설전류(leakage current)의 증가를 유발하므로 한계가 있었으며, 커패시터 구조의 입체화는 그 공정의 곤란함으로 인하여 많은 제약을 받아왔다. However, the thinning of SiO 2 has a limitation because it causes a decrease in breakdown voltage and an increase in leakage current, and the three-dimensional structure of the capacitor has been limited by the difficulty of the process.
특히 256Mbit급 이상의 메모리 반도체소자에서는 기존의 ONO(oxide/nitride/oxide)를 대체할 커패시터용 절연막의 개발이 필수적인데 최근 들어 커패시터용 고유전막으로서 산화실리콘에 비해 유전율이 3-6배정도 높은 산화탄탈륨(Ta2O5)이 주목 받고있다. In particular, the development of a capacitor insulating film to replace the existing ONO (oxide / nitride / oxide) is essential in memory semiconductor devices of 256 Mbit or more. Recently, tantalum oxide having a dielectric constant of 3-6 times higher than that of silicon oxide is used as a high dielectric film for capacitors. Ta2O5) is attracting attention.
도 1은 이러한 산화탄탈륨을 절연막으로 하는 종래 커패시터의 단면구성도로서, 커패시터는 기판(10) 상의 하부전극(20)과, 상기 하부전극(20)에 증착되는 산화탄탈륨(40)과, 증착된 상기 산화탄탈륨(40)의 상부전극(50)으로 이루어진다. 1 is a cross-sectional view of a conventional capacitor using such a tantalum oxide as an insulating film. The capacitor includes a lower electrode 20 on a substrate 10, a tantalum oxide 40 deposited on the lower electrode 20, and a deposited capacitor. The upper electrode 50 of the tantalum oxide 40 is formed.
그러나 산화탄탈륨을 절연막으로 하는 경우 산화탄탈륨을 결정화시키게 되는데, 결정화를 위해 어닐링(annealing) 처리를 하면 산화탄탈륨의 유전율은 증가하지만 산화탄탈륨 박막 내의 일부 산소가 방출된다. However, when tantalum oxide is used as an insulating film, tantalum oxide is crystallized. When annealing is performed for crystallization, the dielectric constant of tantalum oxide is increased, but some oxygen in the tantalum oxide thin film is released.
결과적으로 산화탄탈륨은 산소가 결핍되며, 절연효과를 감소시킴과 동시에 하부전극은 산화탄탈륨으로부터 방출되는 산소에 의해 산화되는 단점이 있다. As a result, tantalum oxide is deficient in oxygen, and at the same time, the bottom electrode is oxidized by oxygen released from tantalum oxide while reducing the insulation effect.
그리고 하부전극을 폴리실리콘으로 형성되는 경우 산화실리콘이 산화에 의해 생성되어 산화탄탈륨의 결정부족을 어느 정도 보충하고 절연효과의 감소를 억제하지만 커패시터의 용량은 필연적으로 감소되며, 반면에 하부전극이 금속성 재료로 형성되는 경우 고품질의 금속산화물이 하부전극용으로 폴리실리콘을 사용하는 경우와는 달리 균일하게 생성되지 않기 때문에 전기누출이 쉽게 일어날 수 있는 문제점을 각각 안고 있다. When the lower electrode is made of polysilicon, silicon oxide is produced by oxidation to compensate for the lack of crystals of tantalum oxide and suppresses the reduction of the insulating effect, but the capacitance of the capacitor is inevitably reduced, whereas the lower electrode is metallic When the material is formed of a high-quality metal oxide, unlike the case of using polysilicon for the lower electrode, since it is not produced uniformly, each has a problem that can easily occur electrical leakage.
이에 산화탄탈륨과 같이 유전율이 높은 산화알루미늄(Al2O3)을 함께 사용하여 산화탄탈륨에 의한 단일막의 단점을 개선시키고자 하는 방법이 제안되었다. Therefore, a method of improving the shortcomings of a single layer caused by tantalum oxide by using aluminum oxide (Al 2 O 3) having a high dielectric constant such as tantalum oxide has been proposed.
도 2는 이러한 기술에 의해 증착된 절연막으로서 산화알루미늄(30)과 산화탄탈륨(40)이 적층구조를 이루고 있는 커패시터의 단면구성을, 그리고 도 3은 산화탄탈륨(40)에 대하여 산화알루미늄(30)이 이중으로 적층구조를 이루고 있는 커패시터의 단면구성을 각각 보여준다. FIG. 2 shows a cross-sectional structure of a capacitor in which aluminum oxide 30 and tantalum oxide 40 are laminated as an insulating film deposited by this technique, and FIG. 3 shows aluminum oxide 30 with respect to tantalum oxide 40. The cross-sectional structure of the capacitor forming this double layer structure is shown.
도 4는 이러한 적층구조를 가지는 절연막을 형성시키는 기본 공정도로서, 그 기본 공정은 기판으로서 웨이퍼(W)를 공정챔버부(process chamber, 또는 PC)로 이송시켜 진공상태에서 상기 기판 상에 상, 하부전극 및 절연막으로서 금속 산화막을 증착시키는 공정(S10)을 포함하여 이루어진다. FIG. 4 is a basic process chart for forming an insulating film having such a laminated structure, and the basic process is to transfer the wafer W as a substrate to a process chamber (PC) so that the upper and lower portions of the insulating film are formed on the substrate in a vacuum state. And depositing a metal oxide film as an electrode and an insulating film (S10).
한편, 상기 공정챔버부(PC)는 각기 다른 증착공정을 수행하는 복수 개의 공정챔버를 포함하는 그 예가 도 5 및 도 6에 각각 도시되어 있다. Meanwhile, examples of the process chamber PC including a plurality of process chambers for performing different deposition processes are shown in FIGS. 5 and 6, respectively.
도 5는 절연막이 산화알루미늄과 산화탄탈륨의 적층구조로 이루어지는 경우 공정챔버부 내부의 각 공정챔버에서 이루어지는 증착공정도로서, 웨이퍼를 제1공정챔버로 이송, 안치시키고 상기 제1공정챔버를 밀폐시킨 다음 내부의 압력을 낮추어서(통상 진공상태) 화학기상증착(chemical vapor deposition 또는 CVD)방식에 의해 산화알루미늄을 증착한다(S22). FIG. 5 is a deposition process diagram formed in each process chamber inside the process chamber when the insulating film is formed of a laminated structure of aluminum oxide and tantalum oxide. The wafer is transferred to and placed in the first process chamber, and the first process chamber is sealed. The internal pressure is reduced (usually in a vacuum state) to deposit aluminum oxide by chemical vapor deposition (chemical vapor deposition or CVD) (S22).
제1공정챔버에서 산화알루미늄의 증착이 완료되면 상기 제1공정챔버 내부의 압력을 초기값(통상적으로 대기압력)으로 복원시킨 다음 상기 공정과 유사하게 웨이퍼를 제2공정챔버 내부로 이송, 안치 및 밀폐, 진공과정을 거친 후 원자층증착(atomic layer deposition 또는 ALD)방식에 의해 산화탄탈륨을 증착하게 되는 것이다(S24). When deposition of the aluminum oxide is completed in the first process chamber, the pressure inside the first process chamber is restored to an initial value (usually atmospheric pressure), and then the wafer is transferred into the second process chamber, settled and After sealing and vacuuming, tantalum oxide is deposited by atomic layer deposition (ALD) (S24).
한편, 도 6은 산화탄탈륨에 대하여 산화알루미늄을 이중으로 적층시키는 경우 공정챔버부 내부의 각 공정챔버에서 이루어지는 증착공정도로서, 도5와 달리 제2공정챔버에서 산화탄탈륨이 증착되고 나면 웨이퍼를 다시 제1공정챔버내부로 이송하여 동일한 방법으로 산화알루미늄을 재 증착하는 단계(S22)를 더욱 포함함을 알 수 있다. On the other hand, Figure 6 is a deposition process chart formed in each process chamber inside the process chamber portion when the aluminum oxide is double stacked on tantalum oxide, unlike in Figure 5, once the tantalum oxide is deposited in the second process chamber again It can be seen that the method further includes the step (S22) of transferring the inside of the chamber to re-deposit aluminum oxide in the same manner.
그러나 종래 웨이퍼 상에 산화알루미늄과 산화탄탈륨 또는 산화탄탈륨에 대하여 산화알루미늄을 이중으로 적층시켜 절연막을 형성시키는 상기와 같은 공정에서는 공정챔버 내부에 존재하는 제1공정챔버에서 화학기상증착방식에 의한 공정이 완료되면 제1공정챔버 내부의 진공상태를 해제하고 초기 압력으로 복원한 다음 웨이퍼를 제2공정챔버 내부로 이송시키고 제2공정챔버 내부를 진공상태로 만든 다음 원자층증착방식에 의한 공정과정을 거치게 되는 분리된 증착시스템으로 이루어져 있었다. However, in the above-described process of forming an insulating film by stacking aluminum oxide and tantalum oxide or tantalum oxide on a wafer in a double layer, a process using a chemical vapor deposition method is performed in a first process chamber existing inside a process chamber. When complete, release the vacuum inside the first process chamber, restore the initial pressure, transfer the wafer into the second process chamber, vacuum the inside of the second process chamber, and then go through the atomic layer deposition process. Consisting of a separate deposition system.
결과적으로 이렇게 분리된 시스템을 이용하여 증착공정을 수행하는 종래 기술에서는 제1시스템에서 제2시스템으로 웨이퍼를 이동시 진공상태를 해제하고 복원하는 과정이 필연적으로 수반될 수밖에 없었는데, 이러한 진공상태의 잦은 해제 및 복원은 절연막 표면이 심각하게 오염되는 문제를 발생시켰으며, 이에 부가하여 제2시스템에서 제1시스템으로 이동이 필요한 도 6의 경우는 더욱 그러하였다. As a result, in the prior art of performing the deposition process using this separated system, the process of releasing and restoring the vacuum state is inevitably involved in moving the wafer from the first system to the second system. And restoring caused a serious contamination of the insulating film surface, in addition to the case of FIG. 6 in which the movement from the second system to the first system is required.
더욱이 이러한 진공상태의 잦은 해제 및 복원과정 수행은 전체 공정을 장기화시켜 커패시터의 생산성을 떨어뜨리는 주요한 요인으로 작용하였다. In addition, the frequent release and restoration of vacuums has been a major factor in reducing the productivity of capacitors by prolonging the entire process.
본 발명은 상기와 같은 문제점을 극복하기 위해 고안된 것으로서, 고유전율을 가지는 금속산화막을 진공상태의 해제 없이 하나의 증착시스템에 의해 적층구조로 형성시킬 수 있는 방법 및 그에 의한 커패시터를 제공함에 그 목적이 있다. The present invention was devised to overcome the above problems, and an object thereof is to provide a method and a capacitor by which a metal oxide film having a high dielectric constant can be formed in a stacked structure by one deposition system without releasing a vacuum state. have.
본 발명은 상기와 같은 목적을 달성하기 위해서, 복수 개의 공정챔버를 포함하며 일정 압력이 유지되는 공정챔버부에서 반도체소자용 커패시터의 하부전극과 상부전극 사이에 유전막을 형성시키는 방법에 관한 것으로서, 제1공정챔버 내부에서 상기 하부전극 상에 제1금속 산화막을 증착하는 단계와, 상기 제1공정챔버 내부와 동일한 압력하에서 상기 제1금속 산화막이 증착된 커패시터를 제2공정챔버 내부로 이송하는 단계와, 상기 제2공정챔버 내부에서 상기 제1금속 산화막 상에 제2금속 산화막을 증착하는 단계를 포함하는 반도체소자용 커패시터의 유전막 형성방법을 제공한다. The present invention relates to a method of forming a dielectric film between a lower electrode and an upper electrode of a capacitor for a semiconductor device in a process chamber portion including a plurality of process chambers and maintaining a constant pressure in order to achieve the above object, Depositing a first metal oxide film on the lower electrode in the first process chamber, and transferring the capacitor on which the first metal oxide film is deposited into the second process chamber under the same pressure as the inside of the first process chamber; And depositing a second metal oxide film on the first metal oxide film in the second process chamber.
상기 제2공정챔버에서 제2금속 산화막을 증착시킨 다음에 상기 제2공정챔버 내부와 동일한 압력하에서 상기 제2금속 산화막이 증착된 웨이퍼를 상기 제1공정챔버로 이송시키고 상기 제2금속 산화막 상에 제1금속 산화막을 재 증착하는 단계를 더욱 포함하는 것을 특징으로 한다. After depositing the second metal oxide film in the second process chamber, the wafer on which the second metal oxide film is deposited is transferred to the first process chamber under the same pressure as the inside of the second process chamber, and is deposited on the second metal oxide film. Re-depositing the first metal oxide film is characterized in that it further comprises.
상기 제1금속 산화막은 산화알루미늄으로 이루어지는 것을 특징으로 한다. The first metal oxide film is made of aluminum oxide.
상기 제2금속 산화막은 산화탄탈륨, 산화하프늄 중의 어느 하나로 이루어지는 것을 특징으로 한다. The second metal oxide film is formed of any one of tantalum oxide and hafnium oxide.
상기 제1공정챔버에서의 증착은 화학기상증착방식에 의하는 것을 특징으로 한다. Deposition in the first process chamber is characterized by the chemical vapor deposition method.
상기 제2공정챔버에서의 증착은 원자층증착방식에 의하는 것을 특징으로 한다. Deposition in the second process chamber is characterized by the atomic layer deposition method.
첨부된 도면을 참조하여 본 발명에 따른 바람직한 실시예들을 상세하게 설명하면 다음과 같은데 동일한 부분에 대해서는 도면부호만 달리할 뿐 동일한 명칭을 사용하기로 한다. DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, only the same reference numerals will be used for the same parts.
도 7은 본 발명의 일실시예로서 공정챔버부 내부에서 적층구조를 가지는 커패시터 절연막을 증착시키는 방법을 보여준다. FIG. 7 illustrates a method of depositing a capacitor insulating film having a stacked structure inside a process chamber as an embodiment of the present invention.
먼저, 절연기판으로서 웨이퍼를 복수 개의 공정챔버를 포함하는 공정챔버부(도 4의 PC와 동일) 내부로 이송시키고 상기 공정챔버부 내부압력을 낮춘다. First, the wafer is transferred as an insulating substrate into a process chamber portion (same as the PC of FIG. 4) including a plurality of process chambers and the internal pressure of the process chamber portion is lowered.
상기 공정챔버부의 내부 압력을 낮추면 상기 공정챔버부에 포함되는 복수 개의 공정챔버 내부압력 역시 동일한 압력으로 낮아지며, 상기 압력은 금속 산화물의 증착을 위한 것임을 고려한다면 진공상태가 바람직하다. When the internal pressure of the process chamber is lowered, the internal pressures of the plurality of process chambers included in the process chamber are also lowered to the same pressure, and a vacuum state is preferable considering that the pressure is for the deposition of metal oxides.
상기 공정챔버부 내부가 일정 압력으로 유지도면 웨이퍼를 제1공정챔버로 이송시켜 안치한 다음 상기 제1공정챔버 내부를 밀폐시키고 상기 웨이퍼의 하부전극 상에 화학기상증착방식에 의해 제1금속 산화막을 증착시킨다(S220). When the inside of the process chamber is maintained at a constant pressure, the wafer is transferred to the first process chamber and placed therein, the inside of the first process chamber is sealed, and the first metal oxide film is deposited on the lower electrode of the wafer by chemical vapor deposition. (S220).
상기 제1금속 산화막을 이루는 금속은 알루미늄이 바람직하며, 알루미늄 산화막으로 증착하기 위한 알루미늄 재료물질로서 알루미늄을 함유하는 어느 하나의 알루미늄 금속화합물에 한정하는 것은 아니지만Al(CH3)3, AlCl3, Al(CH4)3, Al(CH4)3, Al(CH3)2Cl, Al(CH4)2Cl, Al(O-iC3H7)3, Al(O-tC4H9)3, Al(BH4)3, (CH3)Al(O-iC3H7), (CH3)2Al(O-tC4H4), (C2H5)2Al(O-iC3H7), Al(OEt)3, Al(OPr)3 중의 어느 하나를 사용하는 것이 바람직하다. The metal constituting the first metal oxide film is preferably aluminum, and is not limited to any one aluminum metal compound containing aluminum as an aluminum material material for deposition into an aluminum oxide film, but may be Al (CH3) 3, AlCl3, Al (CH4). ) 3, Al (CH4) 3, Al (CH3) 2Cl, Al (CH4) 2Cl, Al (O-iC3H7) 3, Al (O-tC4H9) 3, Al (BH4) 3, (CH3) Al (O- It is preferable to use any one of iC3H7), (CH3) 2Al (O-tC4H4), (C2H5) 2Al (O-iC3H7), Al (OEt) 3, and Al (OPr) 3.
상기 제1공정챔버 내부에서 제1금속 산화막으로서 알루미늄 박막이 증착되면 상기 제1공정챔버를 개방시켜 제1금속 산화막이 증착된 웨이퍼를 제2공정챔버로 이송하여 안치시킨 다음 상기 제2공정챔버 내부를 밀폐시켜 상기 제1금속 산화막 상에 제2금속 산화막을 증착시킨다(S24). When the aluminum thin film is deposited as the first metal oxide film inside the first process chamber, the first process chamber is opened to transfer the wafer on which the first metal oxide film is deposited to the second process chamber, and then to be placed therein. Sealing to deposit a second metal oxide film on the first metal oxide film (S24).
상기 제2금속 산화막을 이루는 금속은 산화탄탈륨 또는 산화하프늄(HfO2) 중의 어느 하나가 바람직하며, 상기 산화탄탈륨 박막을 이루는 탄탈륨 재료물질로서Ta(OC2H5)5, Ta(OCH3)5, Ta(OCH3)6, Ta(OC2H5)5, Ta(OC3H7)5, Ta[(OCH(CH3)2]5, Ta(OC4H9)5, Ta[OCH2CH(CH3)2]5, Ta[OCH(CH3)C2H5]5, Ta[OC(CH3)3]5, Ta[N(CH3)2]5, Ta(DPM)4Cl, Ta(thd)5, Ta(OR)5, TaCl5 중의 어느 하나를 사용하는 것이 바람직하다. The metal constituting the second metal oxide film is preferably any one of tantalum oxide or hafnium oxide (HfO2), and as a tantalum material material constituting the tantalum oxide thin film, Ta (OC2H5) 5, Ta (OCH3) 5, Ta (OCH3) 6, Ta (OC2H5) 5, Ta (OC3H7) 5, Ta [(OCH (CH3) 2] 5, Ta (OC4H9) 5, Ta [OCH2CH (CH3) 2] 5, Ta [OCH (CH3) C2H5] 5 , Ta [OC (CH3) 3] 5, Ta [N (CH3) 2] 5, Ta (DPM) 4Cl, Ta (thd) 5, Ta (OR) 5, TaCl5 are preferably used.
한편, 상기 산화하프늄 박막을 이루는 탄탈륨 재료물질로서 Hf(N(C2H5)CH3)4(tetrakis ethyl methyl amino hafnium), Hf(MMP)4(tetrakis 1-methoxy-2-methyl-2-propoxy hafnium) 중의 어느 하나를 사용하는 것이 바람직하다. Meanwhile, as tantalum material forming the hafnium oxide thin film, Hf (N (C2H5) CH3) 4 (tetrakis ethyl methyl amino hafnium) and Hf (MMP) 4 (tetrakis 1-methoxy-2-methyl-2-propoxy hafnium) It is preferable to use either.
웨이퍼를 상기 제1공정챔버에서 제2공정챔버로의 이송시 공정챔버부 내부가 동일한 압력으로 유지되기 때문에 압력 변화는 발생하지 않는다. When the wafer is transferred from the first process chamber to the second process chamber, the pressure change does not occur because the inside of the process chamber is maintained at the same pressure.
즉, 이 실시예에서 산화알루미늄과 산화탄탈륨(또는 산화하프늄)의 증착은 상호 별개 공정챔버인 제1 및 제2공정챔버 내부에서 이루어지나 상기 제1 및 제2공정챔버 사이에서 웨이퍼의 이송은 동일한 압력이 유지된 상태에서 이루어져 종래와 같이 진공상태의 해제 및 복원과정이 없이 하나의 증착시스템으로 복수 개의 금속 산화막을 증착시킬 수 있게 되는 것이다. That is, in this embodiment, deposition of aluminum oxide and tantalum oxide (or hafnium oxide) is carried out inside the first and second process chambers, which are separate process chambers, but the transfer of the wafer between the first and second process chambers is the same. The pressure is maintained so that a plurality of metal oxide films can be deposited in one deposition system without the process of releasing and restoring the vacuum as in the prior art.
도 8은 본 발명에 의한 다른 실시예로서 산화탄탈륨(또는 산화하프늄)을 중심으로 산화알루미늄을 이중으로 적층시키기 위한 공정챔버 내부의 증착과정을 보여준다. FIG. 8 illustrates a deposition process inside a process chamber for double stacking aluminum oxide around tantalum oxide (or hafnium oxide) as another embodiment according to the present invention.
도 7과 달리 이 실시예에서는 제2공정챔버 내부에서 제2금속 산화막의 증착이 완료되면 동일한 압력을 유지한 상태에서 웨이퍼를 다시 제1공정챔버 내부로 이송시켜 안치하고 제1금속 산화막을 재 증착시키는 단계를 더욱 포함하고 있음을 알 수 있다. Unlike in FIG. 7, in this embodiment, when the deposition of the second metal oxide film is completed in the second process chamber, the wafer is transferred to the first process chamber again while the same pressure is maintained, and the first metal oxide film is re-deposited. It can be seen that it further comprises the step of.
따라서 이 실시예 역시도 웨이퍼가 공정챔버 내부에서 제1 및 제2공정챔버 내부로 이송시와, 제2 및 제1공정챔버 내부로 이송시는 상기 공정챔버부 내부는 계속적으로 동일한 압력이 유지된 상태에서 이루어지므로 진공상태의 해제 및 복원과정이 없는 하나의 증착시스템으로 증착될 수 있는 것이다. Accordingly, this embodiment also maintains the same pressure in the process chamber part when the wafer is transferred from the process chamber into the first and second process chambers and when the wafer is transferred into the second and first process chambers. Since it is made in the vacuum state can be deposited in one deposition system without the release and recovery process.
이 실시예에서의 제1금속 산화막 및 제2금속 산화막을 이루는 각 금속물질은 도 7에서 상술한 재료물질과 동일하다. Each metal material constituting the first metal oxide film and the second metal oxide film in this embodiment is the same as the material material described above in FIG.
상기에서는 본 발명에 따른 바람직한 실시예인 이중구조의 절연막 또는 삼중구조의 절연막에 한정하여 설명하였으나 본 발명은 이에 한정되지 않고 다층구조의 절연막을 형성시킬 수 있도록 변경 또는 수정될 수 있음은 자명하며 이러한 자명한 범위내의 변경 또는 수정은 본 발명의 권리범위내에 속한다 할 것이다. In the above description, the present invention is limited to the double-layered insulating film or the triple-layered insulating film, which is a preferred embodiment of the present invention. However, the present invention is not limited thereto, and it is apparent that the present invention may be changed or modified to form a multilayered insulating film. Changes or modifications within the scope will be within the scope of the present invention.
본 발명에 의하면 커패시터의 절연막으로서 복수 개의 금속 산화막을 증착시키는 경우 분리된 증착시스템이 아닌 하나의 연결된 증착시스템으로 가능한 이점이 있다. According to the present invention, when depositing a plurality of metal oxide films as an insulating film of a capacitor, there is an advantage in one connected deposition system instead of a separate deposition system.
또한, 본 발명은 하나의 증착시스템으로 복수 개의 절연막을 동시에 증착시킬 수 있어 잦은 진공상태의 해제 및 복원과정에 따른 생산성의 저하를 방지할 수 있게 해준다. In addition, the present invention can be deposited a plurality of insulating films at the same time in one deposition system to prevent a decrease in productivity due to the frequent release and restoration of the vacuum state.
도 1은 종래 산화탄탈륨을 절연막으로 가지는 커패시터의 단면구성도. 1 is a cross-sectional configuration diagram of a capacitor having a tantalum oxide as an insulating film.
도 2는 적층구조의 절연막을 가지는 커패시터의 단면구성도. 2 is a cross-sectional view of a capacitor having an insulating film of a laminated structure.
도 3은 다른 적층구조의 절연막을 가지는 커패시터의 단면구성도. 3 is a cross-sectional view of a capacitor having an insulating film of another laminated structure.
도 4는 종래 적층구조를 가지는 절연막을 형성시키는 공정개략도. 4 is a process schematic diagram of forming an insulating film having a conventional laminated structure.
도 5는 도 2의 적층구조를 가지는 절연막을 형성시키는 공정챔버부 내부의 증착과정도. FIG. 5 is a deposition process diagram inside a process chamber forming an insulating film having the stacked structure of FIG.
도 6은 도 3의 적층구조를 가지는 절연막을 형성시키는 공정챔버부 내부의 증착과정도. 6 is a deposition process diagram inside a process chamber forming an insulating film having the stacked structure of FIG.
도 7은 본 발명의 일 실시예에 따른 공정챔버부 내부의 증착과정도. Figure 7 is a deposition process inside the process chamber according to an embodiment of the present invention.
도 8은 본 발명의 다른 실시예에 따른 공정챔버부 내부의 증착과정도. 8 is a deposition process diagram inside the process chamber according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명 * Explanation of symbols on the main parts of the drawings
10 : 절연기판 20 : 하부전극 10: insulating substrate 20: lower electrode
30 : 산화알루미늄막 40 : 산화탄탈륨막 30 aluminum oxide film 40 tantalum oxide film
50 : 상부전극 PC : 공정챔버부 50: upper electrode PC: process chamber
Claims (6)
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| KR1020030056762A KR101108442B1 (en) | 2003-08-18 | 2003-08-18 | Method of manufacturing a capacitor having high perceptivity, and the capacitor thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017018706A1 (en) * | 2015-07-27 | 2017-02-02 | 주성엔지니어링(주) | Capacitor deposition apparatus and deposition method of dielectric film using same |
| CN108028254A (en) * | 2015-07-27 | 2018-05-11 | 周星工程股份有限公司 | The deposition process of the dielectric film of capacitor precipitation equipment and use the capacitor precipitation equipment |
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| DE69900631T2 (en) * | 1998-06-25 | 2002-08-08 | Citizen Watch Co Ltd | REFLECTIVE LIQUID CRYSTAL DISPLAY |
| US6660660B2 (en) * | 2000-10-10 | 2003-12-09 | Asm International, Nv. | Methods for making a dielectric stack in an integrated circuit |
| KR100433041B1 (en) * | 2001-12-27 | 2004-05-24 | 동부전자 주식회사 | method for producting a capacitor of a semiconductor memory |
| KR20030063643A (en) * | 2002-01-23 | 2003-07-31 | 삼성전자주식회사 | Method of forming semiconductor capacitor with tantalum-nitride dielectric layer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2017018706A1 (en) * | 2015-07-27 | 2017-02-02 | 주성엔지니어링(주) | Capacitor deposition apparatus and deposition method of dielectric film using same |
| CN108028254A (en) * | 2015-07-27 | 2018-05-11 | 周星工程股份有限公司 | The deposition process of the dielectric film of capacitor precipitation equipment and use the capacitor precipitation equipment |
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