KR20050012577A - Method for forming gate buffer spacer of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a gate buffer spacer of a semiconductor device is provided to prevent a bridge between a gate and a bit line by omitting etch process for opening a cell region. CONSTITUTION: A gate structure(59) is formed on a semiconductor substrate(51) defined by a cell region(I) and a peripheral region(II). A nitride spacer(65a) is formed at both sidewalls of the gate structure. An oxide spacer(67a) is formed on the nitride spacer. The oxide spacer on the peripheral region is selectively removed, and then ion-implantation is performed at the peripheral region. An interlayer dielectric(73) is formed on the resultant structure. A second photoresist pattern(75) is formed on the interlayer dielectric to define a landing plug contact region of the cell region. A landing plug contact hole is then formed by sequentially removing the interlayer dielectric and the oxide spacer on the cell region.

Description

Method for forming gate buffer spacer of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate buffer spacer of a semiconductor device. More particularly, the semiconductor device can improve a defect between a gate and a bit line contact by eliminating an etching step for opening a cell region and forming a gate spacer. A method of forming a gate buffer spacer is provided.

Among the problems that have recently occurred due to the reduction of the cell size, there is a bunker defect occurring during wet etching to open the cell and a bridge phenomenon in which the gate and the bit line come into contact with each other.

Bunker defects among these problems will be described with reference to a method of forming a gate buffer spacer of a semiconductor device according to an embodiment of the prior art as follows.

FIG. 1 is a cross-sectional view illustrating a principle of bunker defects occurring when a metal wiring contact is formed using a gate buffer spacer of a semiconductor device according to an embodiment of the prior art.

FIG. 2 is a photograph showing a bunker defect occurring when a gate buffer spacer is formed in a semiconductor device according to the prior art.

According to one embodiment of the prior art, a polysilicon layer and a tungsten thin film are formed on the device region after forming the device isolation film 13 defining the device region and the field region in the semiconductor substrate 11, as shown in FIG. And sequentially stacking a hard mask film, and then applying a photosensitive material layer on the hard mask film.

Thereafter, the photosensitive material layer is selectively removed through an exposure and development process using a photolithography process technology to form a photoresist pattern (not shown).

Subsequently, the hard mask layer, the tungsten thin film, and the polysilicon layer are sequentially removed by using the photoresist pattern (not shown) as a mask to form the polysilicon layer pattern 15, the tungsten thin film pattern 17, and the hard mask layer pattern 19. To form. In this case, the silicon layer pattern 15, the tungsten thin film pattern 17, and the hard mask layer pattern 19 form a gate structure.

Then, after removing the photoresist pattern (not shown), the spacer buffer oxide film 21 is thinly deposited on the semiconductor substrate 11 including the surface of the gate structure, and then the nitride film 23 is deposited on the spacer buffer oxide film 21. Form. In this case, cracks are formed at the upper edge of the gate structure during deposition or other influence, which is excessively wet dip out to remove the oxide layer of the cell region during wet etching to open the cell in a subsequent process. ) Will be made.

Subsequently, although not shown in the drawings, an interlayer oxide film (not shown) is deposited on the upper surface of the entire structure, and then an etching process is performed to open the cell. The nitride film 23 and the buffer including the interlayer oxide film (not shown) are etched. The oxide film 21 is sequentially removed.

In this case, as in " A " of FIG. 1, an oxide dip chemical solution penetrates into a gap generated by a nitride film crack. The chemical solution penetrates to the silicon substrate by meeting the gate spacer buffer oxide film 21, resulting in a bunker defect. By forming various defects will appear.

Accordingly, the photo of the bunker defects caused by the penetration of the oxide chemical solution into the gap formed in the upper edge of the gate during the wet etching for the cell opening through the buffer oxide film to the silicon substrate is well shown in FIG. 2.

Meanwhile, a method of forming a gate buffer spacer of a semiconductor device according to another embodiment of the prior art with respect to a bridge phenomenon in a typical landing plug contact (LPC) of the prior art will be described with reference to FIG. 3.

3 is a cross-sectional view illustrating a landing plug contact bridge phenomenon occurring when a gate buffer spacer is formed in a semiconductor device according to another embodiment of the related art.

4 is a photograph showing a typical landing plug contact bridge phenomenon occurring when a gate buffer spacer is formed in a semiconductor device according to another embodiment of the prior art.

According to another embodiment of the related art, a method of forming a gate buffer spacer of a semiconductor device includes a device region in a semiconductor substrate 31 divided into a cell edge portion I and a cell center portion II, as shown in FIG. After forming an isolation layer (not shown) defining a field region, a polysilicon layer pattern 33, a tungsten thin film 35, and a hard mask layer pattern 37 are formed on the device region to form a gate structure 39. do.

After that, the spacer nitride film 41 is deposited on the surface of the gate structure 39, and the interlayer oxide film 43 is thickly deposited on the upper surface of the entire structure to sufficiently cover the gate structure 39.

Subsequently, a photosensitive film pattern 45 defining a landing plug contact region is formed on the interlayer oxide layer 43 to form a landing plug contact.

Thereafter, the interlayer oxide layer 45 and the nitride layer 41 for spacers are selectively removed using the photosensitive layer pattern 45 as a mask to form a landing plug contact (not shown).

Subsequently, the bit line forming process proceeds to the same process as the existing process.

However, according to another embodiment of the prior art, the difference in the CMP process or the like due to the step (i.e. oxide thickness, etc.) between the cell edge portion (I) and the cell center portion (II) (i. B1 ", but at the center of the cell," B2 ") is generated, and the etching of the LPC contact requires etching of oxide and nitride, which makes it difficult to control the etching degree. Will be shown.

As a result, as shown in FIG. 4, when the plug poly is deposited, a bridge is caused to cause a defect.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and does not perform an etching process for opening the cell region, and thus a semiconductor device capable of preventing defects caused by chemicals introduced through the gate buffer spacer. It is an object of the present invention to provide a method for forming a gate buffer spacer.

1 is a cross-sectional view of a semiconductor device for explaining a bunker defect occurring when a gate buffer spacer is formed in a semiconductor device according to an embodiment of the prior art;

2 is a photo showing a bunker defect (bunker defect) occurring when forming a gate buffer spacer of a semiconductor device according to the prior art,

3 is a cross-sectional view of a device for describing a landing plug contact bridge phenomenon occurring when a gate buffer spacer is formed in a semiconductor device according to another embodiment of the prior art;

4 is a photograph showing a typical landing plug contact bridge phenomenon occurring when a gate buffer spacer is formed in a semiconductor device according to another embodiment of the prior art;

5A through 5F are cross-sectional views illustrating a method of forming a gate buffer spacer in a semiconductor device according to the present invention.

[Description of Drawing Reference]

51 semiconductor substrate 53 polysilicon layer pattern

55: tungsten layer pattern 57: hard mask layer pattern

59 gate structure 61 buffer oxide film

63: buffer nitride film 65: spacer nitride film

65a: nitride film spacer 67: spacer oxide film

67a: oxide film spacer 69: first photosensitive film pattern

71: ion implantation process 73: interlayer oxide film

75: second photosensitive film pattern

According to an aspect of the present invention, there is provided a method of forming a gate buffer spacer of a semiconductor device, the method including: forming a gate structure on a semiconductor substrate divided into a cell region and a peripheral circuit region;

Forming a nitride film spacer on the sidewall of the gate structure;

Forming a spacer oxide film on the nitride film spacer;

Forming a first photoresist pattern on the cell region and then selectively removing the spacer oxide layer in the peripheral circuit region to form a spacer oxide layer on the nitride film spacer in the peripheral circuit region and performing ion implantation;

Removing the first photoresist pattern and forming an interlayer oxide film on an upper surface of the entire structure;

Forming a second photoresist pattern defining a landing plug contact region of a cell region on the interlayer insulating layer of the peripheral circuit region; And

And forming a landing plug contact hole by sequentially removing the interlayer oxide layer and the spacer oxide layer in the cell region using the second photoresist pattern as a mask.

(Example)

Hereinafter, a method of forming a gate buffer spacer of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

5A through 5F are cross-sectional views illustrating a method of forming a gate buffer spacer of a semiconductor device according to the present invention.

In the method for forming a gate buffer spacer of a semiconductor device according to the present invention, as shown in FIG. 5A, device regions and field regions are defined in a semiconductor substrate 51 divided into a cell region I and a peripheral circuit region II. After forming an isolation layer (not shown), a polysilicon layer, a tungsten thin film, and a hard mask film are sequentially stacked on the device region, and then a photosensitive material layer is coated on the hard mask film.

Thereafter, the photosensitive material layer is selectively removed after undergoing exposure and development processes using a photolithography process technology to form a photoresist pattern (not shown).

Subsequently, the hard mask layer, the tungsten thin film, and the polysilicon layer are sequentially removed by using the photoresist pattern (not shown) as a mask to form the polysilicon layer pattern 53, the tungsten thin film pattern 55, and the hard mask layer pattern 57. To form. In this case, the polysilicon layer pattern 53, the tungsten thin film pattern 55, and the hard mask layer pattern 57 form a gate structure 59.

Then, after removing the photoresist pattern (not shown), the buffer oxide film 61 and the buffer nitride film 63 are sequentially deposited on the semiconductor substrate 51 including the surface of the gate structure 59 in sequence.

Subsequently, as shown in FIG. 5B, a gate spacer nitride film 65 is deposited on the buffer nitride film 63. In this case, the spacer nitride layer 65 of the cell region is to be used for the gate spacer, and later to secure the etching target and control margin during the landing plug contact (LPC), the spacer nitride layer of the peripheral circuit region Part 65 is used as a gate spacer.

Next, as shown in FIG. 5C, the gate spacer nitride film 65 is etched back to form a nitride film spacer 65a on the sidewall of the gate structure 59.

Subsequently, as shown in FIG. 5D, an oxide film 67 for a gate spacer is deposited on the upper surface of the entire structure including the nitride film spacer 65a.

Next, as shown in FIG. 5E, after forming the first photoresist pattern 69 in a portion corresponding to the cell region I, the peripheral circuit region II is formed by using the first photoresist pattern 69 as a barrier. The oxide film 67 for gate spacers is selectively removed to form an oxide film spacer 67a, and then an N + or P + ion implantation step 71 is formed.

Subsequently, as shown in FIG. 5F, after removing the first photoresist layer pattern 69, an interlayer oxide layer 73 is deposited on the upper surface of the entire structure, and then the interlayer oxide layer 73 corresponding to the peripheral circuit region II is formed. A second photoresist pattern 73 is formed on the substrate. In this case, the second photoresist pattern 73 exposes the landing plug contact region in the cell region I.

Next, the interlayer oxide film 73, the spacer oxide film 67, the buffer oxide film 61, and the buffer nitride film 63 of the cell region I are sequentially removed by using the second photoresist pattern 73 as a barrier. A plug contact hole (not shown) is formed.

As described above, according to the buffer spacer forming method of the semiconductor device according to the present invention, since the etching process for opening the cell region is not performed, defects caused by the chemical flowing through the gate buffer spacer can be prevented. . That is, it is possible to solve the defects formed by excessive wet etching.

Therefore, according to the present invention, it is possible to solve the bridge phenomenon due to the defects caused during the gate spacer etching and the defect of the self-aligned contact, so that the yield of the semiconductor device can be improved and the device characteristics can be improved.

On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (4)

Forming a gate structure on a semiconductor substrate divided into a cell region and a peripheral circuit region; Forming a nitride film spacer on the sidewall of the gate structure; Forming a spacer oxide film on the nitride film spacer; Forming an oxide film spacer on the nitride film spacer of the peripheral circuit region by selectively removing the spacer oxide film of the peripheral circuit region after forming a first photoresist pattern on the cell region and performing ion implantation; Removing the first photoresist pattern and forming an interlayer oxide film on an upper surface of the entire structure; Forming a second photoresist pattern defining a landing plug contact region of a cell region on the interlayer insulating layer of the peripheral circuit region; And And forming a landing plug contact hole by sequentially removing the interlayer oxide layer and the spacer oxide layer in the cell region using the second photoresist pattern as a mask. 2. The method of claim 1, further comprising laminating a buffer oxide film and a buffer nitride film on a semiconductor substrate including a gate structure prior to forming the nitride film spacer. 2. The method of claim 1, wherein the gate structure is a laminated structure of a polysilicon layer, a tungsten thin film, and a hard mask nitride film. The method of claim 1, further comprising forming a landing plug made of tungsten in the landing plug contact hole.