KR20050010259A - Method for forming anti-reflective coating layer in a semiconductor device - Google Patents
Method for forming anti-reflective coating layer in a semiconductor device Download PDFInfo
- Publication number
- KR20050010259A KR20050010259A KR1020030049296A KR20030049296A KR20050010259A KR 20050010259 A KR20050010259 A KR 20050010259A KR 1020030049296 A KR1020030049296 A KR 1020030049296A KR 20030049296 A KR20030049296 A KR 20030049296A KR 20050010259 A KR20050010259 A KR 20050010259A
- Authority
- KR
- South Korea
- Prior art keywords
- titanium
- layer
- titanium oxide
- metal layer
- titanium nitride
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 금속배선 형성 방법에 관한 것으로, 더욱 상세하게는 금속배선을 패터닝할 때 난반사로 인한 불량을 방지하기 위한 반사방지막 형성 방법에 관한 것이다.The present invention relates to a method for forming metal wiring of a semiconductor device, and more particularly to a method for forming an antireflection film for preventing defects due to diffuse reflection when patterning the metal wiring.
일반적으로 반도체 소자의 제조 공정에서 알루미늄(Al) 등으로 금속층을 형성하는 경우 후속 노광 공정시 발생될 수 있는 난반사를 방지하기 위해 금속층 상에 반사방지막(Anti-Reflective Coating Layer)을 형성한다.In general, when the metal layer is formed of aluminum (Al) in the manufacturing process of the semiconductor device, an anti-reflective coating layer is formed on the metal layer in order to prevent diffuse reflection that may occur in a subsequent exposure process.
종래에는 소정의 소자 제조 공정을 거친 반도체 기판 상에 절연막을 형성한 후 물리기상증착(PVD) 또는 화학기상증착(CVD) 방법으로 절연막 상에 알루미늄(Al)과 같은 금속을 증착한다. 스퍼터링(Sputtering) 방법으로 금속층 상에 티타늄(Ti)을 먼저 증착하고, 질소(N2) 분위기에서 반응성 스퍼터링 방법으로 티타늄 나이트라이드(TiN)를 증착하여 티타늄(Ti)/티타늄 나이트라이드(TiN) 적층 구조의 반사방지막을 형성한다.Conventionally, after forming an insulating film on a semiconductor substrate having a predetermined device manufacturing process, a metal such as aluminum (Al) is deposited on the insulating film by physical vapor deposition (PVD) or chemical vapor deposition (CVD). Titanium (Ti) is first deposited on the metal layer by the sputtering method, and titanium nitride (TiN) is deposited by the reactive sputtering method in a nitrogen (N 2 ) atmosphere to deposit titanium (Ti) / titanium nitride (TiN). An antireflection film of the structure is formed.
이 후 금속배선 형성용 마스크를 이용한 사진 및 식각 공정으로 상기 반사방지막 및 금속층을 패터닝하여 하부 금속배선을 형성한다. 전체 상부면에 금속층간 절연막을 형성하고 상기 하부 금속배선의 소정 부분이 노출되도록 상기 금속층간 절연막을 패터닝하여 비아홀(Via hole)을 형성한 후 상기 비아홀을 통해 상기 하부 금속배선과 연결되도록 상부 금속배선을 형성한다.Thereafter, the anti-reflection film and the metal layer are patterned by a photo and etching process using a mask for forming a metal wiring to form a lower metal wiring. A metal interlayer insulating film is formed on the entire upper surface, and the metal interlayer insulating film is patterned to expose a predetermined portion of the lower metal wiring to form a via hole, and the upper metal wiring is connected to the lower metal wiring through the via hole. To form.
그런데 상기와 같은 종래의 공정에서는 상기 비아홀을 형성하기 위한 식각 공정시 상기 반사방지막의 티타늄(Ti)층을 식각정지층으로 이용하기 때문에 약간의과도식각이 이루어지더라도 하부의 금속층이 손상될 수 있다. 금속층이 손상되면 배선저항이 증가되거나 누설전류가 발생될 수 있으며, 플라즈마에 의한 피해(plasma induced damage) 등을 유발할 수 있다.However, in the conventional process as described above, since the titanium (Ti) layer of the anti-reflection film is used as an etch stop layer during the etching process for forming the via hole, even a slight transient etching may damage the lower metal layer. . If the metal layer is damaged, wiring resistance may be increased or leakage current may be generated, and plasma induced damage may be caused.
이러한 문제를 해결하기 위해 티타늄 나이트라이드(TiN)층을 식각정지층으로 이용하면 웨이퍼의 평탄도 차이로 인해 식각 부족이 일어나는 부분에서는 비아홀이 완전히 개공되지 않아 금속배선 간의 접속이 불량해진다.In order to solve this problem, when the titanium nitride (TiN) layer is used as an etch stop layer, the via hole is not completely opened in the portion where the etching is insufficient due to the difference in the flatness of the wafer, and the connection between the metal wirings is poor.
따라서 본 발명은 티타늄(Ti), 티타늄 산화막(TiO) 및 티타늄 나이트라이드(TiN)가 적층된 구조의 반사방지막을 형성함으로써 상기한 단점을 해소할 수 있는 반도체 소자의 반사방지막 형성 방법을 제공하는 데 그 목적이 있다.Accordingly, the present invention provides a method of forming an anti-reflection film of a semiconductor device that can solve the above disadvantages by forming an anti-reflection film having a structure in which titanium (Ti), titanium oxide (TiO) and titanium nitride (TiN) are laminated. The purpose is.
도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 반사방지막 형성 방법을 설명하기 위한 단면도.1A to 1D are cross-sectional views illustrating a method for forming an antireflection film of a semiconductor device according to the present invention.
도 2는 도 1b를 설명하기 위한 스퍼터링 장비의 구조도.FIG. 2 is a structural diagram of sputtering equipment for explaining FIG. 1B. FIG.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
21: 반도체 기판 22: 절연막21: semiconductor substrate 22: insulating film
23: 금속층 24: 타티늄23: metal layer 24: titanium
25: 티타늄 산화막 26: 타타늄 나이트라이드25: titanium oxide film 26: titanium nitride
27: 반사방지막 28: 층간 절연막27: antireflection film 28: interlayer insulating film
29: 비아홀 30: 플러그29: via hole 30: plug
상기한 목적을 달성하기 위한 본 발명은 반도체 기판에 형성된 절연막 상에 금속층을 형성한 후 상기 금속층 상에 반사방지막을 형성하기 위해 티타늄, 티타늄 산화막 및 티타늄 나이트라이드를 증착하는 것을 특징으로 한다.The present invention for achieving the above object is characterized by depositing titanium, titanium oxide film and titanium nitride to form an antireflection film on the metal layer after forming a metal layer on the insulating film formed on a semiconductor substrate.
상기 티타늄 산화막 및 티타늄 나이트라이드는 동일 챔버에서 연속적으로 증착하며, 상기 티타늄 산화막 및 티타늄 나이트라이드를 증착하기 위해 상기 챔버에 산소 및 질소를 순차적으로 플로우시키는 것을 특징으로 한다.The titanium oxide film and the titanium nitride are continuously deposited in the same chamber, and oxygen and nitrogen are sequentially flowed into the chamber to deposit the titanium oxide film and the titanium nitride.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 반사방지막 형성 방법을 설명하기 위한 단면도로서, 도 2를 참조하여 설명하면 다음과 같다.1A to 1D are cross-sectional views for describing a method of forming an anti-reflection film of a semiconductor device according to the present invention, which will be described below with reference to FIG. 2.
도 1a를 참조하면, 소정의 소자 제조 공정을 거친 반도체 기판(21) 상에 절연막(22)을 형성한 후 물리기상증착(PVD) 또는 화학기상증착(CVD) 방법으로 상기 절연막(22) 상에 알루미늄(Al)과 같은 금속을 증착하여 금속층(23)을 형성한다. 이 후 스퍼터링 방법으로 금속층(23) 상에 티타늄(Ti; 24)을 증착한다.Referring to FIG. 1A, an insulating film 22 is formed on a semiconductor substrate 21 that has undergone a predetermined device fabrication process, and then, on the insulating film 22 by physical vapor deposition (PVD) or chemical vapor deposition (CVD). A metal layer 23 is formed by depositing a metal such as aluminum (Al). Thereafter, titanium (Ti) 24 is deposited on the metal layer 23 by the sputtering method.
도 1b를 참조하면, 상기 티타늄(24) 상에 티타늄 산화막(TiO; 25) 및 티타늄 나이트라이드(TiN; 26)를 순차적으로 증착하여 티타늄(Ti)/티타늄 산화막(TiO)/티타늄 나이트라이드(TiN)로 이루어진 반사방지막(27)을 형성한다. 이 때 티타늄 산화막(TiO; 25) 및 티타늄 나이트라이드(TiN; 26)는 동일 챔버에서 형성하는데, 먼저, 챔버(30) 내의 웨이퍼 지지대(32) 상에 상기 반도체 기판(21)을 위치시킨 후 타겟(31)에 직류(DC) 바이어스 전압을 인가한 상태에서 챔버(30)의 가스 주입구(33)를 통해 내부로 산소(O2)를 플로우시키면 프라즈마(plasma)에 의해 타겟(31)으로부터 스퍼터된 티타늄(Ti)과의 반응성 스퍼터링(reactive sputtering)에 의해 상기 티타늄(24) 상에 티타늄 산화막(25)이 형성된다. 이 후 산소(O2)의 공급을 중단하고 질소(N2)를 플로우시켜 티타늄 산화막(25) 상에 티타늄 나이트라이드(26)가 형성되도록 한다.Referring to FIG. 1B, a titanium oxide (TiO) 25 and a titanium nitride (TiN; 26) are sequentially deposited on the titanium 24 to form titanium (Ti) / titanium oxide (TiO) / titanium nitride (TiN). To form an antireflection film 27. At this time, the titanium oxide film TiO and the titanium nitride 26 are formed in the same chamber. First, the semiconductor substrate 21 is placed on the wafer support 32 in the chamber 30, and then the target is formed. When oxygen (O 2 ) flows through the gas inlet 33 of the chamber 30 in a state in which a direct current (DC) bias voltage is applied to the 31, sputtered from the target 31 by a plasma. A titanium oxide film 25 is formed on the titanium 24 by reactive sputtering with titanium (Ti). After that, the supply of oxygen (O 2 ) is stopped and nitrogen (N 2 ) is flowed to form titanium nitride 26 on the titanium oxide film 25.
도 1c를 참조하면, 상기 반사방지막(27) 및 금속층(23)을 패터닝하여 하부금속배선을 형성한 후 전체 상부면에 층간 절연막(28)을 형성하고 상기 반사방지막(27)의 소정 부분이 노출되도록 상기 금속층간 절연막(28)을 패터닝하여 비아홀(29)을 형성한다.Referring to FIG. 1C, after forming the lower metal wiring by patterning the anti-reflection film 27 and the metal layer 23, an interlayer insulating film 28 is formed on the entire upper surface, and a predetermined portion of the anti-reflection film 27 is exposed. The via interlayer insulating layer 28 is patterned to form a via hole 29.
상기 비아홀(29)을 형성하기 위한 식각 공정시 상기 티타늄 산화막(25)을 식각정지층으로 이용하는데, 본 발명에서는 티타늄(24), 티타늄 산화막(25) 또는 티타늄 나이트라이드(TiN) 중 어느 하나의 층을 식각정지층으로 이용할 수 있기 때문에 과도 식각으로 인한 금속층(23)의 손실을 방지할 수 있다. 또한, 시간에 의한 식각을 진행하지 않더라도 식각 가스(CxFy 등)와 티타늄 나이트라이드(TiN)나 티타늄 산화막(TiO)을 식각할 때 발생되는 물질이 다르므로 식각정지점을 용이하게 검출할 수 있다. 예를 들어, 산화막 식각시 SixOy, SixFy 등과 같은 반응물이 생성된다.In the etching process for forming the via hole 29, the titanium oxide film 25 is used as an etch stop layer. In the present invention, any one of titanium 24, titanium oxide film 25 or titanium nitride (TiN) is used. Since the layer can be used as an etch stop layer, the loss of the metal layer 23 due to excessive etching can be prevented. In addition, since the etching gas (CxFy, etc.) and the materials generated when etching the titanium nitride (TiN) or the titanium oxide layer (TiO) are different, the etching stop point may be easily detected. For example, reactants such as SixOy, SixFy, etc. are generated when the oxide is etched.
도 1d를 참조하면, 상기 비아홀(29)에 금속을 매립하여 플러그(30)를 형성한 후 상기 플러그(30)를 통해 상기 하부 금속배선과 연결되도록 상부 금속배선을 형성한다.Referring to FIG. 1D, after the metal is embedded in the via hole 29 to form a plug 30, an upper metal wiring may be formed to be connected to the lower metal wiring through the plug 30.
상술한 바와 같이 본 발명은 티타늄(Ti), 티타늄 산화막(TiO) 및 티타늄 나이트라이드(TiN)가 적층된 구조의 반사방지막을 형성한다. 따라서 티타늄, 티타늄 산화막 또는 티타늄 나이트라이드 중 어느 하나의 층을 식각정지층으로 이용할 수 있기 때문에 과도 식각으로 인한 금속층의 손실을 방지할 수 있다. 또한, 시간에의한 식각을 진행하지 않더라도 식각 가스와 발생되는 물질이 다르므로 식각정지점을 용이하게 검출할 수 있다.As described above, the present invention forms an antireflection film having a structure in which titanium (Ti), titanium oxide (TiO), and titanium nitride (TiN) are stacked. Therefore, since any one of titanium, titanium oxide, or titanium nitride may be used as an etch stop layer, the loss of the metal layer due to excessive etching may be prevented. In addition, the etching stop point can be easily detected since the etching gas and the generated material are different even if the etching is not performed over time.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030049296A KR20050010259A (en) | 2003-07-18 | 2003-07-18 | Method for forming anti-reflective coating layer in a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030049296A KR20050010259A (en) | 2003-07-18 | 2003-07-18 | Method for forming anti-reflective coating layer in a semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20050010259A true KR20050010259A (en) | 2005-01-27 |
Family
ID=37222709
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020030049296A KR20050010259A (en) | 2003-07-18 | 2003-07-18 | Method for forming anti-reflective coating layer in a semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20050010259A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11495533B2 (en) | 2020-03-27 | 2022-11-08 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
-
2003
- 2003-07-18 KR KR1020030049296A patent/KR20050010259A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11495533B2 (en) | 2020-03-27 | 2022-11-08 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
| US11948882B2 (en) | 2020-03-27 | 2024-04-02 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5326427A (en) | Method of selectively etching titanium-containing materials on a semiconductor wafer using remote plasma generation | |
| US11537016B2 (en) | Method of manufacturing array substrate, and array substrate | |
| US9666727B2 (en) | Display device | |
| US11742241B2 (en) | ALD (atomic layer deposition) liner for via profile control and related applications | |
| KR100333724B1 (en) | Mehod for forming metal wire of semiconductor device by using TiAlN antireflection layer | |
| US6057240A (en) | Aqueous surfactant solution method for stripping metal plasma etch deposited oxidized metal impregnated polymer residue layers from patterned metal layers | |
| US6130155A (en) | Method of forming metal lines in an integrated circuit having reduced reaction with an anti-reflection coating | |
| JP3202657B2 (en) | Method for manufacturing semiconductor device | |
| KR20050010259A (en) | Method for forming anti-reflective coating layer in a semiconductor device | |
| US6017816A (en) | Method of fabricating A1N anti-reflection coating on metal layer | |
| JPH10189594A (en) | Method of forming metal wiring of semiconductor device | |
| JPH07297281A (en) | Method for manufacturing connection hole | |
| JP3288010B2 (en) | Method for forming metal wiring of semiconductor device | |
| US20030166335A1 (en) | Method of forming wiring in semiconductor devices | |
| US6426016B1 (en) | Method for etching passivation layers and antireflective layer on a substrate | |
| KR100255559B1 (en) | Method of forming metal interconnector in semiconductor device | |
| KR100403354B1 (en) | Method for forming contact hole of semiconductor device | |
| KR100284139B1 (en) | Tungsten plug formation method of semiconductor device | |
| US6309963B1 (en) | Method for manufacturing semiconductor device | |
| KR100412145B1 (en) | A method for forming via hole of semiconductor device | |
| JP2000156367A (en) | Dry etching method | |
| KR100458085B1 (en) | Method for fabricating semiconductor device to reduce leakage current and improve electron migration characteristic and stress migration characteristic | |
| KR100406676B1 (en) | Method for forming barrier metal of semiconductor device | |
| KR100338114B1 (en) | Method for forming metal film in semiconductor device | |
| KR19980033882A (en) | Metal wiring formation method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| N231 | Notification of change of applicant | ||
| WITN | Withdrawal due to no request for examination |