KR20050010154A - Method of forming dual damascene pattern in semiconductor device - Google Patents

Method of forming dual damascene pattern in semiconductor device Download PDF

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KR20050010154A
KR20050010154A KR1020030049045A KR20030049045A KR20050010154A KR 20050010154 A KR20050010154 A KR 20050010154A KR 1020030049045 A KR1020030049045 A KR 1020030049045A KR 20030049045 A KR20030049045 A KR 20030049045A KR 20050010154 A KR20050010154 A KR 20050010154A
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trench
via hole
etch stop
film
dual damascene
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KR1020030049045A
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Korean (ko)
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KR101016855B1 (en
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남웅대
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a dual damascene pattern of a semiconductor device is provided to guarantee stability of deposition of an interconnection material and improve a characteristic of a semiconductor device by preventing polymer from being deposited on the protrusion of an organic BARC(bottom anti-reflective coating) in a via first dual damascene process. CONSTITUTION: A via hole etch stop layer(12), the first interlayer dielectric(13), a trench etch stop layer(14) and the second interlayer dielectric(15) that are sequentially formed on a substrate(11) are partially etched to form a via hole(17). A polymer deposition preventing layer(100) is formed along the surface of the resultant structure including the via hole. An organic BARC(18) is formed to fill the inside of the via hole by a predetermined thickness. The layers formed on the trench etch stop layer are etched to form a trench(19) by a trench etch process. The inorganic BARC, the polymer deposition preventing layer and the trench etch stop layer that are exposed by the formation of the trench are sequentially removed to form a dual damascene pattern(179) made of the via hole and the trench.

Description

반도체 소자의 듀얼 다마신 패턴 형성방법{Method of forming dual damascene pattern in semiconductor device}Method of forming dual damascene pattern in semiconductor device

본 발명은 반도체 소자의 듀얼 다마신 패턴 형성방법에 관한 것으로, 특히 비아 퍼스트 듀얼 다마신(via first dual damascene) 공정에서 유기 버텀-반사방지막(organic BARC)으로 비아홀을 매립한 후 트렌치 식각시에 발생하는 폴리머(polymer)가 유기 버텀-반사방지막의 돌출부에 증착되는 것을 방지할 수 있는 반도체 소자의 듀얼 다마신 패턴 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a dual damascene pattern of a semiconductor device. In particular, the present invention relates to a method of forming a dual damascene pattern in a semiconductor device. The present invention relates to a method for forming a dual damascene pattern of a semiconductor device capable of preventing a polymer from being deposited on a protrusion of an organic bottom anti-reflection film.

반도체 소자의 금속배선 형성시 다양한 다마신 방식을 적용하고 있는데, 그 중에서 비아홀을 먼저 형성한 후에 트렌치를 형성하는 비아 퍼스트 듀얼 다마신 방식은 다층 구조의 절연층에 먼저 비아홀을 형성하고, 비아홀을 유기 버텀-반사방지막으로 일정 두께 매립한 후 트렌치 식각 공정을 실시하여 트렌치를 형성한다. 다층 구조의 절연층은 비아홀 식각정지막, 제 1 층간 절연막, 트렌치 식각정지막 및 제 2 층간 절연막이 적층되어 형성된다. 이러한 다층 구조의 절연층에 형성된 비아홀 내부를 유기 버텀-반사방지막으로 매립할 때, 트렌치 식각정지막보다 높게 유기 버텀-반사방지막을 매립하면, 후속 공정인 트렌치 식각 공정 동안 불용성 폴리머가 발생되고, 비아홀 부분에서 돌출되는 유기 버텀-반사방지막의 측벽에 폴리머가 증착되고, 증착된 폴리머층은 포토레지스트 제거(strip) 공정 및 유기 버텀-반사방지막 제거 공정 후에도 비아홀 지역에 남아있게 되어 금속 증착 등 이후 공정에 영향을 주게되어 결국 소자의 특성을 열화 시키게 되는 문제가 있다.Various damascene methods are applied to the formation of metal wirings in semiconductor devices. Among the via first dual damascene methods in which the via holes are formed first and then the trenches are formed, the via holes are first formed in the multilayer insulating layer, and the via holes are organically formed. After filling a predetermined thickness with a bottom anti-reflection film, a trench etching process is performed to form a trench. The multilayer insulating layer is formed by stacking a via hole etch stop film, a first interlayer insulating film, a trench etch stop film, and a second interlayer insulating film. When the inside of the via hole formed in the insulating layer having such a multilayer structure is filled with the organic bottom anti-reflection film, when the organic bottom anti-reflection film is buried higher than the trench etch stop film, an insoluble polymer is generated during the subsequent trench etching process, and the via hole is formed. The polymer is deposited on the sidewalls of the organic bottom-anti-reflective film protruding from the portion, and the deposited polymer layer remains in the via hole even after the photoresist stripping process and the organic bottom-anti-reflective film removing process, so that it can be used in a subsequent process such as metal deposition. There is a problem that affects and eventually degrades the characteristics of the device.

따라서, 본 발명은 비아 퍼스트 듀얼 다마신(via first dual damascene) 공정에서 유기 버텀-반사방지막(organic BARC)의 돌출부에 폴리머가 증착되는 것을 방지하여 소자의 특성을 향상시킬 수 있는 반도체 소자의 듀얼 다마신 패턴 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention is a dual die of a semiconductor device capable of improving the characteristics of the device by preventing the deposition of polymer on the protrusions of the organic BARC in the via first dual damascene process. Its purpose is to provide a method of forming a drinking pattern.

도 1a 내지 1f는 본 발명의 실시예에 따른 반도체 소자의 듀얼 다마신 패턴 형성방법을 설명하기 위한 소자의 단면도.1A to 1F are cross-sectional views of a device for explaining a method of forming a dual damascene pattern of a semiconductor device according to an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

11: 기판 12: 비아홀 식각정지막11: substrate 12: via hole etch stop film

13: 제 1 층간 절연막 14: 트렌치 식각정지막13: first interlayer insulating film 14: trench etch stop film

15: 제 2 층간 절연막 16: 반사방지막15: second interlayer insulating film 16: antireflection film

17: 비아홀 18: 유기 버텀-반사방지막17: via hole 18: organic bottom anti-reflective film

19: 트렌치 179: 듀얼 다마신 패턴19: trench 179: dual damascene pattern

20: 비아홀용 포토레지스트 패턴 21: 트렌치용 포토레지스트 패턴20: photoresist pattern for via hole 21: photoresist pattern for trench

100: 폴리머 증착 방지막100: polymer deposition prevention film

이러한 목적을 달성하기 위한 본 발명의 실시예에 따른 반도체 소자의 듀얼 다마신 패턴 형성방법 기판 상에 순차적으로 형성된 비아홀 식각정지막, 제 1 층간 절연막, 트렌치 식각정지막 및 제 2 층간 절연막의 일부분을 식각하여 비아홀을 형성하는 단계; 상기 비아홀을 포함한 전체 구조 표면을 따라 폴리머 증착 방지막을 형성하는 단계; 유기 버텀-반사방지막을 도포하여 상기 비아홀 내부를 일정 두께 매립하는 단계; 트렌치 식각 공정으로 상기 트렌치 식각정지막 상부의 층들을 식각하여 트렌치를 형성하는 단계; 및 상기 트렌치 형성으로 노출되는 상기 유기 버텀-반사방지막, 상기 폴리머 증착 방지막 및 상기 트렌치 식각정지막을 순차적으로 제거하여 비아홀 및 트렌치로 이루어진 듀얼 다마신 패턴을 형성하는 단계를 포함한다.A method of forming a dual damascene pattern of a semiconductor device according to an embodiment of the present invention for achieving the above object is a portion of the via hole etch stop film, the first interlayer insulating film, the trench etch stop film and the second interlayer insulating film sequentially formed on the substrate Etching to form via holes; Forming a polymer deposition preventing film along the entire structure surface including the via hole; Applying an organic bottom anti-reflection coating to fill a predetermined thickness in the via hole; Forming a trench by etching the layers on the trench etch stop layer by a trench etching process; And sequentially removing the organic bottom-anti-reflection film, the polymer deposition prevention film, and the trench etch stop film exposed by the trench formation to form a dual damascene pattern consisting of via holes and trenches.

상기에서, 폴리머 증착 방지막은 SiON을 화학기상증착법으로 10 ~ 200 Å의 두께로 증착하여 형성한다.In the above, the polymer deposition prevention film is formed by depositing SiON to a thickness of 10 ~ 200 kPa by chemical vapor deposition.

상기 유기 버텀-반사방지막은 상기 트렌치 식각정지막보다 높도록 상기 비아홀을 매립한다.The organic bottom anti-reflection film fills the via hole to be higher than the trench etch stop layer.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명함으로써, 본 발명을 상세하게 설명한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예는 본 발명의 개시가 완전하도록 하며, 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only this embodiment to make the disclosure of the present invention complete, and to those skilled in the art the scope of the invention It is provided for complete information.

도 1a 내지 1f는 본 발명의 실시예에 따른 반도체 소자의 듀얼 다마신 패턴 형성방법을 설명하기 위한 소자의 단면도이다.1A to 1F are cross-sectional views of devices for describing a dual damascene pattern forming method of a semiconductor device according to an embodiment of the present invention.

도 1a를 참조하면, 단위 소자들이 형성된 기판(11) 상에 비아홀 식각정지막(12), 제 1 층간 절연막(13), 트렌치 식각정지막(14) 및 제 2 층간 절연막(15)을 순차적으로 형성한다. 제 2 층간 절연막(15) 상에 반사방지막(16)을 도포하고, 그 상부에 비아홀용 포토레지스트 패턴(20)을 형성한다.Referring to FIG. 1A, a via hole etch stop layer 12, a first interlayer insulating layer 13, a trench etch stop layer 14, and a second interlayer insulating layer 15 are sequentially formed on a substrate 11 on which unit elements are formed. Form. An anti-reflection film 16 is coated on the second interlayer insulating film 15, and a via hole photoresist pattern 20 is formed thereon.

도 1b를 참조하면, 비아홀용 포토레지스트 패턴(20)을 이용한 식각 공정으로 반사방지막(16), 제 2 층간 절연막(15), 트렌치 식각정지막(14), 제 1 층간 절연막(13) 및 비아홀 식각정지막(12)을 순차적으로 식각하여 기판(11)이 저면을 이루는 비아홀(17)을 형성한다. 이후 비아홀용 포토레지스트 패턴(20) 및 반사방지막(16)을 제거한다.Referring to FIG. 1B, an anti-reflection film 16, a second interlayer insulating layer 15, a trench etch stop layer 14, a first interlayer insulating layer 13, and a via hole are formed by an etching process using the photoresist pattern 20 for a via hole. The etch stop layer 12 is sequentially etched to form a via hole 17 having a bottom surface of the substrate 11. Thereafter, the via hole photoresist pattern 20 and the anti-reflection film 16 are removed.

도 1c를 참조하면, 비아홀(17)을 포함한 전체 구조 표면을 따라 폴리머 증착방지막(100)을 형성한다. 폴리머 증착 방지막(100)은 SiON을 화학기상증착법으로 10 ~ 200 Å의 두께로 증착하여 형성한다.Referring to FIG. 1C, a polymer deposition preventing film 100 is formed along the entire structure surface including the via hole 17. The polymer deposition prevention film 100 is formed by depositing SiON to a thickness of 10 to 200 kPa by chemical vapor deposition.

도 1d를 참조하면, 유기 버텀-반사방지막(18)을 비아홀(17) 내부에 트렌치 식각정지막(14) 보다 높도록 도포하며, 이때 제 2 층간 절연막(15) 상부의 폴리머 증착 방지막(100) 표면에도 얇게 도포된다. 유기 버텀-반사방지막(18) 상에 트렌치용 포토레지스트 패턴(21)을 형성한다.Referring to FIG. 1D, an organic bottom anti-reflection film 18 is applied to the inside of the via hole 17 so as to be higher than the trench etch stop layer 14, and at this time, the polymer deposition prevention film 100 on the second interlayer insulating film 15. It is also applied thinly on the surface. A trench photoresist pattern 21 is formed on the organic bottom anti-reflection film 18.

도 1e를 참조하면, 트렌치용 포토레지스트 패턴(21)을 이용한 트렌치 식각 공정으로 폴리머 증착 방지막(100), 유기 버텀-반사방지막(18), 제 2 층간 절연막(15)을 순차적으로 식각하여 트렌치(19)를 형성하고, 이로 인하여 비아홀(17)과 트렌치(19)로 이루어진 듀얼 다마신 패턴(179)이 형성된다.Referring to FIG. 1E, the polymer layer 100, the organic bottom anti-reflection layer 18, and the second interlayer insulating layer 15 are sequentially etched in the trench etching process using the trench photoresist pattern 21 to form the trench ( 19), thereby forming a dual damascene pattern 179 consisting of a via hole 17 and a trench 19.

상기에서, 트렌치 식각 공정 동안 불용성 폴리머가 발생되며, 기존 공정에서는 비아홀(17) 부분에서 트렌치 식각정지막(14) 위로 돌출된 유기 버텀-반사방지막(18)의 측벽에 폴리머가 증착되어 문제를 야기했는데, 도면에 도시된 바와 같이 유기 버텀-반사방지막(18)의 돌출된 부분이 폴리머 증착 방지막(100)으로 둘러싸여 있어 폴리머 증착을 원천적으로 방지시킨다.In the above, insoluble polymer is generated during the trench etching process, and in the conventional process, the polymer is deposited on the sidewall of the organic bottom anti-reflective film 18 protruding from the trench etch stop layer 14 in the via hole 17 to cause a problem. As shown in the drawing, the protruding portion of the organic bottom anti-reflection film 18 is surrounded by the polymer deposition prevention film 100 to prevent polymer deposition.

도 1f를 참조하면, 트렌치용 포토레지스트 패턴(21) 및 유기 버텀-반사방지막(18), 폴리머 증착 방지막(100) 및 트렌치 식각정지막(14)을 순차적으로 제거하고, 이로 인하여, 기판(11)의 일부가 노출된 듀얼 다마신 패턴(179)이 완성된다.Referring to FIG. 1F, the trench photoresist pattern 21, the organic bottom anti-reflection film 18, the polymer deposition prevention film 100, and the trench etch stop film 14 are sequentially removed, and thus, the substrate 11 is removed. A dual damascene pattern 179 in which a portion of) is exposed is completed.

도시하지는 않았지만, 이후 통상의 공정으로 듀얼 다마신 패턴(179) 내에 기판(11)과 접촉되는 금속배선을 형성한다.Although not shown, a metal wiring in contact with the substrate 11 is formed in the dual damascene pattern 179 after a conventional process.

상술한 바와 같이, 본 발명은 비아 퍼스트 듀얼 다마신 공정에서 유기 버텀-반사방지막의 돌출부에 폴리머가 증착되는 것을 폴리머 증착 방지막에 의해 차단시키므로, 이후의 배선재료 증착의 안정성을 확보하여 소자의 특성을 향상시킬 수 있다.As described above, the present invention blocks the deposition of polymer on the protrusions of the organic bottom anti-reflective film by the polymer deposition preventing film in the via first dual damascene process, thereby securing the stability of the subsequent wiring material deposition to improve the characteristics of the device. Can be improved.

Claims (3)

기판 상에 순차적으로 형성된 비아홀 식각정지막, 제 1 층간 절연막, 트렌치 식각정지막 및 제 2 층간 절연막의 일부분을 식각하여 비아홀을 형성하는 단계;Etching a portion of the via hole etch stop layer, the first interlayer insulating layer, the trench etch stop layer, and the second interlayer insulating layer sequentially formed on the substrate to form a via hole; 상기 비아홀을 포함한 전체 구조 표면을 따라 폴리머 증착 방지막을 형성하는 단계;Forming a polymer deposition preventing film along the entire structure surface including the via hole; 유기 버텀-반사방지막을 도포하여 상기 비아홀 내부를 일정 두께 매립하는 단계;Applying an organic bottom anti-reflection coating to fill a predetermined thickness in the via hole; 트렌치 식각 공정으로 상기 트렌치 식각정지막 상부의 층들을 식각하여 트렌치를 형성하는 단계; 및Forming a trench by etching the layers on the trench etch stop layer by a trench etching process; And 상기 트렌치 형성으로 노출되는 상기 유기 버텀-반사방지막, 상기 폴리머 증착 방지막 및 상기 트렌치 식각정지막을 순차적으로 제거하여 비아홀 및 트렌치로 이루어진 듀얼 다마신 패턴을 형성하는 단계를 포함하는 반도체 소자의 듀얼 다마신 패턴 형성방법.Sequentially removing the organic bottom-anti-reflection film, the polymer deposition prevention film, and the trench etch stop film exposed by the trench formation to form a dual damascene pattern consisting of via holes and trenches. Formation method. 제 1 항에 있어서,The method of claim 1, 상기 폴리머 증착 방지막은 SiON을 화학기상증착법으로 10 ~ 200 Å의 두께로 증착하여 형성하는 반도체 소자의 듀얼 다마신 패턴 형성방법.The polymer deposition prevention film is a dual damascene pattern formation method of a semiconductor device formed by depositing SiON to a thickness of 10 ~ 200 으로 by chemical vapor deposition. 제 1 항에 있어서,The method of claim 1, 상기 유기 버텀-반사방지막은 상기 트렌치 식각정지막보다 높도록 상기 비아홀을 매립하는 반도체 소자의 듀얼 다마신 패턴 형성방법.And forming the via hole so that the organic bottom anti-reflection film is higher than the trench etch stop layer.
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