KR20050007699A - Semiconductor device and formation method of metal line in the semiconductor device - Google Patents
Semiconductor device and formation method of metal line in the semiconductor device Download PDFInfo
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- KR20050007699A KR20050007699A KR1020030047269A KR20030047269A KR20050007699A KR 20050007699 A KR20050007699 A KR 20050007699A KR 1020030047269 A KR1020030047269 A KR 1020030047269A KR 20030047269 A KR20030047269 A KR 20030047269A KR 20050007699 A KR20050007699 A KR 20050007699A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
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- H—ELECTRICITY
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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Abstract
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로, 더욱 상세하게는 컨택홀 또는 비아홀의 내부에 금속물질을 매립하기 전에 홀의 내벽에 장벽금속막을 형성하는 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a barrier metal film on an inner wall of a hole before embedding a metal material in a contact hole or a via hole.
반도체 소자가 점차 고집적화, 다층화됨에 따라 중요한 기술의 하나로 다층 배선 기술이 등장하게 되었는데, 다층 배선 기술은 회로 소자가 형성된 반도체 기판 상부에 금속 배선층과 절연막층을 교대로 형성한 후, 절연막에 의해 분리된 금속 배선층 사이를 비아를 통해 전기적으로 접속함으로써 회로 동작이 이루어지도록 하는 것이다.As semiconductor devices have been increasingly integrated and multilayered, multilayer wiring technology has emerged as one of important technologies. In the multilayer wiring technology, a metal wiring layer and an insulating film layer are alternately formed on a semiconductor substrate on which a circuit device is formed, and then separated by an insulating film. The circuit operation is performed by electrically connecting the metal wiring layers through the vias.
이러한 다층 배선 기술을 실현하기 위한 종래 방법에서는, 층간절연막을 선택적으로 식각하여 비아홀을 형성하고, 텅스텐이나 알루미늄의 확산으로부터 산화막을 보호하기 위하여 비아홀의 내벽에 얇은 Ti 및 TiN 장벽금속막을 증착한 다음, 장벽금속막 상에 텅스텐을 형성하여 비아홀을 충진시킨다.In the conventional method for realizing such a multi-layered wiring technology, a via hole is formed by selectively etching the interlayer insulating film, and a thin Ti and TiN barrier metal film is deposited on the inner wall of the via hole to protect the oxide film from diffusion of tungsten or aluminum, Tungsten is formed on the barrier metal film to fill the via holes.
다음, 웨이퍼 표면으로부터 텅스텐을 제거할 목적의 화학기계적 연마공정을 수행한 다음, 알루미늄 증착을 통해 블랭킷층을 형성한 후 패터닝하고 열처리하여 금속 배선층을 형성하며, 이와 같은 금속 배선층 형성공정을 반복하여 다층 배선을 형성한다.Next, a chemical mechanical polishing process for removing tungsten from the wafer surface is performed, and then a blanket layer is formed through aluminum deposition, followed by patterning and heat treatment to form a metal wiring layer, and the metal wiring layer forming process is repeated. Form the wiring.
이와 같이 Ti/TiN을 장벽금속막으로 사용하는 종래 기술로는 한국특허 출원 제2001-38884호가 있다.As such, there is a Korean Patent Application No. 2001-38884, which uses Ti / TiN as a barrier metal film.
그러면, 종래 장벽금속막 형성 공정에 대해 도 1a 내지 도 1c를 참조하여 간략하게 설명한다.Next, a conventional barrier metal film forming process will be briefly described with reference to FIGS. 1A to 1C.
먼저, 도 1a에 도시된 바와 같이, 개별소자가 형성된 반도체 기판의 구조물(1) 상에 하부 절연막(2)을 형성하고, 그 위에 하부 금속배선(3)을 형성한 후, 하부 금속배선(3)을 포함하여 하부 절연막(2)의 상부 전면에 층간절연막(4)을 형성한다.First, as shown in FIG. 1A, the lower insulating film 2 is formed on the structure 1 of the semiconductor substrate on which the individual elements are formed, and the lower metal wiring 3 is formed thereon, and then the lower metal wiring 3 is formed. ), An interlayer insulating film 4 is formed on the entire upper surface of the lower insulating film 2.
이어서, 층간절연막(4)을 선택적으로 식각하여 비아홀(100)을 형성하여 하부 금속배선(3)의 소정영역을 노출시킨다.Subsequently, the interlayer insulating film 4 is selectively etched to form a via hole 100 to expose a predetermined region of the lower metal wiring 3.
다음, 비아홀(100) 내부에 충진될 금속물질과 홀 내벽 간의 접착성 향상, 접촉저항 감소, 및 하부 금속배선(3)의 손상 방지를 목적으로, 비아홀(100)의 내부및 층간절연막(4)의 상부 전면에 제1장벽금속막으로서 Ti막(5)를 형성한다.Next, the internal and interlayer insulating film 4 of the via hole 100 is used for the purpose of improving adhesion between the metal material to be filled in the via hole 100 and the inner wall of the hole, reducing contact resistance, and preventing damage to the lower metal wiring 3. The Ti film 5 is formed on the upper front surface of the first barrier metal film.
이어서, 비아홀(100) 내부에 금속물질을 충진시키는 플러그 형성 공정에서 사용되는 독성가스에 의한 금속 손상을 방지하기 위해, Ti막(5) 상에 제2장벽금속막으로서 TiN막(6)을 70-100Å 정도의 두께로 형성한다.Subsequently, in order to prevent metal damage by toxic gas used in the plug forming process of filling the metal material in the via hole 100, the TiN film 6 is formed on the Ti film 5 as the second barrier metal film. Form a thickness of about -100.
다음, 도 1b에 도시된 바와 같이, TiN막(6) 내의 불순물 제거를 위해 플라즈마 처리한다.Next, as shown in FIG. 1B, plasma treatment is performed to remove impurities in the TiN film 6.
다음, 도 1c에 도시된 바와 같이, TiN막(6) 상에 비아홀(100)의 내부를 충분히 충진시키는 두께로 텅스텐(7)을 형성한다.Next, as shown in FIG. 1C, tungsten 7 is formed on the TiN film 6 to a thickness sufficiently filling the inside of the via hole 100.
이후에는, 층간절연막(5)이 노출될 때까지 텅스텐(7)을 화학기계적 연마하여 제거하고 비아홀의 내부에만 텅스텐을 남겨 플러그를 형성한 다음, 알루미늄을 증착하고 패터닝하여 상부 금속배선을 형성한다.Thereafter, the tungsten 7 is removed by chemical mechanical polishing until the interlayer insulating film 5 is exposed, and the plug is formed by leaving tungsten only in the via hole, and then aluminum is deposited and patterned to form the upper metal wiring.
그러나, 상술한 바와 같은 종래 방법에서 제2장벽금속막인 TiN막(6)을 형성할 때에는 스텝 커버리지(step coverage) 향상을 위해 CVD 방법을 사용하며 이 때 소스물질(source material)로서 티디엠에이티(TDMAT : tetrakis dimethyl amino titanum)를 사용한다.However, in the conventional method as described above, when the TiN film 6, which is the second barrier metal film, is formed, a CVD method is used to improve step coverage, and at this time, TMD (source material) is used. TDMAT: tetrakis dimethyl amino titanum) is used.
그런데 TDMAT는 카본, 수소 등을 포함하고 있어서 TDMAT를 소스물질로 사용한 CVD 방법으로 증착한 TiN막(6) 내에는 불순물이 많다는 문제점이 있다.However, since TDMAT contains carbon, hydrogen, etc., there exists a problem that there are many impurities in the TiN film 6 deposited by the CVD method which used TDMAT as a source material.
또한, 플라즈마 처리에 의해 불순물을 제거하여도 70-100Å 정도의 증착두께를 가지는 TiN막 내에는 불순물이 완전지 제거되지 못하고 여전히 남아있으며, 이로 인해 비아저항이 증가되는 문제점이 있었다.In addition, even when impurities are removed by plasma treatment, impurities are not completely removed but remain in the TiN film having a deposition thickness of about 70-100 micrometers, thereby increasing the via resistance.
그리고, Ti막(5)은 주상구조로 성장되어 막질이 치밀하지 못하므로 장벽특성이 낮다는 문제점이 있다.In addition, since the Ti film 5 is grown in a columnar structure and the film quality is not dense, there is a problem in that the barrier property is low.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 장벽금속막의 막질을 향상시켜 비아저항을 낮추는 것이다.The present invention is to solve the above problems, the object is to improve the film quality of the barrier metal film to lower the via resistance.
본 발명의 다른 목적은 장벽금속막을 치밀화시켜 장벽특성을 향상시키는 것이다.Another object of the present invention is to increase the barrier properties by densifying the barrier metal film.
도 1a 내지 1c는 종래 반도체 소자의 금속 배선층 형성 방법을 도시한 단면도이고,1A to 1C are cross-sectional views illustrating a metal wiring layer forming method of a conventional semiconductor device.
도 2a 내지 2d는 본 발명에 따른 반도체 소자의 금속 배선층 형성 방법을 도시한 단면도이다.2A to 2D are cross-sectional views showing a metal wiring layer forming method of a semiconductor device according to the present invention.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 비아홀 또는 컨택홀의 내벽에 제1장벽금속막으로서 Ti막을 형성한 후 질소 분위기에서 플라즈마를 발생시켜 Ti막의 표면을 질화시킨 후, 그 위에 제2장벽금속막으로서 TiN막을 최소한의 두께로 얇게 증착하는 것을 특징으로 한다.In order to achieve the above object, in the present invention, after forming the Ti film as the first barrier metal film on the inner wall of the via hole or the contact hole, plasma is generated in a nitrogen atmosphere to nitride the surface of the Ti film, and then the second barrier is formed thereon. The TiN film is thinly deposited to a minimum thickness as the metal film.
즉, 본 발명에 따른 반도체 소자의 금속 배선층 형성 방법은, 개별소자 및 하부 금속배선층이 형성된 반도체 기판의 구조물 상에 층간절연막을 형성하는 단계; 층간절연막을 선택적으로 식각하여 하부 금속배선층의 소정 영역을 노출시키는 비아홀을 형성하는 단계; 비아홀의 내벽에 제1장벽금속막을 형성하는 단계; 제1장벽금속막을 플라즈마 처리하는 단계; 및 제1장벽금속막 상에 제2장벽금속막을 20-50Å의 두께로 형성하는 단계; 제2장벽금속막 상에 금속물질을 형성하여 비아홀을 매립하는 금속플러그를 형성하는 단계를 포함하여 이루어진다.That is, the method for forming a metal wiring layer of a semiconductor device according to the present invention comprises: forming an interlayer insulating film on a structure of a semiconductor substrate on which individual elements and a lower metal wiring layer are formed; Selectively etching the interlayer insulating film to form a via hole exposing a predetermined region of the lower metal wiring layer; Forming a first barrier metal film on an inner wall of the via hole; Plasma treating the first barrier metal film; And forming a second barrier metal film on the first barrier metal film at a thickness of 20-50 kPa. And forming a metal plug on the second barrier metal film to fill the via hole.
이 때, 제1장벽금속막으로는 스퍼터링 방법으로 Ti막 또는 Ta막을 형성하는것이 바람직하다.At this time, it is preferable to form a Ti film or a Ta film by the sputtering method as the first barrier metal film.
또한, 제1장벽금속막의 플라즈마 처리 단계에서는 질소 플라즈마를 이용하여 플라즈마 처리하는 것이 바람직하며, 이와 같이 플라즈마 처리하면 장벽금속막의 표면에 질화막이 형성될 수 있다.In the plasma treatment step of the first barrier metal film, it is preferable to perform plasma treatment using nitrogen plasma. In this way, a nitride film may be formed on the surface of the barrier metal film.
그리고, 제2장벽금속막으로는 티디엠에이티(TDMAT : tetrakis dimethyl amino titanum)를 소스물질(source material)로 사용하는 화학기상증착 방법에 의해 TiN막 또는 TaN막을 형성하는 것이 바람직하며, 제2장벽금속막 형성 후에는 플라즈마 처리하는 단계를 더 포함하는 것이 바람직하다.As the second barrier metal film, it is preferable to form a TiN film or a TaN film by a chemical vapor deposition method using TDMAT (tetrakis dimethyl amino titanum) as a source material. It is preferable to further include the step of plasma treatment after film formation.
이하, 본 발명에 따른 반도체 소자의 금속 배선층 형성 방법에 대해 첨부된 도면을 참조하여 상세히 설명한다. 도 2a 내지 2d는 본 발명에 따른 반도체 소자의 금속 배선층 형성 방법을 도시한 단면도이다.Hereinafter, a method for forming a metal wiring layer of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. 2A to 2D are cross-sectional views showing a metal wiring layer forming method of a semiconductor device according to the present invention.
먼저, 도 2a에 도시된 바와 같이, 개별소자가 형성된 반도체 기판의 구조물(11) 상에 하부 절연막(12)을 형성하고, 그 위에 하부 금속배선(13)을 형성한 후, 하부 금속배선(13)을 포함하여 하부 절연막(12)의 상부 전면에 층간절연막(14)을 형성한다.First, as shown in FIG. 2A, the lower insulating film 12 is formed on the structure 11 of the semiconductor substrate on which the individual elements are formed, and then the lower metal wiring 13 is formed thereon, and then the lower metal wiring 13 is formed. An interlayer insulating film 14 is formed on the entire upper surface of the lower insulating film 12, including.
이어서, 층간절연막(14)을 선택적으로 식각하여 비아홀(100)을 형성하여 하부 금속배선(13)의 소정영역을 노출시킨다.Subsequently, the interlayer insulating layer 14 is selectively etched to form a via hole 100 to expose a predetermined region of the lower metal wiring 13.
다음으로, 비아홀(100) 내부에 충진될 금속물질과 홀 내벽 간의 접착성 향상, 접촉저항 감소, 및 하부 금속배선(13)의 손상 방지를 목적으로, 비아홀(100)의 내부 및 층간절연막(14)의 상부 전면에 제1장벽금속막으로서 Ti막(15)를 형성한다.Next, in order to improve adhesion between the metal material to be filled in the via hole 100 and the inner wall of the hole, to reduce contact resistance, and to prevent damage to the lower metal wiring 13, the interior and interlayer insulating film 14 of the via hole 100 may be removed. The Ti film 15 is formed as a first barrier metal film on the upper front surface of the?
장벽금속막으로서 Ti막 대신에 Ta막을 형성할 수도 있다.As the barrier metal film, a Ta film may be formed instead of the Ti film.
다음, 질소 가스를 주입하고 플라즈마를 발생시켜 Ti막(15)을 플라즈마 처리한다.Next, nitrogen gas is injected and plasma is generated to plasma-treat the Ti film 15.
질소 플라즈마는 Ti막(15) 표면으로 침투해들어가면서 Ti막(15)의 막질을 치밀화시키고 Ti막(15) 표면을 질화시켜 2차장벽금속막의 특성을 갖도록 한다.Nitrogen plasma penetrates into the surface of the Ti film 15 to densify the film quality of the Ti film 15 and to nitride the surface of the Ti film 15 so as to have characteristics of the secondary barrier metal film.
다음, 도 2b에 도시된 바와 같이, Ti막(15) 상에 제2장벽금속막으로서 TiN막(16)을 형성한다. TiN막(16)은 TDMAT를 소스물질로 사용하는 화학기상증착 방법에 의해 형성한다.Next, as shown in FIG. 2B, the TiN film 16 is formed on the Ti film 15 as the second barrier metal film. The TiN film 16 is formed by a chemical vapor deposition method using TDMAT as a source material.
이 때 Ti막(15) 표면이 질화되어 있는 상태이므로 TiN막(16)은 기존의 70-100Å 보다 훨씬 얇은 20-50Å 정도의 두께로 형성하여도 제2장벽금속막 기능을 수행할 수 있다.At this time, since the surface of the Ti film 15 is nitrided, the TiN film 16 may function as the second barrier metal film even when the TiN film 16 is formed to a thickness of about 20-50 kPa, which is much thinner than the existing 70-100 kW.
TiN막(16) 대신에 TaN막을 형성할 수도 있다. 제1 및 제2장벽금속막으로서 각각 Ta막 및 TaN막을 사용한 Ta/TaN 구조는 현재 구리 플러그 공정에서 많이 사용되고 있다.Instead of the TiN film 16, a TaN film may be formed. Ta / TaN structures using Ta films and TaN films as first and second barrier metal films, respectively, are currently used in copper plug processes.
다음, 도 2c에 도시된 바와 같이, TiN막(16) 내의 불순물 제거를 위해 플라즈마 처리한다.Next, as shown in FIG. 2C, a plasma treatment is performed to remove impurities in the TiN film 16.
이 때 TiN막(16)은 20-50Å 정도로 얇은 두께를 가지고 있기 때문에 기존의 70-100Å 정도의 두께를 가지는 경우에 비해 플라즈마 처리에 의한 불순물 제거 효율이 훨씬 높다는 장점이 있다.At this time, since the TiN film 16 has a thickness of about 20-50 microns, the TiN film 16 has an advantage that the impurity removal efficiency by plasma treatment is much higher than that of the conventional 70-100 microns.
다음, 도 2d에 도시된 바와 같이, TiN막(16) 상에 비아홀(100)의 내부를 충분히 충진시키는 두께로 텅스텐(17)을 형성한다.Next, as shown in FIG. 2D, tungsten 17 is formed on the TiN film 16 to a thickness sufficiently filling the inside of the via hole 100.
텅스텐 대신에 구리(Cu)를 형성할 수도 있다.Copper (Cu) may be formed instead of tungsten.
이후에는, 층간절연막(14)이 노출될 때까지 텅스텐(17)을 화학기계적 연마하여 제거하고 비아홀의 내부에만 텅스텐을 남겨 플러그를 형성한 다음, 알루미늄을 증착하고 패터닝하여 상부 금속배선을 형성한다.Subsequently, the tungsten 17 is removed by chemical mechanical polishing until the interlayer insulating layer 14 is exposed, and a plug is formed by leaving tungsten only inside the via hole, and then aluminum is deposited and patterned to form an upper metal wiring.
상술한 바와 같이, 본 발명에서는 1차장벽금속막으로서 형성한 Ti막을 질소 플라즈마로 처리하여 Ti막 표면을 질화한 후, 그 위에 TiN막을 형성하기 때문에 CVD TiN막의 증착두께를 기존의 70-100Å 보다 훨씬 얇은 20-50Å 정도로 형성하며, 따라서 공정시간의 단축 및 비용절감의 효과가 있다.As described above, in the present invention, the Ti film formed as the primary barrier metal film is treated with nitrogen plasma to nitrate the Ti film surface, and then a TiN film is formed thereon, so that the deposition thickness of the CVD TiN film is higher than that of the conventional 70-100 kPa. It forms a much thinner 20-50Å, thus reducing the process time and cost.
또한, CVD TiN막의 증착두께가 얇기 때문에 TiN 증착 후 수행하는 플라즈마 처리에 의한 불순물 제거효율이 뛰어나며, 따라서 TiN의 막질을 향상시켜 비아저항을 낮추는 효과가 있다.In addition, since the deposition thickness of the CVD TiN film is thin, the impurity removal efficiency by plasma treatment performed after TiN deposition is excellent, and thus, the via resistance is reduced by improving the film quality of TiN.
그리고, Ti막을 플라즈마 처리하여 치밀화시키기 때문에 장벽특성이 향상되는 효과가 있다.In addition, since the Ti film is densified by plasma treatment, the barrier property is improved.
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