KR20050002486A - Method for forming contact of semiconductor device - Google Patents
Method for forming contact of semiconductor device Download PDFInfo
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- KR20050002486A KR20050002486A KR1020030043865A KR20030043865A KR20050002486A KR 20050002486 A KR20050002486 A KR 20050002486A KR 1020030043865 A KR1020030043865 A KR 1020030043865A KR 20030043865 A KR20030043865 A KR 20030043865A KR 20050002486 A KR20050002486 A KR 20050002486A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 계면 산화막의 완전한 제거를 이루면서 소자 특성 저하를 방지할 수 있는 반도체 소자의 콘택 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact for a semiconductor device capable of preventing the deterioration of device characteristics while completely removing the interface oxide film.
반도체 소자의 고집적화가 진행됨에 따라 회로 패턴의 크기가 점점 감소되고 있으며, 이러한 경향에 부합해서 우수한 소자 특성을 얻기 위한 다양한 공정 기술들이 적용 및 개발되고 있다. 특히, 소자의 동작 효율을 높이기 위해 콘택 공정에 대한 새로운 공정 기술들이 개발되고 있다.As the integration of semiconductor devices increases, the size of circuit patterns is gradually reduced, and various process technologies are being applied and developed to obtain excellent device characteristics in accordance with this trend. In particular, new process technologies for the contact process are being developed to increase the operation efficiency of the device.
상기 콘택 공정에 대한 새로운 기술의 요구는 패턴 크기의 미세화가 달성되더라도, 상하부 패턴간의 콘택이 불안정하거나 콘택저항이 증가될 경우, 소자의 신뢰성이 확보되지 못함은 물론 고속 동작이 곤란하기 때문이다.The demand for a new technology for the contact process is that even if the size of the pattern is achieved, if the contact between the upper and lower patterns is unstable or the contact resistance is increased, the reliability of the device is not secured and the high speed operation is difficult.
한편, 반도체 소자의 콘택 물질로는 최근까지 배치-타입 퍼니스(batch-type furnace)에서 증착되는 폴리실리콘이 주로 이용되어져 왔다. 이러한 폴리실리콘은 500∼600℃의 퍼니스에서 소오스 가스로 SiH4 가스를 이용하면서 도펀트로서 PH3 가스를 이용하여 증착하며, 이때, 도펀트인 인(P)의 농도는 0.1∼3.0E20원자/㎤ 정도로 하고 있다.Meanwhile, polysilicon deposited in a batch-type furnace has been mainly used as a contact material of a semiconductor device until recently. The polysilicon is deposited using a PH3 gas as a dopant while using SiH4 gas as a source gas in a furnace at 500 to 600 ° C. At this time, the concentration of phosphorus (P) as a dopant is about 0.1 to 3.0E20 atoms / cm 3. .
그러나, 이와 같이 퍼니스에서 증착되는 폴리실리콘은 증착전 공기중의 산소에 노출됨으로써 계면 산화막이 형성되며, 이것이 소자의 콘택 저항 증가 및 신뢰성 저하의 주요 원인이 되고 있다. 이와 같은 계면 산화막의 형성은 폴리실리콘 증착전 전처리 과정인 HF 또는 BOE 용액을 이용한 습식 세정이 익스-시튜(ex-situ)로 진행되는 것이므로 세정 후 퍼니스에 로딩될 때까지 공기중에 노출될 뿐만 아니라, 전처리 습식세정후 대기압 하에서 웨이퍼를 퍼니스에 로딩할 때 존재하는 수십 ppm 정도로 적은 양의 산소 농도에 의한 것이다.However, the polysilicon deposited in the furnace is exposed to oxygen in the air before deposition to form an interfacial oxide film, which is a major cause of increased contact resistance and lower reliability of the device. The formation of such an interfacial oxide film is not only exposed to air until it is loaded into the furnace after cleaning because the wet cleaning using HF or BOE solution, which is a pretreatment process before polysilicon deposition, proceeds ex-situ. This is due to the oxygen concentration as low as several tens of ppm present when loading the wafer into the furnace under atmospheric pressure after pretreatment wet cleaning.
이에, 플러그 물질로서 싱글-타입 에피-실리콘(single-type epitaxial-Si)을이용하려는 연구가 최근에 활발하게 진행되고 있다. 이것은 실리콘 증착전에 인-시튜(in-situ)로 800∼900℃에서 수소-베이크 공정을 진행함으로써 실리콘 증착전 계면의 미세 산화막을 제거할 수 있는 장점이 있기 때문이다.Accordingly, research into using single-type epitaxial-Si as a plug material has been actively conducted in recent years. This is because the hydrogen-baking process is performed in-situ before the silicon deposition at 800 to 900 ° C. to remove the fine oxide film at the interface before the silicon deposition.
그러나, 에피-실리콘은 자체 형성 온도가 900℃ 정도로 너무 높고 수소-베이크의 온도 또한 높기 때문에, 이와 같은 높은 열공정으로 인해 기판 이온주입된 도펀트들의 확산(disffusion) 및 재분포(redistribution)가 일어나므로, 상기 에피-실리콘의 형성은 접합 및 트랜지스터 특성 등을 크게 변동 또는 저하시키는 원인이 되고 있다.However, since epi-silicon has a high self-forming temperature of about 900 ° C. and a high hydrogen-baking temperature, such a high thermal process causes diffusion and redistribution of dopants implanted with the substrate. In addition, the formation of the epi-silicon causes a large variation or decrease in the junction and transistor characteristics.
따라서, 상기 싱글-타입 에피-실리콘 형성시의 문제점을 해결하기 위한 다른 방법으로서, 저온(low temperature) 싱글-타입 에피-실리콘 형성이 제안되었다. 이 방법은 에피-실리콘을 500∼600℃에서 형성할 수 있으며, 인-시튜 상태에서 수소-베이크를 진행할 수 있으므로 계면 산화막을 제거할 수 있을 뿐만 아니라 기존의 화학기상증착(Chemcial Vapor Deposition : CVD) 장비를 그대로 사용할 수 있는 장점이 있어 전술한 퍼니스 폴리실리콘을 대체할 수 있는 물질로 주목 받고 있다.Therefore, as another method for solving the problem in forming the single-type epi-silicon, low temperature single-type epi-silicon formation has been proposed. In this method, epi-silicon can be formed at 500 to 600 ° C., and hydrogen-baking can be performed in-situ to remove the interfacial oxide film as well as conventional chemical vapor deposition (CVD). Since the equipment can be used as it is, it is attracting attention as a material that can replace the furnace polysilicon described above.
그러나, 상기한 저온 싱글-타입 에피-실리콘의 형성방법은 수소-베이크 온도가 후속 열처리 온도로서는 높은 수준인 850℃ 정도이므로, 이러한 수소-베이크가 진행되는 동안 필연적으로 소자 특성 저하가 일어날 수 밖에 없으며, 그래서, 그 이용에 어려움이 있다.However, the method of forming the low temperature single-type epi-silicon described above inevitably deteriorates device characteristics during the hydrogen-baking process because the hydrogen-baking temperature is about 850 ° C, which is a high level as a subsequent heat treatment temperature. , So, there is difficulty in using it.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서,콘택 물질로서 저온 싱글-타입 에피-실리콘을 형성하되, 전처리 공정인 수소-베이크시의 공정 온도에 기인하는 소자 특성 저하를 방지할 수 있는 반도체 소자의 콘택 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, to form a low-temperature single-type epi-silicon as a contact material, to prevent deterioration of device characteristics due to the process temperature during the hydrogen-baking pretreatment process It is an object of the present invention to provide a method for forming a contact for a semiconductor device.
도 1은 저온 싱글-타입 에피-실리콘 형성시 수소-베이크 온도를 변수로 하였을 때의 계면 산화막 양을 보여주는 산소의 농도에 대한 SIMS 분석 그래프.1 is a SIMS analysis graph of the concentration of oxygen showing the amount of interfacial oxide film when the hydrogen-baking temperature is a variable when forming low-temperature single-type epi-silicon.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도.2A to 2C are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 : 반도체 기판 2 : 소자분리막1 semiconductor substrate 2 device isolation film
3 : 게이트 4 : 스페이서3: gate 4: spacer
5 : 층간절연막 6 : 콘택홀5 interlayer insulating film 6 contact hole
7 : 콘택 플러그 8 : 소오스/드레인 영역7: contact plug 8: source / drain area
상기와 같은 목적을 달성하기 위하여, 본 발명은, 소자분리막을 구비한 반도체 기판 상에 게이트를 형성하는 단계; 상기 기판 결과물에 대해 소오스/드레인 이온주입 및 접합 이온주입을 차례로 수행하는 단계; 상기 게이트를 덮도록 기판의 전면 상에 층간절연막을 증착하는 단계; 상기 층간절연막을 식각하여 게이트들 사이의 기판 부분을 노출시키는 콘택홀을 형성하는 단계; 상기 노출된 기판 부분 표면의 이물질이 제거되도록 전처리 하는 단계; 상기 기판 결과물을 싱글 챔버 화학기상증착 장비 내에 장입시키는 단계; 상기 기판 결과물에 대해 콘택 계면의 계면 산화막이 완전 제거되도록 800℃ 미만의 온도로 수소-베이크 하는 단계; 상기 콘택홀 내에 콘택 물질을 매립시키는 단계; 및 상기 기판 결과물을 열처리하여 게이트 양측의 기판 표면에 소오스/드레인 영역을 형성하는 단계를 포함하는 반도체 소자의 콘택 형성방법을 제공한다.In order to achieve the above object, the present invention, forming a gate on a semiconductor substrate having a device isolation film; Performing source / drain ion implantation and junction ion implantation on the substrate result in turn; Depositing an interlayer insulating film on an entire surface of the substrate to cover the gate; Etching the interlayer insulating film to form contact holes exposing substrate portions between gates; Pretreatment to remove foreign material from the exposed surface of the substrate portion; Charging the substrate output into a single chamber chemical vapor deposition apparatus; Hydrogen-baking the substrate resultant to a temperature below 800 ° C. to completely remove the interfacial oxide film at the contact interface; Embedding a contact material in the contact hole; And forming a source / drain region on the surface of the substrate on both sides of the gate by heat-treating the resultant of the substrate.
여기서, 상기 수소-베이크는 수소 가스량을 1∼20slm으로 하고, 공정온도를 600∼800℃로 하여 10∼1000초 동안 수행하며, 인-시튜로 진행한다.Here, the hydrogen-baking is carried out for 10 to 1000 seconds at a hydrogen gas amount of 1 to 20 slm and a process temperature of 600 to 800 ° C., and proceeds in-situ.
상기 콘택 물질로서는 실리콘, 저마늄 또는 실리콘저마늄 중에서 어느 하나를 이용하며, 상기 실리콘일 경우에는 비정질실리콘, 결정질실리콘 또는 에피-실리콘 중에서 어느 하나를 이용한다.As the contact material, any one of silicon, germanium, or silicon germanium is used, and in the case of silicon, any one of amorphous silicon, crystalline silicon, or epi-silicon is used.
본 발명에 따르면, 공정변수들의 조절을 통해 수소-베이크 온도를 750℃ 이하로 낮춤으로써 계면 산화막을 완전히 제거할 수 있음은 물론 접합 및 트랜지스터 특성 저하를 방지할 수 있다.According to the present invention, by lowering the hydrogen-baking temperature to 750 ° C. or lower through the control of process variables, it is possible to completely remove the interfacial oxide film and to prevent the deterioration of the junction and transistor characteristics.
(실시예)(Example)
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1은 저온 싱글-타입 에피-실리콘 형성시의 수소-베이크 온도를 변수로 하였을 때, 계면에 존재하는 미세 계면 산화막의 양을 보여주는 산소의 농도에 대한 SIMS(Secondary Ion Mass Spectroscope) 분석 그래프이다.FIG. 1 is a graph of Secondary Ion Mass Spectroscope (SIMS) analysis of oxygen concentration showing the amount of fine interfacial oxide film present at an interface when the hydrogen-baking temperature at the time of forming a low temperature single-type epi-silicon is a variable.
보여지는 바와 같이, 850℃에서는 수소-베이크를 120초 또는 60초로 진행한 모두의 경우에서 완전히 제거되었음을 볼 수 있지만, 800℃ 미만의 온도에서 수소-베이크를 120초 동안 진행한 경우는 그 산화막 제거 효과가 현저히 떨어짐을 볼 수 있다. 물론, 800℃에서는 산화막 제거 효과가 다소 나타난 것을 볼 수 있다.As can be seen, the hydrogen-baking was completely removed at 850 ° C in all cases of 120 seconds or 60 seconds, but the oxide film was removed when hydrogen-baking was performed for 120 seconds at temperatures below 800 ° C. It can be seen that the effect is significantly reduced. Of course, it can be seen that the oxide film removal effect appeared somewhat at 800 ℃.
이와 같은 결과들은 에피-실리콘 형성 전 온도 이외의 수소-베이크 공정 조건을 변화시키면, 수소-베이크 온도를 낮출 수 있음을 의미한다. 즉, 수소-베이크 시간 및 수소 가스의 양 등을 변화시키면, 수소-베이크 온도를 낮출 수 있다는 것이다.These results indicate that changing the hydrogen-baking process conditions other than the temperature before epi-silicon formation can lower the hydrogen-baking temperature. In other words, the hydrogen-baking temperature can be lowered by changing the hydrogen-baking time and the amount of hydrogen gas.
따라서, 본 발명은 이와 같은 방법으로 수소-베이크 온도를 800℃ 미만으로 낮춤으로써 소자의 접합 및 트랜지스터 특성 저하를 유발함이 없이 계면 산화막이 완전히 제거되도록 한다.Accordingly, the present invention lowers the hydrogen-baking temperature to less than 800 ° C in this manner so that the interfacial oxide film can be completely removed without causing the junction of the device and the deterioration of transistor characteristics.
보다 자세하게, 도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 콘택 형성방법을 설명하기 위한 공정별 단면도로서, 이를 설명하면 다음과 같다.More specifically, FIGS. 2A to 2C are cross-sectional views of processes for describing a method for forming a contact of a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 소자분리막(2)을 구비한 반도체 기판(1) 상에 공지의 공정에 따라 게이트(3)를 형성한다. 그런다음, 게이트(3)의 양측벽에 스페이서(4)를 형성한 후, 기판 결과물에 대해 소오스/드레인 이온주입 및 접합 이온주입을 차례로 수행한다.Referring to FIG. 1A, a gate 3 is formed on a semiconductor substrate 1 having an isolation layer 2 according to a known process. Then, spacers 4 are formed on both side walls of the gate 3, and then source / drain ion implantation and junction ion implantation are sequentially performed on the substrate resultant.
도 1b를 참조하면, 상기 기판 결과물 상에, 예컨데, BPSG막으로 이루어진 층간절연막(5)을 증착한다. 그런다음, 공지의 SAC(Self-Aligned Contact) 공정에 따라 상기 층간절연막(5)을 식각하여 비트라인 콘택 및 스토리지 노드 콘택을 형성하기 위한 콘택홀(6)을 형성한다.Referring to FIG. 1B, an interlayer insulating film 5 made of, for example, a BPSG film is deposited on the substrate resultant. Then, the interlayer insulating layer 5 is etched according to a known self-aligned contact (SAC) process to form a contact hole 6 for forming a bit line contact and a storage node contact.
도 1c를 참조하면, 콘택홀 표면의 불순물을 제거하기 위해 기판 결과물에 대해 전처리 공정을 수행한다. 상기 전처리 공정은 익스-시튜 방식에 따라 습식세정으로 진행함이 바람직하다. 그 다음, 저온 싱글-타입 에피-실리콘 성장을 위해 상기 기판 결과물을 싱글 챔버 CVD 장비 내에 장입시킨 후, 우선, 인-시튜로 수소-베이크 공정을 진행한다.Referring to FIG. 1C, a pretreatment process is performed on a substrate resultant to remove impurities on the contact hole surface. The pretreatment process is preferably carried out by wet cleaning according to the ex-situ method. The substrate output is then loaded into a single chamber CVD apparatus for low temperature single-type epi-silicon growth, followed by a hydrogen-baking process in situ.
여기서, 상기 수소-베이크 공정은 수소 가스량을 1∼20slm 정도로 하고, 그리고, 공정시간을 10∼1000초 정도로 하며, 특히, 이러한 공정변수들의 조절을 통해 공정온도를 800℃ 미만, 바람직하게 600∼800℃ 정도로 종래의 그것에 비해 낮추어 진행한다.Here, the hydrogen-baking process is a hydrogen gas amount of about 1 to 20 slm, and a process time of about 10 to 1000 seconds, in particular, by adjusting the process parameters of the process temperature is less than 800 ℃, preferably 600 to 800 It proceeds lowering compared with the conventional one about degreeC.
이 경우, 공정온도를 낮추더라도 계면 산화막은 완전히 제거 가능하며, 반면, 공정온도를 800℃ 미만으로 낮춤에 따라 수소-베이크가 진행되는 동안에 접합 및 트랜지스터의 특성 저하는 유발하지 않게 된다.In this case, even if the process temperature is lowered, the interfacial oxide film can be completely removed, while the process temperature is lowered below 800 ° C., so that the deterioration of the junction and the transistor during hydrogen-baking does not occur.
계속해서, 수소-베이크에 의해 계면 산화막이 제거된 콘택홀을 포함한 기판 전면 상에 콘택 물질로서 에피-실리콘을 형성한다. 그런다음, 상기 에피-실리콘을 에치백 또는 CMP(Chemical Mechanical Polishing)하여 콘택홀 내에 콘택 플러그(7)를 형성한다.Subsequently, epi-silicon is formed as a contact material on the entire surface of the substrate including the contact hole in which the interfacial oxide film has been removed by hydrogen baking. Then, the epi-silicon is etched back or chemical mechanical polishing (CMP) to form a contact plug 7 in the contact hole.
여기서, 상기 콘택 물질로서는 에피-실리콘을 형성하였지만, 비정질실리콘 또는 결정질실리콘을 형성하는 것도 가능하다. 또한, 콘택 물질로서 실리콘을 이용하였지만, 그 이외에 저마늄(Ge) 또는 실리콘저마늄(SiGe) 등도 이용 가능하다.Here, although epi-silicon is formed as the contact material, it is also possible to form amorphous silicon or crystalline silicon. In addition, although silicon is used as the contact material, germanium (Ge), silicon germanium (SiGe), and the like may also be used.
그 다음, 상기 단계까지의 기판 결과물에 대해 RTP 공정을 이용한 소오스/드레인 열처리를 행하여 게이트(3) 양측의 기판 표면에 소오스/드레인 영역(8)을 형성한 후, 공지의 후속 공정을 진행하여 본 발명에 따른 반도체 소자를 형성한다.Subsequently, the source / drain heat treatment using the RTP process is performed on the substrate resultant up to the above step to form the source / drain regions 8 on the substrate surface on both sides of the gate 3, and then the known subsequent process is performed. To form a semiconductor device according to the invention.
이상에서와 같이, 본 발명은 계면 산화막 제거를 위한 수소-베이크 진행시 공정 변수들을 조절하여 공정온도를 접합 및 트랜지스터 특성에 영향을 미치지 않을 750℃ 이하로 낮춤으로써, 낮은 콘택저항을 얻을 수 있음에 따라 콘택 특성을 확보할 수 있으며, 아울러, 접합 및 트랜지스터의 특성 저하를 방지할 수 있어 소자 특성 및 제조수율을 향상시킬 수 있다.As described above, the present invention can obtain a low contact resistance by adjusting the process parameters during hydrogen-baking for removing the interfacial oxide film and lowering the process temperature to 750 ° C. or less, which will not affect the junction and transistor characteristics. Accordingly, the contact characteristics can be secured, and the deterioration of the characteristics of the junction and the transistor can be prevented, thereby improving device characteristics and manufacturing yield.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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