KR20050002411A - Method of manufacturing flash memory device - Google Patents

Abstract

PURPOSE: A method of manufacturing a flash memory device is provided to improve the difference of EFH(Effective Field oxide Height) between predetermined regions and to secure a process margin by planarizing a polysilicon layer within all the regions. CONSTITUTION: A semiconductor substrate(21) with high voltage gate oxide layer(22A) and a low voltage/cell gate oxide layer(22B) is provided. A sacrificial nitride pattern is formed on a first polysilicon layer(23) of a low voltage transistor/cell region(LV/CELL). An oxide layer is formed by oxidizing the first polysilicon layer of a high voltage transistor region(HV) as much as a predetermined thickness. The oxide layer and the sacrificial nitride pattern are sequentially removed therefrom, so that the first polysilicon layer is planarized within the high voltage transistor region and the low voltage transistor/cell region. A plurality of isolation layers(260) are formed therein. A second polysilicon layer(27) is formed on the planarized first polysilicon layer including the isolation layers.

Description

Method of manufacturing flash memory device {Method of manufacturing flash memory device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a high voltage transistor region in a flash memory device to which a Self Align Shallow Trench Isolation (SA-STI) scheme is applied. And a method of manufacturing a flash memory device capable of improving an effective field oxide height (EFH) difference caused between these regions by protrusions of element isolation films in each of the low voltage transistor / cell regions.

The flash memory has a high voltage transistor and a low voltage transistor for driving a cell due to the characteristics of the device. The gate oxide film of the high voltage transistor is thick, the gate oxide film of the low voltage transistor is thin, and the gate oxide film of the cell is equal to or similar to the thickness of the gate oxide film of the low voltage transistor. The difference caused by the gate oxide thickness difference between the high voltage transistor region and the low voltage transistor / cell region causes the thickness of the nitride film remaining after the chemical mechanical polishing (CMP) process of the device isolation oxide, which is a subsequent process, to be changed in each region. It causes the EFH difference between the high voltage transistor region and the low voltage transistor / cell region. Here, EFH refers to the step of the device isolation layer based on the interface between the first polysilicon layer for floating gate and the second polysilicon layer for floating gate.

1 is a cross-sectional view of a device for explaining a method of manufacturing a conventional flash memory device applying a self-aligned shallow trench isolation scheme.

The flash memory device includes a cell region, a low voltage transistor region, and a high voltage transistor region. For convenience of description, a cell region and a low voltage transistor region having a similar thickness of the gate oxide film are grouped into one region.

Referring to FIG. 1, a thick high voltage gate oxide film 12A is formed on the semiconductor substrate 11 in the high voltage transistor region HV, and on the semiconductor substrate 11 in the low voltage transistor / cell region LV / CELL. A thin low voltage / cell gate oxide film 12B is formed. A first polysilicon layer 13 for floating gate is formed on the gate oxide films 12A and 12B. The SA-STI process is performed to form a plurality of device isolation trenches 15 in the semiconductor substrate 11, and the device isolation layer 160 is formed by filling oxides for device isolation in the trenches 15. A second polysilicon layer 19 for floating gate is formed on the entire structure including the device isolation layer 160. Although not shown, gates are formed in each region by performing an etching process using a floating gate mask, a dielectric film forming process, a control layer conductive layer forming process, and an etching process using a control gate mask.

When the flash memory device is manufactured by the above-described conventional method, an EFH difference is generated between the regions of the device isolation layer 160 of each of the high voltage transistor region HV and the low voltage transistor / cell region LV / CELL. In general, the step EFH1 of the device isolation layer 160 with respect to the first polysilicon layer 13 in the high voltage transistor region HV has a value of (−) 50 to 100 kV, while the low voltage transistor / cell region LV / CELL), the step (EFH2) of the device isolation layer 160 with respect to the first polysilicon layer 13 has a value of 300 to 800 mW. The step EFH2 of the low voltage transistor / cell region LV / CELL is high and has a wide range of values, each of which depends on the progress of the chemical mechanical polishing (CMP) process. The difference in the EFH value between the high voltage transistor region HV and the low voltage transistor / cell region LV / CELL and the high EFH value of the low voltage transistor / cell region LV / CELL are difficult to set the gate etching target of each region. And many problems such as not only obtaining a good gate pattern profile but also causing the device to fail due to polysilicon residues. These problems are becoming more important as devices become more integrated, and efforts have been made to solve them.

Accordingly, the present invention improves the stability of the subsequent process and improves the reliability of the device by improving the surface of the entire area while improving the EFH difference caused between these regions by the protrusions of the device isolation layers of the high voltage transistor region and the low voltage transistor / cell region, respectively. It is an object of the present invention to provide a method of manufacturing a flash memory device that can be improved.

1 is a cross-sectional view of a device for explaining a method of manufacturing a conventional flash memory device.

2A to 2G are cross-sectional views of devices for explaining a method of manufacturing a flash memory device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

11, 21: semiconductor substrate 12A, 22A: high-voltage gate oxide film

12B and 22B: low-voltage / cell gate oxide films 13 and 23: first polysilicon layer

24: nitride film 15, 25: trench

26: oxide film for device isolation 160, 260: device isolation film

27: second polysilicon layer 30: photoresist pattern

200: sacrificial nitride film 200P: sacrificial nitride film pattern

230: oxide film

In accordance with another aspect of the present invention, there is provided a method of manufacturing a flash memory device, comprising: providing a semiconductor substrate having a high voltage gate oxide film and a low voltage / cell gate oxide film; Forming a sacrificial nitride film pattern on the first polysilicon layer in the low voltage transistor / cell region; Oxidizing the first polysilicon layer in the high voltage transistor region to a predetermined thickness to form an oxide film; Sequentially removing the oxide layer and the sacrificial nitride layer pattern, thereby performing surface planarization of the first polysilicon layer in the high voltage transistor region and the low voltage transistor / cell region; Forming a plurality of device isolation layers in the semiconductor substrate in each of the high voltage transistor region and the low voltage transistor / cell region; And forming a second polysilicon layer for floating gate on the planarized first polysilicon layer including the device isolation layers.

The oxide film is formed by oxidizing the first polysilicon layer by a step between the high voltage gate oxide film and the low voltage / cell gate oxide film by a wet or dry poly oxidation process.

The sacrificial nitride pattern is removed by a dry or wet etching process. In the case of dry etching, CHF ₃ gas or CHF ₃ / CF ₄ gas is used as the base, and in the case of wet etching, the heated phosphoric acid solution is used.

The device isolation layers are formed by a self-aligned shallow trench isolation process.

Device isolation layers in each of the high voltage transistor region and the low voltage transistor / cell region have similar EFH values.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only this embodiment to make the disclosure of the present invention complete, and to those skilled in the art the scope of the invention It is provided for complete information.

2A to 2G are cross-sectional views of devices for describing a method of manufacturing a flash memory device according to an embodiment of the present invention to which a self-aligned shallow trench isolation scheme is applied.

The flash memory device includes a cell region, a low voltage transistor region, and a high voltage transistor region. For convenience of description, a cell region and a low voltage transistor region having a similar thickness of the gate oxide film are grouped into one region.

Referring to FIG. 2A, a thick high voltage gate oxide film 22A is formed on the semiconductor substrate 21 in the high voltage transistor region HV, and on the semiconductor substrate 21 in the low voltage transistor / cell region LV / CELL. A thin low voltage / cell gate oxide film 22B is formed. A first polysilicon layer 23 for floating gate is formed on the gate oxide films 22A and 22B. The sacrificial nitride film 200 is formed on the first polysilicon layer 23.

In the above, the high voltage gate oxide film 22A is generally formed to a thickness of 300 to 400 kV, and the low voltage / cell gate oxide film 22B is generally formed to a thickness of 50 to 100 kV. And a step is generated between the low voltage transistor / cell region LV / CELL. These steps serve as a source of difficulty in subsequent processes.

The first polysilicon layer 23 is formed to a thickness of 350 ~ 600 mm 3. The sacrificial nitride film 200 is formed by deposition to a thickness of 50 to 500 kPa by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PE-CVD) method.

Referring to FIG. 2B, a photoresist pattern 30 is formed on the sacrificial nitride film 200 in which the high voltage transistor region HV is open and the low voltage transistor / cell region LV / CELL is closed. do. The sacrificial nitride film pattern 200P is formed in the low voltage transistor / cell region LV / CELL by removing the sacrificial nitride film 200 of the high voltage transistor region LV in an etching process using the photoresist pattern 30 as an etching mask.

Referring to FIG. 2C, the photoresist pattern 30 is stripped and wafer cleaned, and a poly oxidation process using the sacrificial nitride film pattern 200P as an anti-oxidation film is performed. An oxide film 230 is formed by oxidizing the first polysilicon layer 23 in the high voltage transistor region HV to a predetermined thickness. In the low voltage transistor / cell region LV / CELL, the first polysilicon layer 23 is not oxidized by the mask layer pattern 200P.

In the above, the oxide film 230 is formed by oxidizing the first polysilicon layer 23 by a step between the high voltage gate oxide film 22A and the low voltage / cell gate oxide film 22B by a wet or dry poly oxidation process.

Referring to FIG. 2D, the oxide film 230 is removed using the sacrificial nitride film pattern 200P as an etch mask layer. Thereafter, the sacrificial nitride film pattern 200P is removed and a wafer cleaning process is performed. As a result, the first polysilicon layer 23 has a surface planarized so that the high voltage transistor region HV and the low voltage transistor / cell region LV / CELL have little step.

In the above, the oxide film 230 may be a dry or wet etching process, but it is preferable to remove the oxide layer 230 by a wet etching process in order to minimize etching damage of the first polysilicon layer 23.

The sacrificial nitride film pattern 200P may be a dry or wet etching process, and when the dry etching process is applied, the CHF ₃ gas or the CHF ₃ / CF ₄ gas is used as the base and is removed using a hot phosphoric acid solution when a wet etching process is applied. Dry etching equipment uses ICP, ECR or RIE types.

Referring to FIG. 2E, the nitride film 24 is formed on the planarized first polysilicon layer 23, and the nitride film 24, the first polysilicon layer 23, the gate oxide film 22A and the SA-STI process are formed. 22B) and the semiconductor substrate 21 are etched to form a plurality of device isolation trenches 25 in the semiconductor substrate 21 in the high voltage transistor region HV and the semiconductor substrate 21 in the low voltage transistor / cell region LV / CELL. To form. The isolation layer 26 is formed over the entire structure including the isolation isolation trench 25 to sufficiently fill the trenches 25. The oxide isolation layer 26 for device isolation is formed using a material such as HDP oxide having excellent gap filing ability and excellent insulation properties.

Referring to FIG. 2F, a chemical mechanical polishing (CMP) process is performed until just before the surface of the planarized first polysilicon layer 23 is exposed to form device isolation layers 260 in the trenches 25. As can be seen in the drawing, the protrusions of the nitride film 24 and the device isolation layers 260 left in the high voltage transistor region HV with respect to the surface of the first polysilicon layer 23 and the low voltage transistor / cell region LV / CELL. The heights of the protrusions of the nitride film 24 and the device isolation layers 260 left in FIG.

Referring to FIG. 2G, the remaining nitride film 24 is stripped and wafer cleaning is performed. At this time, the upper ends of the device isolation layers 260 of the high voltage transistor region HV and the low voltage transistor / cell region LV / CELL are also partially removed. A second polysilicon layer 27 for floating gate is formed on the device isolation layers 260 and the first polysilicon layer 23 in the entire region HV and LV / CELL. Although not shown, gates are formed in each region by performing an etching process using a floating gate mask, a dielectric film forming process, a control layer conductive layer forming process, and an etching process using a control gate mask.

When the flash memory device is manufactured according to the above-described exemplary embodiments, the EFH values of the device isolation layers 260 of the low voltage transistor / cell region LV / CELL are lowered, resulting in each region HV and LV / CELL. The device isolation layers 260 have an EFH value between (−) 50 and 50 kHz, and the difference in EFH values between these regions HV and LV / CELL is almost eliminated.

As described above, the present invention achieves surface planarization of the entire region while improving the EFH difference caused between these regions by the protrusions of the element isolation films of the high voltage transistor region and the low voltage transistor / cell region, thereby ensuring stability of subsequent processes. Not only can this be done, but also the reliability of an element can be improved.

Claims (11)

Providing a semiconductor substrate on which a high voltage gate oxide film and a low voltage / cell gate oxide film are formed; Forming a sacrificial nitride film pattern on the first polysilicon layer in the low voltage transistor / cell region; Oxidizing the first polysilicon layer in the high voltage transistor region to a predetermined thickness to form an oxide film; Sequentially removing the oxide layer and the sacrificial nitride layer pattern, thereby performing surface planarization of the first polysilicon layer in the high voltage transistor region and the low voltage transistor / cell region; Forming a plurality of device isolation layers in the semiconductor substrate in each of the high voltage transistor region and the low voltage transistor / cell region; And Forming a second polysilicon layer for a floating gate on the planarized first polysilicon layer including the device isolation layers. The method of claim 1, The high voltage gate oxide film is formed to a thickness of 300 ~ 400 kHz, the low voltage / cell gate oxide film is formed of a thickness of 50 ~ 100 kHz. The method of claim 1, The first polysilicon layer is a manufacturing method of a flash memory device to form a thickness of 350 ~ 600 Å. The method of claim 1, The sacrificial nitride film pattern is a method of manufacturing a flash memory device to form a thickness of 50 ~ 500Å. The method of claim 1, And the oxide film is formed by oxidizing the first polysilicon layer by a step between the high voltage gate oxide film and the low voltage / cell gate oxide film by a wet or dry poly oxidation process. The method of claim 1, The oxide film is removed by a wet etching method of manufacturing a flash memory device. The method of claim 1, The sacrificial nitride film pattern is a method of manufacturing a flash memory device which is removed by a dry or wet etching process. The method of claim 7, wherein The dry etching process is a flash memory device manufacturing method using the CHF ₃ gas or CHF ₃ / CF ₄ gas as a base to proceed. The method of claim 7, wherein The wet etching process is performed using a heated phosphoric acid solution. The method of claim 1, And forming the device isolation layers by a self-aligned shallow trench isolation process. The method of claim 1, And / or device isolation layers in each of the high voltage transistor region and the low voltage transistor / cell region have similar EFH values.