KR20050002022A - method for fabricating semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to prevent a refresh characteristic from being deteriorated by forming a field stopper only under a field oxide layer in an N-type well. CONSTITUTION: A mask layer(35) is formed on a semiconductor substrate(31) having the first and second conductive wells to define an isolation region and an active region. By using the mask layer, a predetermined depth of the isolation region is etched to form the first trench(37) in the first conductive well, the second trench(38) in the second conductive well, and the third trench(39) whose one side is positioned in the first conductive well and the other side is positioned in the second conductive well. The first ion implantation mask is formed in the second conductive well on the substrate. The first field stopper(45) of the second conductivity type is formed under one part of the first and third trenches. The first ion implantation mask is removed. The second ion implantation mask(47) is formed in the first conductive well on the substrate. The second field stopper(51) of the first conductivity type is formed under the other part of the second and third trenches. The second ion implantation mask is removed. A field oxide layer is formed in the first, second and third trenches. The mask layer and the pad oxide layer are eliminated.

Description

Method for fabricating semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a device is separated using a trench.

In general, in a semiconductor device having a high degree of integration, a field oxide film for isolating devices is used in a shallow oxide isolation shallow trench isolation (STI) technique. The STI technology has a structure in which a trench is formed in a semiconductor substrate and silicon oxide is embedded in the trench by chemical vapor deposition (hereinafter, referred to as CVD). The field oxide film does not generate a bird's beak and thus does not reduce the size of the active region, and a flat surface can be obtained by embedding the oxide film in the trench and etching back.

1A to 1D are process diagrams showing a method for manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1A, a pad oxide layer 13 is formed on a semiconductor substrate 11 doped with N-type impurities such as phosphorous by a first conductivity type, for example, by a thermal oxidation method. Silicon nitride is deposited on the pad oxide layer 13 by CVD to form a mask layer 15. The semiconductor substrate 11 may be an N type well.

In addition, the device isolation region and the active region are sequentially defined so that the semiconductor substrate 11 is exposed to the mask layer 15 and the pad oxide layer 13 by a photolithography method.

Referring to FIG. 1B, the trench 17 is formed by etching the exposed device isolation region of the semiconductor substrate 11 to a predetermined depth using the mask layer 15 as a mask. The trench 17 is formed by anisotropic etching or oblique etching by reactive ion etching (hereinafter referred to as RIE) or plasma etching.

Referring to FIG. 1C, silicon oxide is deposited by CVD to fill the trench 17 on the mask layer 15. Before depositing the silicon oxide, a buffer layer (not shown) and a liner layer (not shown) made of silicon nitride may be formed on the surface exposed by the trench 17 of the semiconductor substrate 11. have. The silicon oxide is etched back by the chemical-mechanical polishing (hereinafter referred to as CMP) method or the RIE method so that the mask layer 15 is exposed to remain only in the trench 17. At this time, the silicon oxide remaining in the trench 17 becomes a field oxide film 19 separating the elements.

Then, the mask layer 15 is removed by a wet method, and the pad oxide layer 13 is chartered to expose the active region of the semiconductor substrate 11. At this time, a portion higher than the surface of the semiconductor substrate 11 of the field oxide film 19 in the trench 17 is also etched to reduce the level difference.

Referring to FIG. 1D, a P-type field stopper 21 is formed below the field oxide film 19. In the above, the field stopper 21 is formed by ion implantation so that the P-type impurity such as boron is located below the field oxide film 19 on the entire surface of the structure described above.

As described above, in the method of manufacturing a semiconductor device of the related art, a field stopper is formed in an active region as well as an isolation region by forming a field oxide film, removing a mask layer, and ion implantation of impurities.

However, the field stopper formed in the active region is unnecessary and degrades the refresh characteristics of the semiconductor devices.

Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device which can prevent the refresh characteristics of devices from being lowered by forming a field stopper only under the field oxide film.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes forming a mask layer defining an isolation region and an active region on a semiconductor substrate having a first conductive well portion and a second conductive well portion; The device isolation region of the semiconductor substrate is etched to a predetermined depth by using a mask layer so that a first trench is formed in the first conductive well, a second trench is formed in the second conductive well, and one side is formed in the first conductive well. And forming third trenches each having a second side in the second conductive well portion, and forming a first ion implantation mask in the second conductive well portion on the semiconductor substrate and forming a first ion implantation mask in the second trench. Forming a first field stopper of a second conductivity type under one side, removing the first ion implantation mask, and performing a second ion implantation on a first conductive well part on the semiconductor substrate; Forming a second trench and forming a second field stopper of a first conductivity type under the other side of the second trench and the third trench, removing the second ion implantation mask, and removing the first, second, and third And forming a field oxide film in the trench and removing the mask layer and the pad oxide layer.

The first field stopper is formed by ion implantation with low energy so that impurities implanted with ions do not pass through the mask layer.

In addition, a method of manufacturing a semiconductor device according to the present invention includes forming a mask layer defining an isolation region and an active region on a semiconductor substrate having a first conductive well portion and a second conductive well portion, and using the mask layer. The device isolation region of the semiconductor substrate is etched to a predetermined depth so that a first trench is formed in the first conductive well, a second trench is formed in the second conductive well, and one side is positioned in the first conductive well. Forming a third trench in which the other side is positioned in the conductive well portion, and forming a first ion implantation mask in the second conductive well portion on the semiconductor substrate, and forming a first ion implantation mask in the lower portion of the first trench and the third trench. Forming a second conductivity type first field stopper; removing the first ion implantation mask; forming a field oxide film in the first, second, and third trenches; And the step of removing the oxide layer, forming a second ion-implantation mask on a first conductive type welbu on the semiconductor substrate and a step of forming a second field, the stopper of the first conductivity type on the second conductive type welbu.

1A to 1D are process drawings showing a method for manufacturing a semiconductor device according to the prior art.

2A to 2E are process drawings showing a method of manufacturing a semiconductor device according to the present invention.

Explanation of symbols on the main parts of the drawings

NA: N type well part PA: P type well part

31 semiconductor substrate 33 pad oxide layer

35 mask layer 37, 38, 39: first, second and third trenches

41: first ion implantation mask 43: N-type well

45: first field stopper 47: second ion implantation mask

49: P-type well 51: second field stopper

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are process drawings showing the manufacturing method of the semiconductor device according to the present invention.

Referring to FIG. 2A, a pad oxide layer 33 is formed on a semiconductor substrate 31 having an N-type well portion NA and a P-type well portion PA by a thermal oxidation method, and CVD is performed on the pad oxide layer 33. Silicon nitride is deposited by the method to form the mask layer 35. The semiconductor substrate 31 may be an N-type or P-type substrate.

In addition, the device isolation region and the active region are sequentially defined so that the semiconductor substrate 31 is exposed to the mask layer 35 and the pad oxide layer 33 by a photolithography method.

Referring to FIG. 2B, the exposed device isolation region of the semiconductor substrate 31 is etched to a predetermined depth by using the mask layer 35 to etch the first, second and third trenches 37, 38, and 39. Form. In the above, the first, second and third trenches 37, 38 and 39 are formed by anisotropic etching or oblique etching by RIE or plasma etching, and the first and second trenches 37 and 38 are respectively N. It is formed in the mold well part NA and P-type well part PA. The third trench 39 is formed in a portion where the N well portion NA and the P type well portion PA contact each other, and one side is formed in the N type well portion NA and the other side is formed in the P type well portion PA. .

Referring to FIG. 2C, after the photoresist is applied on the semiconductor substrate 31, the first ion implantation mask 41 is formed by patterning the photoresist to remove the N-well well NA.

Then, using the first ion implantation mask 41 as a mask, N-type impurities such as phosphorus are ion-implanted into the N-type well part NA with high energy to form the N-type well 43. Then, using the first ion implantation mask 41 as a mask, ion implantation of P-type impurities such as boron into the N-type well 43 with low energy is performed to the first trench 37 and one side of the third trench 39. A P-type first field stopper 45 is formed at a lower portion adjacent to the bottom surface of the P-type. In the above, the N-type well 43 is formed by ion implanting impurities with high energy so as to pass through the mask layer 35 and be formed deeper than the bottom surfaces of the first and third trenches 37 and 39. The stopper 45 ion implants the implanted impurities with low energy so as not to pass through the mask layer 35 so that the stopper 45 is formed at a lower portion adjacent to the bottom surfaces of the first and third trenches 37 and 39.

Referring to FIG. 2D, after removing the first ion implantation mask 41, the photoresist is applied on the semiconductor substrate 31, and then patterned to remove the P-well well PA from the second ion implantation mask. Form 47.

Then, using the second ion implantation mask 47 as a mask, P-type impurities such as boron are ion-implanted into the P-type well part PA with high energy to form the P-type well 49. Then, using the second ion implantation mask 47 as a mask, ion implantation of N-type impurities such as phosphorus into the P-type well 49 at low energy is carried out to remove the second trench 38 and the third trench 39. An N-type second field stopper 51 is formed at a lower portion adjacent to the other bottom surface.

The P-type well 49 is formed by ion implanting impurities with high energy so as to pass through the mask layer 35 and be formed deeper than the bottom surfaces of the second and third trenches 38 and 39. The stopper 51 implants impurities to be implanted with low energy so as not to pass through the mask layer 35 so as to be formed at a lower portion adjacent to the bottom surfaces of the second and third trenches 38 and 39.

Since the first and second field stoppers 45 and 51 are formed only on the lower portions of the first, second and third trenches 37, 38, and 39, the resistance of the device isolation region can be accurately adjusted and refreshed. Properties can be improved.

Referring to FIG. 2E, the second ion implantation mask 47 is removed. Then, silicon oxide or the like is filled in the first, second and third trenches 37, 38 and 39 to form a field oxide film 53, and the mask layer 35 and the pad oxide layer 33 are removed.

The field oxide film 53 may include a buffer layer (not shown) and silicon nitride deposited with thermal oxide on the surfaces of the first, second and third trenches 37, 38, and 39 (not shown). And an insulating material such as silicon oxide is deposited on the mask layer 35 to fill the first, second and third trenches 37, 38 and 39, and then etched back.

According to another embodiment of the present invention, after forming the field oxide film, an N-type impurity may be ion-implanted into the P-well to form a second field stopper.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Therefore, the present invention is advantageous in that the field stopper is formed only at the bottom of the field oxide film in at least the N-type well, thereby preventing the refresh characteristics of the devices from being lowered.

Claims (3)

Forming a mask layer defining a device isolation region and an active region on a semiconductor substrate having a first conductive well portion and a second conductive well portion; By using the mask layer, the device isolation region of the semiconductor substrate is etched to a predetermined depth so that a first trench is formed in the first conductive well, a second trench is formed in the second conductive well, and one side is formed in the first conductive well. Forming third trenches, the third trenches being positioned at the other side of the second conductive well part; Forming a first ion implantation mask in a second conductive well portion on the semiconductor substrate and forming a first field stopper of a second conductive type under one side of the first trench and the third trench; The first ion implantation mask is removed, and a second ion implantation mask is formed in the first conductivity type well on the semiconductor substrate, and a second field stopper of the first conductivity type is formed under the other side of the second trench and the third trench. Forming process, Removing the second ion implantation mask, forming a field oxide film in the first, second and third trenches, and removing the mask layer and the pad oxide layer. The method according to claim 1, And forming the first field stopper by ion implantation with low energy so that impurities implanted with the ion do not pass through the mask layer. Forming a mask layer defining a device isolation region and an active region on a semiconductor substrate having a first conductive well portion and a second conductive well portion; By using the mask layer, the device isolation region of the semiconductor substrate is etched to a predetermined depth so that a first trench is formed in the first conductive well, a second trench is formed in the second conductive well, and one side is formed in the first conductive well. Forming third trenches, the third trenches being positioned at the other side of the second conductive well part; Forming a first ion implantation mask in a second conductive well portion on the semiconductor substrate and forming a first field stopper of a second conductive type under one side of the first trench and the third trench; Removing the first ion implantation mask, forming a field oxide film in the first, second and third trenches, and removing the mask layer and the pad oxide layer; And forming a second ion implantation mask in the first conductive well portion on the semiconductor substrate and forming a second field stopper of the first conductive type in the second conductive well portion.