KR20040110279A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR20040110279A KR20040110279A KR1020030039505A KR20030039505A KR20040110279A KR 20040110279 A KR20040110279 A KR 20040110279A KR 1020030039505 A KR1020030039505 A KR 1020030039505A KR 20030039505 A KR20030039505 A KR 20030039505A KR 20040110279 A KR20040110279 A KR 20040110279A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 49
- 230000007547 defect Effects 0.000 claims abstract description 47
- 238000004544 sputter deposition Methods 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 23
- 238000011065 in-situ storage Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 46
- 238000000059 patterning Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Spectroscopy & Molecular Physics (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Formation Of Insulating Films (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, TEOS 산화막을 이용한 절연막 형성시의 볼록이성 결함 발생을 억제하기 위한 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for suppressing convex heterogeneity defects during formation of an insulating film using a TEOS oxide film.
현재 대부분의 반도체 제조 공정에서는 금속배선들 사이의 절연 물질로서 TEOS(Tetra Ethyl Ortho Silicate) 산화막을 많이 사용하고 있다. 이는 TEOS 산화막이 그 형성이 용이하면서도 소자 제조시에 요구되는 절연 특성을 확보할 수 있기 때문이다.Currently, most semiconductor manufacturing processes use TEOS (Tetra Ethyl Ortho Silicate) oxide as an insulating material between metal wires. This is because the TEOS oxide film can be easily formed and ensure the insulating characteristics required for device fabrication.
그런데, 상기 TEOS 산화막은 일반적인 CVD 공정에 따라 증착할 경우, 그 표면에 미세하게 볼록이성 결함(defect)이 생성되는 성질을 가지고 있다. 특히, 이러한 결함은 반도체 소자가 고집적화되고 미세 패턴화되면서 그 자체로도 문제가 되고 있지만, 후속에서 이러한 TEOS 산화막 상에 CVD 공정에 따라 산화막(이하, CVD 산화막이라 칭함)이 증착될 경우, 상기 TEOS 산화막의 미세 볼록이성 결함이 증폭되어 거대 볼록이성 결함을 유발하게 되며, 이러한 거대 볼록이성 결함은 후속하는 패터닝 공정에서 브릿지 등의 패터닝 불량을 야기함으로써 소자 페일을 초래하게 된다.However, when the TEOS oxide film is deposited by a general CVD process, fine convexity defects are generated on the surface thereof. In particular, such a defect is a problem in itself as the semiconductor device is highly integrated and finely patterned, but when the oxide film (hereinafter referred to as CVD oxide film) is deposited on the TEOS oxide film in accordance with the CVD process in the following, the TEOS The fine convexity defects of the oxide film are amplified to cause the large convexity defects, and the large convexity defects cause device failure by causing a patterning defect such as a bridge in a subsequent patterning process.
도 1은 미세한 볼록이성 결함이 발생된 TEOS 산화막 및 이에 기인하여 후속에서 커다란 볼록이성 결함이 발생된 CVD 산화막을 보여주는 사진이고, 도 2는 이러한 볼록이성 결함에 의해 후속 공정에서 패터닝 불량이 발생된 상태를 보여주는 사진이며, 도 1에서, 도면부호 1은 TEOS 산화막, 2는 CVD 산화막, A는 TEOS 산화막에서의 미세한 볼록이성 결함, B는 CVD 산화막에서의 커다란 볼록이성 결함, 그리고, C는 패터닝 불량 발생 지역을 각각 나타낸다.FIG. 1 is a photograph showing a TEOS oxide film in which a fine convex defect is generated and a CVD oxide film in which a large convex defect is subsequently generated, and FIG. 2 is a state in which a patterning defect is generated in a subsequent process by such a convex defect. In Fig. 1, reference numeral 1 denotes a TEOS oxide film, 2 is a CVD oxide film, A is a fine convex defect in the TEOS oxide film, B is a large convex defect in the CVD oxide film, and C is a patterning defect. Represent each area.
결국, 금속배선들 사이의 절연 물질로서 TEOS 산화막을 사용하기 위해서는 상기 TEOS 산화막 증착 후 그 표면에 발생된 미세 볼록이성 결함의 제거가 필수적이다.As a result, in order to use the TEOS oxide film as the insulating material between the metal wires, it is necessary to remove the fine convexity defects generated on the surface after the TEOS oxide film is deposited.
한편, 상기한 TEOS 산화막에서의 미세 볼록이성 결함 발생을 방지하기 위해 다양한 증착 공정들이 개발되고 있지만, 현재 볼록이성 결함 발생의 방지에 커다란 효과가 없는 실정이다.On the other hand, various deposition processes have been developed to prevent the occurrence of fine convex defects in the TEOS oxide film, but there is currently no great effect on the prevention of convex defects.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, TEOS 산화막을 이용한 절연막 형성시의 볼록이성 결함 발생을 억제할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of suppressing the occurrence of convexity defects during formation of an insulating film using a TEOS oxide film.
또한, 본 발명은 TEOS 산화막에서의 볼록이성 결함을 억제함으로써 소자 페일 발생을 방지할 수 있는 반도체 소자의 제조방법을 제공함에 그 다른 목적이 있다.Another object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing device failing by suppressing convexity defects in a TEOS oxide film.
도 1 및 도 2는 종래의 문제점을 설명하기 위한 도면.1 and 2 are views for explaining a conventional problem.
도 3a 내지 도 3c는 본 발명에 따른 볼록이성 결함 제거방법을 설명하기 위한 모식도.Figure 3a to 3c is a schematic diagram for explaining a convex defect removal method according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
31 : 반도체 기판 32 : TEOS 산화막31 semiconductor substrate 32 TEOS oxide film
33 : 볼록이성 결함 34 : 이온33: convexity defect 34: ion
상기와 같은 목적을 달성하기 위하여, 본 발명은, 반도체 기판 상에 절연막으로서 TEOS 산화막을 증착하는 반도체 소자의 제조방법에 있어서, 상기 TEOS 산화막을 CVD 공정에 따라 증착한 후, 동일 CVD 챔버 내에서 인-시튜(in-situ)로 스퍼터링을 행하여 상기 TEOS 산화막 표면에 발생된 볼록이성 결함을 제거하는 것을 특징으로 하는 반도체 소자의 제조방법을 제공한다.In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device in which a TEOS oxide film is deposited as an insulating film on a semiconductor substrate, wherein the TEOS oxide film is deposited by a CVD process, and then phosphorus is deposited in the same CVD chamber. The present invention provides a method for manufacturing a semiconductor device, characterized in that sputtering is performed in-situ to remove convexity defects generated on the surface of said TEOS oxide film.
여기서, 상기 스퍼터링은 스퍼터링 가스로서 O2, N2 또는 Ar을 사용하며, 또한, TEOS 산화막 표면의 50∼1000Å의 두께가 식각되도록 수행하고, 그리고, 스퍼터링 효율이 개선되도록 기판쪽에 5∼20kW의 바이어스를 걸어준 상태로 수행한다.Here, the sputtering uses O2, N2 or Ar as the sputtering gas, and performs 50 to 1000 kW thickness of the TEOS oxide film to be etched, and applies a bias of 5 to 20 kW on the substrate side to improve the sputtering efficiency. Run in a quasi state.
본 발명에 따르면, TEOS 산화막을 증착한 후에 인-시튜(in-situ)로 스퍼터링을 행하여 상기 TEOS 산화막 표면의 미세 볼록이성 결함을 제거함으로써 상기 미세 볼록이성 결함 발생 지역에서의 거대 볼록이성 결함의 유발을 방지할 수 있으며, 이에 따라, 패턴 결함이 발생되는 등의 소자 제조수율 저하를 방지할 수 있다.According to the present invention, after depositing a TEOS oxide film, sputtering in-situ is performed to remove microconvex defects on the surface of the TEOS oxide film, thereby causing large convex defects in the region where the microconvex defects occur. In this way, it is possible to prevent a decrease in device manufacturing yield such that pattern defects occur.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
일반적으로 TEOS 산화막은 TEOS와 O2 가스를 사용하여 증착하며, CVD 챔버 내로 상기 TEOS와 O2 가스가 유입된 후, 일부가 플라즈마 내에서 이온화되어 반응하여 기판 상에 TEOS 박막으로 증착된다. 그런데, TEOS 산화막 내부에는 C 또는 H 등의 여러가지 원소들이 함유되는데, 이러한 원소들의 부산물로 인해 최종 증착된 TEOS 산화막의 표면에는 미세한 볼록이성 결함이 형성된다.In general, the TEOS oxide film is deposited using TEOS and O2 gas. After the TEOS and O2 gas are introduced into the CVD chamber, some of the TEOS oxide is reacted by being ionized in the plasma and deposited on the substrate as a TEOS thin film. However, various elements such as C or H are contained in the TEOS oxide film, and by-products of these elements form fine convex defects on the surface of the TEOS oxide film that is finally deposited.
따라서, 본 발명은 이러한 미세 볼록이성 결함을 제거하기 위해, 상기 TEOS 산화막의 증착 후에 인-시튜(in-situ)로 스퍼터링을 추가하여 상기 미세 볼록이성 결하이 제거되도록 하며, 이를 통해, 후속 공정에서의 패터닝 불량의 발생이 방지되도록 한다.Accordingly, the present invention adds sputtering in-situ after deposition of the TEOS oxide film to remove such microconvex defects so that the microconvex defects are removed, thereby, in a subsequent process. The occurrence of the patterning failure of the to be prevented.
자세하게, 도 3a 내지 도 3c는 본 발명에 따른 TEOS 산화막 표면에서의 볼록이성 결함 제거방법을 설명하기 위한 모식도로서, 이를 설명하면 다음과 같다.In detail, Figures 3a to 3c is a schematic diagram for explaining a method of removing convex defects on the surface of the TEOS oxide film according to the present invention.
먼저, 도 3a에 도시된 바와 같이, 소정의 하지층이 형성된 반도체 기판(31) 상에 CVD공정, 바람직하게 PECVD(Plasma Enhanced CVD) 공정에 따라 1000∼25000Å 두께로 TEOS 산화막(32)을 증착한다. 이때, 상기 TEOS 산화막(32)의 표면에는 막 특성에 따라 미세 볼록이성 결함(33)이 발생된다.First, as shown in FIG. 3A, a TEOS oxide film 32 is deposited to a thickness of 1000 to 25000 에 by a CVD process, preferably, a PECVD (Plasma Enhanced CVD) process, on a semiconductor substrate 31 on which a predetermined base layer is formed. . At this time, the fine convexity defect 33 is generated on the surface of the TEOS oxide film 32 according to the film characteristics.
그 다음, 도 3b에 도시된 바와 같이, 표면에 볼록이성 결함(33)이 발생된 TEOS 산화막 표면에 대해 인-시튜로 스퍼터링을 수행한다. 이때, 스퍼터링 가스로서는 O2 가스를 사용하여 수행하며, 만약 챔버 내에 어느 정도의 질량을 가지는 다른 가스, 예컨데, N2 또는 Ar 가스가 있다면 이러한 가스를 스퍼터링 가스로서 사용하는 것도 가능하다. 미설명된 도면부호 34는 이온을 나타낸다.Then, as shown in FIG. 3B, sputtering is performed in-situ on the surface of the TEOS oxide film on which the convexity defect 33 is generated. At this time, the sputtering gas is carried out using an O 2 gas, and if there is another gas having a certain mass in the chamber, for example, N 2 or Ar gas, it is also possible to use such a gas as the sputtering gas. Unexplained reference numeral 34 denotes ions.
이 결과, 도 3c에 도시된 바와 같이, TEOS 산화막(32)의 표면 일부 두께, 바람직하게 50∼1000Å의 두께가 식각되며, 이에 따라, 볼록이성 결함 또한 제거되고, 상기 TEOS 산화막(32)은 볼록이성 결함이 없는 평탄한 표면을 갖게 된다.As a result, as shown in FIG. 3C, a portion of the surface of the TEOS oxide film 32 is preferably etched, preferably 50 to 1000 microns, so that convexity defects are also eliminated, and the TEOS oxide film 32 is convex. It will have a flat surface free of heterogeneous defects.
결국, 본 발명은 TEOS 산화막의 증착 후에 인-시튜로 스퍼터링을 행함으로써 볼록이성 결함을 효과적으로 제거할 수 있으며, 이에 따라, 후속에서 상기 TEOS 산화막 상에 다른 CVD 산화막을 증착하더라도 하층에 기인한 볼록이성 결함 발생을 방지할 수 있게 되고, 그래서, 후속 패터닝 공정에서 브릿지 발생 등의 패턴 불량으로 인한 페일 발생을 방지할 수 있게 된다.As a result, the present invention can effectively eliminate convexity defects by sputtering in-situ after deposition of the TEOS oxide film, thus convexity due to the lower layer even if another CVD oxide film is subsequently deposited on the TEOS oxide film. It is possible to prevent the occurrence of a defect, and thus to prevent the occurrence of a failure due to a pattern defect such as a bridge generation in a subsequent patterning process.
한편, 전술한 본 발명의 방법은 TEOS 산화막의 증착 후, 동일 장비 내에서 인-시튜로 스퍼터링을 행하는 것을 통해 볼록이성 결함을 제거하므로, 상기 볼록이성 결함을 제거하기 위한 별도의 공정 및 장비의 추가가 필요치 않으며, 이에 따라, 제조 단가의 증가를 방지하면서 TAT(Turn Around Time)의 증가 또한 방지할 수 있다.Meanwhile, the aforementioned method of the present invention removes convexity defects by sputtering in-situ within the same equipment after deposition of the TEOS oxide film, thereby adding a separate process and equipment for removing the convexity defects. Is not required, and thus, an increase in TAT (Turn Around Time) can be prevented while preventing an increase in manufacturing cost.
또한, 본 발명은 스퍼터링을 행함에 있어서 기판쪽에 약간의 "+" 바이어스, 예컨데, 5∼20kW의 바이어스를 걸어주어 이온화된 스퍼터링용 가스가 기판쪽으로 가속되면서 TEOS 박막에 충돌이 되도록 함으로써 스퍼터링 효율이 개선되도록 하며, 이를 통해, 보다 짧은 시간에 결함 제거가 이루어지도록 한다.In addition, the present invention improves the sputtering efficiency by applying a slight "+" bias to the substrate side, for example, a 5-20 kW bias in sputtering so that the ionized sputtering gas is accelerated toward the substrate and collides with the TEOS thin film. This allows defects to be eliminated in a shorter time.
이상에서와 같이, 본 발명은 절연막으로서 TEOS 산화막을 증착한 후 인-시튜로 스퍼터링을 행함으로써 상기 TEOS 산화막 표면의 미세 볼록이성 결함을 효과적으로 제거할 수 있으며, 이에 따라, 볼록이성 결함에 기인하는 패턴 결함 발생을 방지할 수 있어 소자 특성 및 제조수율을 향상시킬 수 있다.As described above, the present invention can effectively remove the fine convexity defects on the surface of the TEOS oxide film by sputtering in-situ after depositing the TEOS oxide film as the insulating film, thus, the pattern resulting from the convexity defects Defects can be prevented to improve device characteristics and manufacturing yield.
기타, 본 발명은 그 요지가 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.
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