KR20040108015A - Method for forming gate line of semiconductor device - Google Patents

Abstract

PURPOSE: A method of forming a gate line of a semiconductor device is provided to prevent the short between a contact plug and the gate line due to the tail of the gate line by performing a gate line forming process using a triple-structure composed of a silicon nitride layer, a silicon oxide layer and an anti-reflective coating as a hard mask layer. CONSTITUTION: A gate oxide layer(22), a gate line layer(25) composed of a polysilicon layer(23) and a silicide layer(24), a hard mask layer(29) and a photoresist pattern are sequentially formed on a silicon substrate(21). At this time, the hard mask layer is composed of a silicon nitride layer(26), a silicon oxide layer(27) and an anti-reflective coating(28). The hard mask layer is etched by using the photoresist pattern as an etching mask. The photoresist pattern is removed therefrom. A gate line is formed by etching selectively the gate line layer using the patterned hard mask layer as an etching mask.

Description

TECHNICAL FOR FORMING GATE LINE OF SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a gate wiring of a semiconductor device, and more particularly, to a method of forming a gate wiring capable of preventing a short circuit between a contact plug and a gate wiring caused by a shape residue remaining after etching of a polysilicon film. It is about.

As the integration of semiconductor devices increases, the gate line width is reduced due to the decrease in cell size. Accordingly, various techniques for gate formation capable of implementing low resistance at a fine line width have been researched and developed.

Here, a polysilicon film is generally used as the gate material. The polysilicon is not only easy to handle, but also has a desired conductivity type according to the type and doping concentration of the dopant, and at the same time has a specific level of resistivity. As various uses.

In forming such a gate wiring, conventionally, the mask oxide film is etched and the gate wiring material film is etched using dry etching in a state where a mask oxide film is formed on the gate wiring material film, thereby forming a desired material. The gate wiring is formed.

A method of forming a gate wiring of a conventional semiconductor device will be briefly described with reference to FIGS. 1A to 1D as follows.

In a method of forming a gate wiring of a conventional semiconductor device, as shown in FIG. 1A, first, a gate oxide film 2 is formed on a silicon substrate 1, and a polysilicon film 3 is formed on the gate oxide film 2. ) And a silicide film 4 are formed. Next, a hard mask film 8 formed of a stack of silicon nitride film 6 and low reflection film 7 is formed on the gate wiring film 5. A photosensitive film pattern 9 defining a gate wiring forming region is formed on the hard mask film 8.

Next, as shown in FIG. 1B, the hard mask layer 8 is etched using the photoresist pattern 9 as an etch barrier. At this time, Cl2 gas is used to etch the hard mask film 8. Then, the photoresist pattern 9 is removed.

Then, as illustrated in FIG. 1C, the silicide layer 4 is etched using the etched hard mask layer 8 as an etch barrier. In this case, a plasma containing fluorine is used to etch the silicide layer 4. At this time, plasma containing SF6 and plasma containing NF3 are used as the plasma containing fluorine. After etching the silicide layer 4, the low reflection layer 7 is removed.

Subsequently, as shown in FIG. 1D, the polysilicon film 3 is etched. When etching the polysilicon film 3, a high density plasma film etching apparatus is used. In addition, a plasma in which oxygen is added to the HBr gas is usually used in the high density plasma etching apparatus. Subsequently, the polysilicon film 3 is etched until the gate oxide film 2, which is an underlayer film of the polysilicon film 3, is exposed to form a gate wiring.

However, in the gate wiring forming method of the conventional semiconductor device as described above, when the gate oxide film, which is the underlayer film of the polysilicon film, is exposed during the etching of the polysilicon film, the HBr gas included in the plasma used for etching the polysilicon film and The gate oxide film reacts to generate oxygen as a reaction by-product.

At this time, the chemical reaction formula (I) is as follows.

HBr + SiO2-> SiBrx + HOy + Oz ------- (Ⅰ)

The oxygen contained in the plasma is then added to the oxygen produced by the reaction by-products, thereby increasing the oxygen concentration in the entire reaction. As a result, the etch stop occurs to the polysilicon film, so that the etching becomes uneven, so that a residue remains in the shape of the polysilicon film even after the over-etching of the polysilicon film is performed. As a result, a problem occurs that causes a short circuit between the contact plug and the gate wiring formed in a subsequent process.

Accordingly, the present invention has been made to solve the above problems, to prevent the etch stop phenomenon occurring during the polysilicon film etching, thereby preventing the failure of the semiconductor device and shorten the development period of the semiconductor device It is an object of the present invention to provide a method for forming a gate wiring.

1A to 1D are cross-sectional views illustrating processes for forming gate wirings of a semiconductor device according to the related art.

2A to 2D are cross-sectional views illustrating processes for forming gate wirings of a semiconductor device in accordance with an embodiment of the present invention.

Explanation of symbols on main parts of drawing

21 silicon substrate 22 gate oxide film

23 polysilicon film 24 silicide film

25 gate wiring film 26 silicon nitride film

27 silicon oxide film 28 low reflection film

29: hard mask film 30: photosensitive film pattern

A method for forming a gate wiring of a semiconductor device of the present invention for achieving the above object comprises the steps of: forming a gate oxide film on a silicon substrate; Forming a gate wiring film formed of a stack of a polysilicon film and a silicide film on the gate oxide film; Forming a hard mask film including a stack of a silicon nitride film, a silicon oxide film, and a low reflection film on the gate wiring film; Forming a photoresist pattern defining a gate wiring formation region on the hard mask layer; Etching the hard mask layer using the photoresist pattern as an etch barrier; Removing the photoresist pattern; Etching the silicide layer by using the hard mask layer as an etch barrier to remove the low reflection layer and expose the silicon oxide layer; And etching the polysilicon layer to form a gate wiring.

According to the present invention, the shape of the polysilicon film due to the non-uniformity of the etching reaction (Tail) is prevented. As a result, a short circuit between the contact plug and the gate wiring in a subsequent process can be prevented, thereby improving the yield and characteristics of the device.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2D are cross-sectional views of respective processes for explaining a method of forming gate wirings of a semiconductor device according to an exemplary embodiment of the present invention.

In the method for forming a gate wiring of a semiconductor device according to an embodiment of the present invention, as shown in FIG. 2A, first, a gate oxide film 22 is formed on a silicon substrate 21, and then on the gate oxide film 22. A gate wiring film 25 formed of a stack of polysilicon film 23 and silicide film 24 is formed. Then, a hard mask film 29 is formed on the gate wiring film 25 by laminating a silicon nitride film 26, a silicon oxide film 27, and a low reflection film 28. A photoresist pattern 30 is formed on the hard mask layer 29 to define a gate wiring formation region.

Next, as shown in FIG. 2B, the hard mask layer 29 is etched using the photoresist pattern 30 as an etch barrier. At this time, Cl2 gas is used to etch the hard mask layer 29. Then, the photosensitive film pattern 30 is removed.

Then, as illustrated in FIG. 2C, the silicide layer 24 is etched using the hard mask layer 29 as an etch barrier. Here, a plasma containing fluorine is used to etch the silicide layer 24. At this time, plasma containing SF6 and plasma containing NF3 are used as the plasma containing fluorine. After etching the silicide layer 24, the low reflection layer 28 is removed, and the silicon oxide layer 27, which is a lower layer layer of the low reflection layer 28, is exposed.

Subsequently, as shown in FIG. 2D, the polysilicon film 23 is etched. When the polysilicon layer 23 is etched, a high density plasma etching apparatus such as Decoupled Plasma Source (DPS), Transformer Coupled Plasma (TCP), Inductively Coupled Plasma (ICP), or Electron Cyclotron Resonance (ECR) is used. In addition, a plasma in which oxygen is added to the HBr gas is used inside the high density plasma etching apparatus. At this time, the HBr gas contained in the plasma is used for etching the polysilicon film and oxygen is used to increase the etching selectivity with the gate oxide film. Here, the flow rate of the oxygen contained in the plasma is 1% to 10% or less of the HBr gas flow rate. At this time, when the oxygen ratio decreases, the amount of sidewall polymer decreases, so that an undercut shape of the polysilicon is generated at the bottom of the silicide layer, and when the oxygen ratio increases, the etch stop occurs. Therefore, it is very important to control the oxygen ratio included in the plasma when the polysilicon layer 23 is etched. The process conditions inside the high density plasma etching apparatus are pressure 10-100 mTorr, source power 500-1500 W, bias power 30-150 W, and HBr gas flow 50-150 sccm. , Flow rate of O2 is 1-5sccm. Subsequently, the polysilicon layer 23 is etched until the gate oxide layer 22, which is a lower layer layer of the polysilicon layer 23, is exposed to form a gate wiring.

In the present invention, the silicon oxide film 27 is exposed to the entire upper structure when the polysilicon film 23 is etched. As a result, when the polysilicon layer 23 is etched, the gate oxide layer 22, which is a lower layer of the polysilicon layer 23, is exposed, and the gate oxide layer 22 reacts with the HBr gas included in the plasma to surplus it. Even if oxygen is generated, the increase in the ratio of oxygen in the entire etching gas is minimal. As a result, the etch stop is prevented so that there is little change in the etching reaction.

As described above, according to the present invention, a triple structure of a silicon nitride film, a silicon oxide film, and a low reflection film is applied as a hard mask film, whereby the reaction of the gate oxide film with the HBr gas included in the plasma used for etching the polysilicon film. Even if oxygen is generated, the increase of the oxygen ratio in the entire etching gas is minimal. Thus, the etch stop phenomenon of the polysilicon film is prevented.

Accordingly, the present invention prevents a shape tail of the polysilicon film due to non-uniformity of the etching reaction, thereby preventing short circuit between the contact plug and the gate wiring in a subsequent process, thereby improving the yield and characteristics of the device. .

In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (1)

Forming a gate oxide film on the silicon substrate; Forming a gate wiring film formed of a stack of a polysilicon film and a silicide film on the gate oxide film; Forming a hard mask film including a stack of a silicon nitride film, a silicon oxide film, and a low reflection film on the gate wiring film; Forming a photoresist pattern defining a gate wiring formation region on the hard mask layer; Etching the hard mask layer using the photoresist pattern as an etch barrier; Removing the photoresist pattern; Etching the silicide layer by using the hard mask layer as an etch barrier to remove the low reflection layer and expose the silicon oxide layer; And And forming a gate wiring by etching the polysilicon layer.