KR20040107135A - Method for forming Cu wiring of semiconductor device - Google Patents

Method for forming Cu wiring of semiconductor device Download PDF

Info

Publication number
KR20040107135A
KR20040107135A KR1020030038015A KR20030038015A KR20040107135A KR 20040107135 A KR20040107135 A KR 20040107135A KR 1020030038015 A KR1020030038015 A KR 1020030038015A KR 20030038015 A KR20030038015 A KR 20030038015A KR 20040107135 A KR20040107135 A KR 20040107135A
Authority
KR
South Korea
Prior art keywords
copper
insulating layer
film
solution
diluted
Prior art date
Application number
KR1020030038015A
Other languages
Korean (ko)
Inventor
조일현
Original Assignee
매그나칩 반도체 유한회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 매그나칩 반도체 유한회사 filed Critical 매그나칩 반도체 유한회사
Priority to KR1020030038015A priority Critical patent/KR20040107135A/en
Publication of KR20040107135A publication Critical patent/KR20040107135A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

PURPOSE: A method of forming a copper line of a semiconductor device is provided to remove reliably residues of copper from an upper portion of an insulating layer by dipping a corresponding substrate into a diluted HF solution after a CMP(Chemical Mechanical Polishing) process of a copper film. CONSTITUTION: A first insulating layer(22), an etch stop layer(23) and a second insulating layer(24) are sequentially formed on a semiconductor substrate(21) with predetermined conductive patterns. A trench(25) with a contact hole is formed in the resultant structure by using etching, wherein the contact hole is under the trench. A copper film(26) for filling the contact hole and trench is deposited thereon. A CMP process is performed on the copper film until the second insulating layer is exposed to the outside. The resultant structure is dipped into a diluted HF solution to remove copper residues(27) from the second insulating layer.

Description

반도체 소자의 구리배선 형성방법{Method for forming Cu wiring of semiconductor device}Method for forming Cu wiring of semiconductor device

본 발명은 반도체 소자의 구리배선 형성방법에 관한 것으로, 보다 상세하게는, 구리막에 대한 화학적기계연마 후의 구리 잔류물(Cu residue)을 제거하기 위한 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming copper wiring of semiconductor devices, and more particularly, to a method for removing copper residues after chemical mechanical polishing on copper films.

주지된 바와 같이, 화학적기계연마(Chemical Mechanical Polishing : 이하, CMP) 공정은 슬러리(slurry)에 의한 화학 반응과 연마 패드(polishing pad)에 의한 기계적 가공이 동시에 수행되는 평탄화 공정으로서, 평탄화를 위해 기존에 이용되어져 왔던 리플로우(reflow) 공정 또는 에치-백(etch-back) 공정 등과 비교해서 글로벌(global) 평탄화를 얻을 수 있고, 아울러, 저온에서 수행될 수 있다는 잇점이 있다.As is well known, the Chemical Mechanical Polishing (CMP) process is a planarization process in which a chemical reaction by a slurry and a mechanical processing by a polishing pad are simultaneously performed. Compared with the reflow process or the etch-back process, which has been used in the present invention, global flattening can be obtained and, in addition, it can be performed at low temperature.

이러한 CMP 공정은 평탄화 공정의 일환으로 제안된 것이지만, 최근에 들어서는 콘택플러그 형성을 위한 폴리실리콘막의 식각 및 금속배선 형성을 위한 금속막의 식각 공정에 이용되고 있으며, 그 이용 분야가 점차 확대되고 있는 추세이다.The CMP process is proposed as part of the planarization process, but recently, the CMP process has been used for etching a polysilicon film for forming a contact plug and an etching process for a metal film for forming a metal wiring. .

한편, 상기 CMP 공정을 이용하여 구리배선을 형성할 경우, 도 1에 도시된 바와 같이, 구리막의 CMP 후에는 제2절연막(4) 상에 구리 잔류물(Cu residue : 7)이 남을 수 있다. 따라서, 구리배선(6)을 형성함에 있어서 구리막의 CMP 후에 가장 신경을 써야 하는 사항 중의 하나는 구리 잔류물(7)이라 할 수 있다.On the other hand, when the copper wiring is formed using the CMP process, as shown in FIG. 1, after the CMP of the copper film, a copper residue (Cu residue) 7 may remain on the second insulating film 4. Therefore, one of the items to be most concerned with after the CMP of the copper film in forming the copper wiring 6 may be referred to as the copper residue 7.

이것은 구리 잔류물(7)이 소자에 치명적인 이물질로 작용하기 때문이다. 예컨데, 상기 구리 잔류물(7)은 이웃하는 구리배선들(6)간의 쇼트(short)를 유발함으로써 제조수율 저하를 초래할 수 있다.This is because the copper residue 7 acts as a lethal foreign material to the device. For example, the copper residue 7 may lead to a decrease in manufacturing yield by causing a short between neighboring copper wirings 6.

이에 따라, 종래에는 구리막에 대한 CMP 후에 추가 CMP를 수행하여 절연막 상에 남겨진 구리 잔류물을 제거하고 있다.Accordingly, conventionally, after the CMP for the copper film, additional CMP is performed to remove the copper residues left on the insulating film.

도 1에서, 미설명된 도면부호 1은 반도체 기판, 2는 제1절연막, 그리고, 3은 식각정지막을 각각 나타낸다.In FIG. 1, reference numeral 1 denotes a semiconductor substrate, 2 denotes a first insulating layer, and 3 denotes an etch stop layer.

그러나, 추가 CMP를 이용하는 방법은 구리 잔류물을 신뢰성있게 제거할 수는 있지만, 공정 추가에 따른 제조비용 증가를 유발하게 되고, 특히, 현재로서는 미세하게 남은 구리 잔류물의 관찰이 어려운 것과 관련해서 추가 CMP의 수행 여부를 판단하기 어려우므로, 비용 증가에 대한 부담을 가질 수 밖에 없다.However, methods using additional CMP can reliably remove copper residues, but lead to increased manufacturing costs due to the addition of the process, in particular with respect to the difficulty of observing finely left copper residues at present. Since it is difficult to determine whether to perform, there is no choice but to bear the burden of increasing costs.

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, CMP를 추가 수행함이 없이 구리 잔류물을 신뢰성있게 제거할 수 있는 반도체 소자의 구리배선 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a copper wiring of a semiconductor device capable of reliably removing copper residues without additionally performing CMP.

도 1은 종래 기술에 따라 형성된 구리배선에서의 문제점을 설명하기 위한 단면도.1 is a cross-sectional view illustrating a problem in a copper wiring formed according to the prior art.

도 2a 내지 도 2d는 본 발명의 실시예에 따른 구리배선 형성방법을 설명하기 위한 공정별 단면도.Figure 2a to 2d is a cross-sectional view for each process for explaining a copper wiring forming method according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

21 : 반도체 기판 22 : 제1절연막21 semiconductor substrate 22 first insulating film

23 : 식각정지막 24 : 제2절연막23: etching stop film 24: second insulating film

25 : 트렌치 26,26a : 구리배선25: trench 26,26a: copper wiring

27 : 구리 잔류물27: copper residue

상기와 같은 목적을 달성하기 위하여, 본 발명은, 소정의 도전 패턴들이 형성된 반도체 기판 상에 제1절연막과 식각정지막 및 제2절연막을 차례로 형성하는 단계; 상기 제2절연막과 식각정지막 및 제1절연막을 식각하여 하부에 콘택홀을 구비한 트렌치를 형성하는 단계; 상기 콘택홀 및 트렌치를 매립하도록 구리막을 증착하는 단계; 상기 제2절연막이 노출될 때까지 구리막을 CMP하는 단계; 및 상기 기판 결과물을 희석된 HF 용액 내에 침지시켜 제2절연막 상의 구리 잔류물을 제거하는 단계를 포함하는 반도체 소자의 구리배선 형성방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of forming a first insulating film, an etch stop film and a second insulating film on a semiconductor substrate formed with a predetermined conductive pattern; Etching the second insulating layer, the etch stop layer and the first insulating layer to form a trench having a contact hole in a lower portion thereof; Depositing a copper film to fill the contact hole and the trench; CMPing the copper film until the second insulating film is exposed; And removing the copper residue on the second insulating layer by immersing the resultant substrate in a diluted HF solution.

여기서, 상기 희석된 HF 용액은 바람직하게 HF/H2O이며, 이때, 상기 HF/H2O에서의 HF와 H2O의 혼합비율은 1:10∼500 정도로 한다.Here, the diluted HF solution is preferably HF / H 2 O, wherein the mixing ratio of HF and H 2 O in the HF / H 2 O is about 1:10 to 500.

또한, 상기 희석된 HF 용액으로서 NH4HF/HF/H2O, 또는, HF/H2O/H2O2를 사용하는 것도 가능하다.It is also possible to use NH 4 HF / HF / H 2 O, or HF / H 2 O / H 2 O 2 as the diluted HF solution.

본 발명에 따르면, 구리막의 CMP 후에 기판 결과물을 희석된 HF 용액 내에 침지시킴으로써 절연막 표면을 에치백함과 동시에 상기 절연막 상의 구리 잔류물을 신뢰성있게 제거할 수 있으며, 아울러, 단순히 기판 결과물을 희석된 HF 용액 내에 침지시키는 것만으로 구리 잔류물을 제거할 수 있는 바, 제조비용의 증가도 방지할 수 있다.According to the present invention, after the CMP of the copper film, the substrate product is immersed in the diluted HF solution to etch back the surface of the insulating film and to reliably remove the copper residue on the insulating film. The copper residue can be removed only by immersion in the bar, and an increase in manufacturing cost can be prevented.

(실시예)(Example)

이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d는 본 발명의 실시예에 따른 구리배선 형성방법을 설명하기 위한 공정별 단면도이다.2A to 2D are cross-sectional views of processes for describing a method of forming a copper wiring according to an embodiment of the present invention.

도 2a를 참조하면, 공지의 공정에 따라 소정의 도전 패턴들(도시안됨)이 형성된 반도체 기판(21)의 전 영역 상에 상기 도전 패턴들을 덮도록 제1절연막(22)을 형성한다. 그런다음, 상기 제1절연막(32) 상에, 예컨데, 질화막으로 이루어진 식각정지막(23)을 형성한 후, 상기 식각정지막(23) 상에 표면 평탄화가 이루어진 제2절연막(24)을 형성한다.Referring to FIG. 2A, a first insulating layer 22 is formed to cover the conductive patterns on the entire region of the semiconductor substrate 21 on which predetermined conductive patterns (not shown) are formed according to a known process. Then, an etch stop film 23 made of, for example, a nitride film is formed on the first insulating film 32, and a second insulating film 24 having surface planarization is formed on the etch stop film 23. do.

도 2b를 참조하면, 공지의 듀얼 다마신 공정에 따라 제2절연막(24)과 식각정지막(23) 및 제1절연막(22)을 식각하고, 이를 통해, 구리배선이 형성될 영역을 한정하는 콘택홀(도시안됨)을 포함한 트렌치(25)를 형성한다.Referring to FIG. 2B, the second insulating layer 24, the etch stop layer 23, and the first insulating layer 22 are etched according to a known dual damascene process, thereby defining a region in which the copper wiring is to be formed. A trench 25 including a contact hole (not shown) is formed.

도 2c를 참조하면, 트렌치(25)를 완전 매립하도록 제2절연막(24) 상에 전기도금 방식에 따라 두껍게 구리막을 증착한다. 그런다음, 상기 제2절연막(24)이 노출될 때까지 구리막을 CMP하고, 이를 통해, 구리배선(26)을 형성한다.Referring to FIG. 2C, a thick copper film is deposited on the second insulating layer 24 by electroplating to completely fill the trench 25. Then, the copper film is CMP until the second insulating film 24 is exposed, thereby forming the copper wiring 26.

여기서, 전술한 바와 같이 구리막에 대한 CMP 후에는 제2절연막(24) 상에는 구리 잔류물(27)이 발생된다.As described above, after the CMP with respect to the copper film, a copper residue 27 is generated on the second insulating film 24.

도 2d를 참조하면, 상기 기판 결과물을 희석된 HF 용액, 예컨데, HF의 농도를 0.2∼10%, 보다 정확하게는 HF와 H2O의 혼합비율이 1:10∼500로 한 HF 용액 내에 침지시킨다. 이 경우, 절연막, 즉, 제2절연막(24)이 에치백되며, 이에 따라, 구리막 CMP 후에 제2절연막(24) 상에 발생된 구리 잔류물이 함께 제거되고, 이 결과로서, 구리 잔류물이 없는 최종적인 구리배선(26a)이 형성된다.Referring to FIG. 2D, the substrate product is immersed in a diluted HF solution, for example, an HF solution having a concentration of HF of 0.2 to 10%, more precisely, a mixing ratio of HF and H 2 O of 1:10 to 500. In this case, the insulating film, i.e., the second insulating film 24 is etched back, whereby the copper residue generated on the second insulating film 24 after the copper film CMP is removed together, and as a result, the copper residue The final copper wiring 26a is formed.

여기서, 희석된 HF 용액으로서 HF/H2O 이외에 BOE(Buffered Oxide Etchant : NH4HF/HF/H2O), 또는, HF/H2O/H2O2를 사용하는 것도 가능하다.Here, in addition to HF / H 2 O, BOE (Buffered Oxide Etchant: NH 4 HF / HF / H 2 O) or HF / H 2 O / H 2 O 2 may be used as the diluted HF solution.

이상에서와 같이, 본 발명은 구리막의 CMP 후에 기판 결과물을 희석된 HF 용액 내에 침지시킴으로써 절연막 상의 구리 잔류물을 용이하면서도 신뢰성있게 제거할 수 있으며, 아울러, 단순히 기판 결과물을 희석된 HF 용액 내에 침지시키는 것만으로 구리 잔류물을 제거할 수 있는 바, 제조비용의 증가도 방지할 수 있다.As described above, the present invention can easily and reliably remove the copper residue on the insulating film by immersing the substrate product in the diluted HF solution after the CMP of the copper film, and simply by dipping the substrate product in the diluted HF solution. Only the copper residues can be removed, thereby increasing the manufacturing cost.

기타, 본 발명은 그 요지가 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (4)

소정의 도전 패턴들이 형성된 반도체 기판 상에 제1절연막과 식각정지막 및 제2절연막을 차례로 형성하는 단계;Sequentially forming a first insulating film, an etch stop film, and a second insulating film on a semiconductor substrate on which predetermined conductive patterns are formed; 상기 제2절연막과 식각정지막 및 제1절연막을 식각하여 하부에 콘택홀을 구비한 트렌치를 형성하는 단계;Etching the second insulating layer, the etch stop layer and the first insulating layer to form a trench having a contact hole in a lower portion thereof; 상기 콘택홀 및 트렌치를 매립하도록 구리막을 증착하는 단계;Depositing a copper film to fill the contact hole and the trench; 상기 제2절연막이 노출될 때까지 구리막을 CMP하는 단계; 및CMPing the copper film until the second insulating film is exposed; And 상기 기판 결과물을 희석된 HF 용액 내에 침지시켜 제2절연막 상의 구리 잔류물을 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.Removing the copper residue on the second insulating layer by immersing the resultant substrate in a diluted HF solution. 제 1 항에 있어서, 상기 희석된 HF 용액은 HF/H2O인 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.The method of claim 1, wherein the diluted HF solution is HF / H2O. 제 2 항에 있어서, 상기 HF/H2O 용액은 HF와 H2O의 혼합비율을 1:10∼500로 한 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.The method for forming copper wiring of a semiconductor device according to claim 2, wherein the HF / H2O solution has a mixing ratio of HF and H2O of 1:10 to 500. 제 1 항에 있어서, 상기 희석된 HF 용액은 NH4HF/HF/H2O, 또는, HF/H2O/H2O2인 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.The method of claim 1, wherein the diluted HF solution is NH4HF / HF / H2O, or HF / H2O / H2O2.
KR1020030038015A 2003-06-12 2003-06-12 Method for forming Cu wiring of semiconductor device KR20040107135A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020030038015A KR20040107135A (en) 2003-06-12 2003-06-12 Method for forming Cu wiring of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020030038015A KR20040107135A (en) 2003-06-12 2003-06-12 Method for forming Cu wiring of semiconductor device

Publications (1)

Publication Number Publication Date
KR20040107135A true KR20040107135A (en) 2004-12-20

Family

ID=37381411

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020030038015A KR20040107135A (en) 2003-06-12 2003-06-12 Method for forming Cu wiring of semiconductor device

Country Status (1)

Country Link
KR (1) KR20040107135A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7351653B2 (en) 2005-08-11 2008-04-01 Samsung Electronics Co., Ltd. Method for damascene process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7351653B2 (en) 2005-08-11 2008-04-01 Samsung Electronics Co., Ltd. Method for damascene process

Similar Documents

Publication Publication Date Title
CN101256977B (en) Semiconductor structure and forming method of semiconductor structure
US7638434B2 (en) Method for filling a trench in a semiconductor product
JP2004225159A (en) Method for forming conductive copper structure
US20040171277A1 (en) Method of forming a conductive metal line over a semiconductor wafer
US6881661B2 (en) Manufacturing method of semiconductor device
US20070066072A1 (en) Method of fabricating semiconductor device
US20060189131A1 (en) Composition and process for element displacement metal passivation
KR20040107135A (en) Method for forming Cu wiring of semiconductor device
KR20080047541A (en) Method for forming a capping layer on a semiconductor device
US6228765B1 (en) Structure and method for forming conductive members in an integrated circuit
US7276439B2 (en) Method for forming contact hole for dual damascene interconnection in semiconductor device
KR100688561B1 (en) Method for forming interconnections for semiconductor device
US7452802B2 (en) Method of forming metal wiring for high voltage element
US7021320B2 (en) Method of removing a via fence
CN110571189A (en) Conductive plug and forming method thereof and integrated circuit
KR0176195B1 (en) Method for forming wiring of semiconductor device
KR100906306B1 (en) Method of forming a copper wiring in a semiconductor device
KR100434700B1 (en) Method for forming copper of semiconductor device
KR100406587B1 (en) Method for fabricating semiconductor device
KR20040080599A (en) Method for forming contact plug of semiconductor device
JP2001210644A (en) Semiconductor device and its manufacturing method
KR100638976B1 (en) Method for forming Cu interconnection of semiconductor device
KR100657760B1 (en) Fabricating method of metal line in semiconductor device
KR100699593B1 (en) Method of forming dual damascene pattern in semiconductor device
KR20050050190A (en) Contact plug of the semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
N231 Notification of change of applicant
WITN Withdrawal due to no request for examination