KR20040103017A - Memory system including an on chip temperature sensor for controlling the refresh rate of a memory device - Google Patents

Abstract

PURPOSE: A memory system having a temperature sensing device to control refresh period is provided to reduce power consumption and required time during the refresh operation by effectively controlling the refresh period in response to the inner temperature of the memory device. CONSTITUTION: A memory system having a temperature sensing device(180) to control refresh period includes a memory device(100) and a controller(200). The memory device is provided with a temperature sensing device to detect the inner temperature. And, the controller controls the refresh operation of the memory device by receiving the temperature information from the temperature sensing device.

Description

MEMORY SYSTEM INCLUDING AN ON CHIP TEMPERATURE SENSOR FOR CONTROLLING THE REFRESH RATE OF A MEMORY DEVICE}

The present invention relates to a memory system, and more particularly to a memory system and apparatus for effectively controlling the refresh cycle.

In general, in the case of a memory device (eg, a dynamic random access memory (DRAM)), a basic cell is composed of one transistor and one capacitor, and data is stored in the capacitor. However, the capacitor formed on the semiconductor substrate is not completely electrically separated from the surroundings, and thus the stored data, that is, the charge is discharged without being preserved. In other words, leakage current may occur and damage data of the memory cell. Thus, the memory device periodically performs a refresh operation to maintain the charge stored in the capacitor.

The memory device having the refresh operation mode performs the refresh operation by sequentially changing its internal address by an external command. That is, when the refresh operation mode is entered by an external command, the row address is sequentially increased at predetermined intervals and the word line of the memory cell is selected. The charge stored in the capacitor corresponding to the word line is amplified by the sense amplifying means and stored in the capacitor again. Through this series of refresh processes, the stored data is preserved intact.

However, the refresh operation conventionally used for preserving information stored in the memory device is performed at regular intervals regardless of the temperature inside the memory device. This makes the refresh characteristic weaker as the temperature rises, and the refresh operation cycle must be accelerated. Therefore, the circuit designer sets the refresh operation cycle based on the high temperature.

For this reason, even when the information stored in the memory cell is maintained in a low temperature state, the refresh operation is performed at a set period based on the high temperature, and thus wastes power consumed by unnecessary refresh operation at a low temperature and operation time according to the same. There is a problem done.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a memory system that effectively performs a refresh operation by embedding a temperature sensing device inside a chip.

1 is a block diagram illustrating a memory system incorporating a temperature sensing device according to the present invention.

FIG. 2 is a block diagram illustrating a memory device of FIG. 1.

3 is a block diagram illustrating a memory controller of FIG. 1.

4 is a block diagram illustrating another exemplary embodiment of the memory device of FIG. 1.

5 is a block diagram illustrating another embodiment of the memory controller of FIG. 1.

6 is a circuit diagram illustrating the temperature sensing device of FIG. 2 or 4.

FIG. 7 is a graph illustrating temperature characteristics of the temperature sensing device of FIG. 6.

Explanation of symbols on the main parts of the drawings

100: memory device 101, 301: address pad

102, 302: command pad 103, 303: power pad

104, 304: data input / output pad 105: temperature output pad

110, 310: memory cell array 120, 320: peripheral circuit

130: data input / output circuit 140, 340: row address buffer

150, 350: row decoder 160, 360: column address buffer

170, 370: column decoder 180, 380: temperature sensing device

201 and 401: command pad 202 and 402: data input / output pad

203: temperature input pad 210, 410: temperature analysis device

220, 420: refresh cycle control generator

230, 430: refresh cycle generator 240, 440: refresh command generator

250 and 450: data memory section 330: data input / output amplification circuit

390: data input and output register

According to an aspect of the present invention, there is provided a memory system including a temperature sensing device for sensing an internal temperature, and receiving temperature information from a memory device for storing data and the temperature sensing device. And a control device for controlling the refresh operation.

In this embodiment, the memory device is provided with transmitting means for transmitting the temperature information, and the control device is provided with receiving means for receiving the temperature information.

In this embodiment, the transmitting means and the receiving means are characterized in that each of the pads provided separately in the memory device and the control device.

In another embodiment, the transmitting means and the receiving means are data input / output pads provided in the memory device and the control device, respectively.

In addition, the memory device according to the present invention comprises: a memory cell array for storing data; Selection circuitry for selecting rows and columns of the memory cell array; Temperature sensing means for sensing an internal temperature and converting the internal temperature into an electrical signal representing temperature information; And transmission means for transmitting the electrical signal of the temperature sensing means to the outside.

In this embodiment, the transmitting means is a pad provided separately in the memory device.

In another embodiment, the transmitting means is a data input / output pad provided in the memory device.

In addition, a control device for controlling a memory device according to the present invention comprises: receiving means for receiving a temperature signal provided from the memory device; Analysis means for analyzing a temperature signal provided by said receiving means; And control means for adjusting the refresh cycle of the memory device in accordance with the temperature signal analyzed by the analyzing means.

In this embodiment, the receiving means is characterized in that the pad provided separately in the control device.

In another embodiment, the receiving means is a data input / output pad provided in the control device.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating an interconnection structure of a memory device 100 and a memory controller 200 as a memory system for controlling a refresh operation of a memory device (eg, DRAM) according to the present invention.

Referring to FIG. 1, a memory system according to the present invention includes a memory device 100 and a memory controller 200. The memory device 100 has a temperature sensing device 180 that can sense an internal temperature. The temperature sensing device 180 senses an internal temperature of the memory device 100 and sends temperature information to the memory controller 200. The memory controller 200 includes a temperature analyzer 210. The temperature analysis device 210 analyzes temperature information provided from the memory device 100 to control a refresh operation cycle by varying a refresh command cycle input to the memory device 100. A detailed description of the memory device 100 is described in detail with reference to FIG. 2 or FIG. 4 to be described later. A detailed description of the memory controller 200 will be described in detail with reference to FIG. 3 or FIG. 5 to be described later.

FIG. 2 is a block diagram illustrating the memory device 100 of FIG. 1 in detail. The memory device 100 includes the temperature sensing device 180 and a temperature output pad 105. Referring to FIG. 2, the configuration and operation of the memory device 100 are described as follows.

The memory device 100 according to the present invention may include a pad unit 101, 102, 103, 104, 105, a memory cell array 110, a peripheral circuit 120, a data input / output circuit 130, and a selection circuit 140. 150, 160, 170, and a temperature sensing device 180.

The pad unit includes a command pad 102 for receiving operation command information, an address pad 101 for applying an address for designating a memory cell, a data input / output pad 104 for data input / output, and a power pad 104 for supplying power. In the present invention, the temperature output pad 105 for outputting the temperature sensing information is additionally included.

The memory cell array 110 has a plurality of memory cells arranged in rows and columns, respectively, and memory cells are selected by the row decoder 150 and the column decoder 170. In FIG. 2, only some of the plurality of memory cells are simply illustrated as an example for convenience of description herein.

The peripheral circuit 120 interprets the information input to the command pad to operate the memory device 100. The peripheral circuit 120 includes a control circuit for operating the memory device 100, an internal address adder, a refresh control circuit, and the like. The circuits and operating principles in the peripheral circuit 120 are well known to those skilled in the art.

The selection circuits 140, 150, 160, and 170 are circuits for selecting a specific cell in the memory cell array 110 based on information input to the address pad. The row address buffer 140 and the row decoder 150 select rows in the memory cell array 110, and the column address buffer 160 and the column decoder 170 select columns.

The data input / output circuit 130 is a circuit for inputting or outputting data to a memory cell by a command.

2, the memory device 100 according to the present invention has the same elements as a conventional memory device (for example, DRAM), but a temperature sensing device 180 is added therein. . A detailed description of the temperature sensing device 180 is described with reference to FIG. 6 to be described later.

3 is a block diagram illustrating in detail the memory controller 200 of FIG. 1. The configuration of the memory controller 200 shown in FIG. 3 is a schematic diagram, and only parts necessary for the present invention are shown, and parts related to the remaining components are omitted. The configuration and operation of the memory controller 200 will be described with reference to FIG. 3.

The memory controller receives temperature information output through the temperature output pad 105 shown in FIG. 1 through the temperature input pad 203. The temperature information input to the temperature input pad 203 is analyzed by the temperature analyzer 210, and then the analyzed information is provided to the refresh cycle control generator 220. The refresh period control generator 220 sends the received information to the refresh period generator 230. The refresh period generator 230 provides information received to the refresh command generator 240 that controls the refresh command cycle of the memory device 100 to link the refresh command cycle of the memory device 100 with an internal cycle. The refresh cycle of the memory device 100 is controlled while being variable.

4 and 5 are block diagrams illustrating another example of the memory system of FIG. 1. Compared with the memory device and the memory controller of FIGS. 2 and 3, the temperature information of the temperature sensing device 180 is not inputted or outputted through the temperature output pad 105 or the temperature input pad 203. The input / output is performed through the existing data input / output pad 202.

4 is a block diagram illustrating a memory device 300 according to another exemplary embodiment of the present invention, and FIG. 5 is a block diagram illustrating a memory controller 400 according to another exemplary embodiment of the present invention. The operation of the memory system will now be described with reference to FIGS. 4 and 5.

When the memory controller 400 needs the output of the temperature sensing device 380 embedded in the memory device 300, when the memory controller 400 applies a specific command to the memory device 300, the The memory device 300 does not output data but outputs temperature information of the temperature sensing device 380. The memory controller 400 receives temperature information, analyzes the temperature of the memory device 300, and changes or maintains a refresh cycle. The reason for this is to reduce pads and pins due to the additional placement of the pads.

6 is an internal circuit diagram of the temperature sensing devices 180 and 380 embedded in the memory devices 100 and 300 of FIG. 2 or 4. The configuration and operation of the temperature sensing apparatuses 180 and 380 will now be described with reference to FIG. 6. The temperature sensing devices 180 and 380 of FIG. 6 are examples of a temperature sensing circuit using a general bandgap reference circuit.

Referring to FIG. 6, it is assumed that diode D1 189 and diode D2 190 are the same junction diode, and the aspect ratio (W / L) of Mp1: Mp2: Mp3: Mp4 and Mn1: Mn2: Mn3: Mn4 is M Assume that: 1: M: M Then, the current of Io: Ir = M: 1 flows by the operation of the current mirrors of Mp1 and Mp2 and Mn1 and Mn2, and the node voltages of A and B become equal. The diode current expression is I = Is {e (VD / VT) -1} ≒ Is {e (VD / VT)} in the turn-on period. Here, Is is a reverse saturation current, VD is a diode voltage, and VT = kT / q means a thermal voltage.

In FIG. 6, VA = VB = VD1 = VD2 + (Ir * R). However, since Io = Is * e (VD1 / VT), VD1 = VT * ln (Io / Is), and Ir = Is * e (VD2 / VT), VD2 = VT * ln (Ir / Is) = VT * ln ( M * Io / Is). Therefore, VT * ln (Io / Is) = VT * ln (M * Io / Is) + Ir * R. If both sides are divided by R, Ir = VT * ln (M) / R, and a current proportional to temperature flows. In addition, if I1, I2, and Io are set to flow a current in a similar region, VC and VD become almost equal to the value of VB, and VB = VD1 = VT * ln (Io / Is). Usually VT also increases with temperature, but Is increases much more. Therefore, diode voltage generally has a characteristic of decreasing with temperature. Eventually, the tuning of the resistor R1 192 and the resistor R2 193 can be designed to cross the values of Io and I1, Io and I2 at a specific temperature, so that a specific temperature can be detected using this.

7 is a graph illustrating temperature characteristics of the circuit diagram of FIG. 6. The temperature range can be further refined, but for convenience of explanation, only 45 ° C and 85 ° C are shown as an example. Temperature sensing at 45 ° C. outputs T1 at the point where I 1 crosses or decreases with Ir. Similarly, 85 ° C. outputs T 2 at the point where I 2 crosses or decreases with Ir.

By the memory system incorporating the temperature sensing device of the present invention, instead of controlling the refresh cycle irrespective of temperature as in the memory device of the prior art, by effectively controlling the refresh cycle in accordance with the internal temperature of the memory device, the refresh operation It can reduce power consumption and time required.

Claims (10)

A memory device including a temperature sensing device for sensing an internal temperature; And a control device which receives temperature information from the temperature sensing device and controls a refresh operation of the memory device. The method of claim 1, The memory device has transmission means for transmitting the temperature information, And the control device comprises a receiving means for receiving the temperature information. The method of claim 2, And the transmitting means and the receiving means are pads provided separately in the memory device and the control device, respectively. The method of claim 2, And the transmitting means and the receiving means are data input / output pads provided in the memory device and the control device, respectively. A memory cell array for storing data; Selection circuitry for selecting rows and columns of the memory cell array; Temperature sensing means for sensing an internal temperature and converting the internal temperature into an electrical signal representing temperature information; And transmission means for transmitting the electrical signal of the temperature sensing means to the outside. The method of claim 5, wherein And the transmitting means is a pad provided separately in the memory device. The method of claim 5, wherein And the transmitting means is a data input / output pad provided in the memory device. A control device for controlling the memory device of claim 5, comprising: Receiving means for receiving a temperature signal provided from said memory device; Analysis means for analyzing a temperature signal provided by said receiving means; And control means for adjusting a refresh cycle of the memory device in accordance with the temperature signal analyzed by the analyzing means. The method of claim 8, And the receiving means is a pad provided separately in the control device. The method of claim 8, And the receiving means is a data input / output pad provided in the control device.