KR20040102736A - Reset signal generator can discriminate power fail reset and power on reset - Google Patents

Abstract

PURPOSE: A reset signal generator equipped with a power reset flag generating circuit discriminating power-on reset and power-fail reset is provided to offer an optimal initialization program fit to respective reset features on an interrupt service routine by discriminating the power-on reset and the power-fail reset, and increase performance of a processor and system efficiency by preventing system overload. CONSTITUTION: A low voltage detector(25) outputs the corresponding signal if power voltage is increased over a prescription voltage. A pulse generator(31) generates a pulse having a predetermined width depending on the output of the low voltage detector. An AND gate(32) inverts/receives a power-on signal activated if the power voltage is supplied to the system or receiving the output of the pulse generator. A flag signal generator(33) generates a flag signal discriminating the power-on reset and the power-fail reset by receiving an output signal of the AND gate and the pulse generator.

Description

RESET SIGNAL GENERATOR CAN DISCRIMINATE POWER FAIL RESET AND POWER ON RESET}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset signal generator of a semiconductor device, and more particularly, to a reset signal generator having a power reset flag generating circuit so as to distinguish and process a power-on reset and a power-fail reset.

Typically, every system has a built-in power interruption circuit. In particular, sophisticated micro-controller systems have a power on detection circuit and a low voltage detection circuit to produce a power on reset signal or a power interruption reset signal.

Conventionally, the same reset signal was used without distinguishing between the power-on reset and the power fail reset. This conventional technology will be described with reference to FIG.

The reset signal generator according to the related art includes a Schmitt trigger (11) receiving an externally applied reset signal, a noise canceller (12) for removing noise included in the output signal of the Schmitt trigger, and a system in an infinite loop. A watch dog timer (WDT) 14 for outputting a signal for escape from a missing or null state, and a corresponding signal for a power supply voltage rising above a predetermined voltage; A low voltage detector (LVD) 15, a first OR gate 16 that receives an output signal of the watchdog timer 14 and an output signal of the low voltage detector 15, and the first OR And a second OR gate 13 receiving the output signal of the gate 16 and the output signal of the noise canceller 12, and the output of the second OR gate 13 is a CPU or a peripheral circuit 17. To reset the system. To be used.

Next, the operation of the reset signal generator according to the prior art thus constructed will be described. First, the reset signal input to the Schmitt trigger 11 corresponds to a reset button of a computer system.

The externally applied reset signal is input to the Schmitt trigger 11 and output as a shaped waveform, and the output of the Schmitt trigger removes noise included in the signal through the noise canceller 11 to remove the second OR gate 13. Will be printed).

The watchdog timer 14 outputs an 'H' signal to the first OR gate 16 to reset the system when the system is in an infinite loop or null.

The low voltage detector 15 outputs an 'H' signal to the first OR gate 16 when power is turned on in the system or when a power failure occurs when the power supply voltage is unstable during system operation.

The first OR gate 16 inputs the output signal of the watchdog timer 14 and the output signal of the low voltage detector 15, and the output signal of the first OR gate 16 to the second OR gate 13. Is entered. Also as described above, the second OR gate 13 receives the output of the noise canceller 13.

As a result, in the reset signal generator according to the related art, if any one of an externally applied reset signal, a reset signal according to the output of the watchdog timer, or a reset signal according to the output of the low voltage detector is activated, the system is controlled through the second OR gate 13. Will be reset.

That is, in the related art, the scheme for generating the same reset signal and resetting the system even when the power is turned on and during the power failure during operation is all.

Therefore, even after a power failure in which the power is unstable due to unstable power during system operation after power-on, the same reset signal is generated as the reset signal applied at power on, and the system initializes and restarts from the beginning.

This will be described in more detail as follows. In processors such as a central processing unit (CPU) and a micro controller unit (MCU), power-related reset signals are divided into power-on reset signals and power fail reset signals, and are divided into different interrupt service routines at system initialization. Processing may increase processor performance and system efficiency, but this has not been possible in the prior art.

In particular, a memory test, a hard disk test, and a peripheral device such as a keyboard and a mouse are performed in a power-on reset operation, such as a computer bios, and the same service routine as the power-on reset operation is performed during a power failure. If you do, there was a problem that the system is overloaded.

Therefore, if the power on reset and the power fail reset are used separately, and the system is configured to test only the minimum items tested during the power on reset, the overall system overload can be reduced to improve performance. .

When such a power-on reset is called a cold boot, the power fail reset may also be called a warm boot.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object thereof is to provide a reset signal generator having a power reset flag generating circuit so as to distinguish and process a power-on reset and a power-fail reset.

1 is a circuit diagram showing the configuration of a reset signal generator according to the prior art;

2 is a circuit diagram showing the configuration of a reset signal generator having a power reset flag generation circuit according to an embodiment of the present invention;

3 is a circuit diagram showing a detailed configuration of a power reset flag generating circuit according to an embodiment of the present invention;

4 is a waveform diagram showing each signal waveform in the power reset flag generating circuit according to an embodiment of the present invention;

5 illustrates a flag signal generator according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

21: Schmitt trigger 22: Noise canceller

23: third OR gate 24: watchdog timer

25 low voltage detector 26 power reset flag generating circuit

27: fourth OR gate 28: core and peripheral circuit

31: pulse generator 32: end gate

33: flag signal generator

The present invention for achieving the above object, in the reset signal generator for generating a signal for resetting the system, receiving the output of the low voltage detector to distinguish the power-on reset and the power fail reset signal corresponding to each reset And a reset signal generator including an output power reset flag generating circuit.

The present invention provides a reset by adding a power reset flag generation circuit in order to change a system related to a power-related reset signal generation system to distinguish between a power-on reset signal generated at power-on and a power fail reset signal generated at power failure. It relates to a signal generator.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

2 to 3 illustrate a reset signal generator according to an embodiment of the present invention. First, referring to FIG.

The overall configuration of the reset signal generator according to an embodiment of the present invention is similar to the reset signal generator according to the related art shown in FIG. 1, but by adding a power reset flag generation circuit 26 to the output terminal of the low voltage detector 25. This is different from the prior art.

Referring to this, the reset signal generator according to an embodiment of the present invention, the Schmitt trigger 21 for receiving a reset signal applied from the outside, and the noise canceller 22 for removing the noise included in the output signal of the Schmitt trigger ), A watchdog timer (WDT) 24 which outputs a signal for exiting the system when the system is in an infinite loop or in a null state, and correspondingly when the power supply voltage rises above a certain voltage. A low voltage detector (LVD) 25 for outputting a signal, a power reset flag generation circuit 26 for outputting a reset signal and a flag signal using the output signal of the low voltage detector, and the watchdog timer 24, respectively. An output signal of the third OR gate 27 receiving the reset signal, an output signal of the third OR gate 27, and an output signal of the noise canceler 22, from among an output signal and an output signal of the power reset flag generation circuit; And a fourth OR gate 23 receiving a call.

Here, the flag signal of the output signal of the fourth OR gate 23 and the output signal of the power reset flag generating circuit is input to the CPU and the peripheral circuit 28 to be used to reset the system.

That is, the power reset flag generation circuit 26 added in one embodiment of the present invention outputs the same signal to the third OR gate 27 at the time of power-on, and outputs a flag signal at the time of power failure. Output to the peripheral circuit (28).

By using such a flag signal, during power failure, the system can be reset by jumping to an interrupt service routine different from the service routine applied at power on.

FIG. 3 is a diagram showing the detailed configuration of the power reset flag generating circuit 26 shown in FIG. 2 together with the low voltage detector 25. The power reset flag generating circuit will be described with reference to the drawing.

The power reset flag generation circuit receives the output of the low voltage detector 25 and outputs a PORSet1 signal, which is a pulse signal having a predetermined width, corresponding to the output of the low voltage detector 25, the inverted PORON signal and the pulse generator 31. An AND gate 32 that receives the output PORSet1 signal and outputs a PORSet1 'signal, and a flag that receives the PORSet1' signal and the PORSet1 signal, which are outputs of the AND gate, generates a flag signal and outputs the flag signal to the CPU and the peripheral circuit. And a signal generator 33.

Here, the PORSet1 signal, which is an output signal of the pulse generator 31, is input not only to the AND gate 32 and the flag signal generator 33, but also to the third OR gate 27 shown in FIG.

The PORON signal is a signal activated by 'H' when power is supplied to the system. The PORON signal is inverted and input to the AND gate 32. Hereinafter, with reference to FIG. 4.

FIG. 4 is a signal waveform diagram showing waveforms of various signals used in the power reset flag generating circuit shown in FIG. 3, and the operation of the power reset flag generating circuit will be described with reference to the figure.

First, when power is supplied to the system, the power supply voltage starts to rise from the VSS level to the VCC level. At this time, the low voltage detector 25 outputs a corresponding signal when the power supply voltage becomes higher than a predetermined voltage (see the low voltage detector in FIG. 4). The output signal waveform of is not shown).

In this way, if the power supply voltage is unstable during the operation of the system other than when the power is initially supplied, the power supply voltage decreases and then returns to the original operating voltage. Output the corresponding signal.

The pulse generator 31 receives the output signal of the low voltage detector 25 and generates and outputs a PORSet1 signal, which is a pulse signal having a predetermined width. Therefore, it can be seen that the PORSet1 signal that is activated high for a predetermined time is generated not only when the power is initially turned on but also when the power supply voltage becomes unstable and decreases and returns to the original level.

The PORON signal is a signal that is activated high when power is supplied to the system, and the PORON signal is inputted with an AND gate 32 with its phase reversed. The PORSet1 signal is also input to the AND gate 32.

Therefore, the PORSet1 'signal, which is the output signal of the AND gate 32, is as shown in FIG. That is, the PORSet1 'signal is also activated high only during a period in which power is initially supplied and the PORSet1 signal is activated high, and maintains a low level during power failure.

The flag signal generator 33 generates a flag signal for distinguishing the power-on reset and the power fail reset by using the PORSet1 signal output from the pulse generator 31 and the POESet1 'signal output from the AND gate 32. As the output circuit, the waveform of the flag signal is as shown in FIG.

That is, when power is first turned on, the flag signal maintains a high level. However, the flag signal falls to a low level during a power failure in which the power supply voltage is unstable during system operation.

The flag signal is directly input to the CPU and the peripheral circuit 28. Using this flag signal, the system load can be reduced by applying different interrupt service routines during the power-on reset and power fail reset operations.

FIG. 5 is a diagram illustrating an exemplary embodiment of simply implementing the flag signal generator 33 shown in FIG. 3, and for generating a PORFlag signal using a PORSet1 signal and a PORSet1 'signal having a waveform as shown in FIG. 4. It is a figure which shows a circuit structure.

Referring to Fig. 5, the flag signal generator 33 can be configured as a simple D flip-flop with a clock input. Here, the PORSet1 signal, which is an output signal of the pulse generator, is input to the clock input terminal of the D flip-flop 51, and the PORSet1 'signal, which is the output of the AND gate, is input to the D input terminal of the D flip-flop 51.

As a result, the output signal of the D flip-flop 51 having such an input signal becomes a PORFlag signal having the waveform shown in FIG.

In the case of applying the reset signal generator according to an embodiment of the present invention, since the system can be reset by dividing the power-on reset and the power fail reset, unnecessary test operation can be reduced, thereby increasing the efficiency of the system.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in the art.

According to the present invention, the power-on reset and the power fail reset can be distinguished to enable optimal initialization programming for each reset characteristic in the interrupt service routine. Preventing system overload leads to increased processor performance and system efficiency.

Claims (4)

In the reset signal generator for generating a signal for resetting the system, And a power reset flag generating circuit configured to receive the output of the low voltage detector and distinguish a power on reset and a power fail reset to output a signal corresponding to each reset. The method of claim 1, The power reset flag generating circuit, A low voltage detector for outputting a signal corresponding to the increase in power supply voltage above a predetermined voltage; A pulse generator for generating a pulse having a predetermined width according to the output of the low voltage detector; An AND gate which receives an inverted power-on signal that is activated when a power supply voltage is supplied to the system and receives an output of the pulse generator; And A flag signal generator that receives a output signal of the AND gate and an output signal of the pulse generator and generates a flag signal that can distinguish a power on reset and a power fail reset. Reset signal generator characterized in that comprises a. The method of claim 2, The flag signal generator, And a clocked D flip-flop that receives the output signal of the pulse generator through a clock input terminal and receives the output signal of the AND gate into an input terminal. A Schmitt trigger receiving an externally applied reset signal; A noise canceller for removing noise included in an output signal of the Schmitt trigger; A watchdog timer that outputs a signal to escape from when the system is stuck in an infinite loop or is in a null state; A low voltage detector for outputting a signal corresponding to the increase in power supply voltage above a predetermined voltage; A power reset flag generation circuit for outputting a power on reset signal and a power fail flag signal using the output signal of the low voltage detector; A first OR gate configured to receive a power on reset signal among an output signal of the watchdog timer and an output signal of the power reset flag generation circuit; And A second OR gate receiving the output signal of the first OR gate and the output signal of the noise canceller; Reset signal generator comprising a.