KR20040102262A - Method for manufacturing metal layer in semiconductor device - Google Patents

Method for manufacturing metal layer in semiconductor device Download PDF

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Publication number
KR20040102262A
KR20040102262A KR1020030033616A KR20030033616A KR20040102262A KR 20040102262 A KR20040102262 A KR 20040102262A KR 1020030033616 A KR1020030033616 A KR 1020030033616A KR 20030033616 A KR20030033616 A KR 20030033616A KR 20040102262 A KR20040102262 A KR 20040102262A
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South Korea
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semiconductor device
metal wiring
metal layer
film
wiring layer
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KR1020030033616A
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Korean (ko)
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KR100532748B1 (en
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김광수
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아남반도체 주식회사
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Priority to KR10-2003-0033616A priority Critical patent/KR100532748B1/en
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17503—Ink cartridges
    • B41J2/17513—Inner structure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17503—Ink cartridges
    • B41J2/17506—Refilling of the cartridge
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17503—Ink cartridges
    • B41J2/1752—Mounting within the printer
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17503—Ink cartridges
    • B41J2/17559—Cartridge manufacturing

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method of manufacturing a metal line layer of a semiconductor device is provided to reduce remarkably the hillock by depositing an anti-reflective coating on a metal film within predetermined temperature range. CONSTITUTION: A metal film is deposited on an interlayer dielectric with contact holes(S200). An anti-reflective coating is deposited on the resultant structure at a temperature of 200 to 390 °C(S202). A photoresist pattern is formed on the anti-reflective coating(S206). The anti-reflective coating and the metal film are selectively etched by using the photoresist pattern as an etching mask(S208). The photoresist pattern and the anti-reflective coating are removed therefrom.

Description

반도체 소자의 금속 배선층 제조 방법{METHOD FOR MANUFACTURING METAL LAYER IN SEMICONDUCTOR DEVICE}METHOD FOR MANUFACTURING METAL LAYER IN SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자 형성 기술에 관한 것으로, 특히, 반도체 소자의 금속 배선층 제조시 힐록(hillock) 현상을 방지하는데 적합한 반도체 소자의 금속 배선층 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology of forming a semiconductor device, and more particularly, to a method of manufacturing a metal wiring layer of a semiconductor device suitable for preventing a hillock phenomenon in manufacturing a metal wiring layer of a semiconductor device.

일반적으로, 반도체 소자는 여러 단계의 공정 과정을 거쳐 형성되는데, 그 중 포토리소그래피 공정은 포토레지스트층 상부에 소정 부분만을 선택적으로 노광할 수 있도록 패터닝된 마스크 패턴을 개재하여 포토레지스트층에 선택적으로 광을 조사한 후 현상하여 레지스트 패턴을 형성하고, 이 레지스트 패턴을 기반으로 레지스트 패턴 하부에 위치한 금속층을 식각하여 각종 배선, 전극 등에 필요한 패턴을형성하는 공정을 일컫는다.In general, a semiconductor device is formed through a multi-step process, wherein a photolithography process selectively selectively lights a photoresist layer through a patterned mask pattern so as to selectively expose only a predetermined portion over the photoresist layer. It is a process of forming a resist pattern by irradiating and developing a resist pattern, and etching a metal layer under the resist pattern based on the resist pattern to form a pattern necessary for various wirings, electrodes, and the like.

이와 같은 반도체 소자의 제조에서 금속 배선층은 반도체 기판 상에 형성된 개별 소자들을 전기적으로 접속하여 회로를 형성함으로써 반도체 소자가 동작하도록 하는 것이다.In the manufacture of such a semiconductor device, the metal wiring layer electrically connects the individual devices formed on the semiconductor substrate to form a circuit to operate the semiconductor device.

이러한 반도체 소자의 금속 배선층 제조 공정에서 반도체 소자의 미세화에 따라 금속 배선층의 미세한 패턴을 높은 해상도로 형성하기 위하여 금속 배선층 형성을 위한 금속층의 증착 이후 금속층 식각시 반사 방지막을 형성함으로써 포토리소그래피에 의한 노광 공정 진행시 금속층에서의 광의 반사를 방지하도록 한다.Exposure process by photolithography by forming an anti-reflection film during metal layer etching after deposition of the metal layer for forming the metal wiring layer in order to form a fine pattern of the metal wiring layer with high resolution according to the miniaturization of the semiconductor device in the manufacturing process of the metal wiring layer of the semiconductor device. To prevent the reflection of light in the metal layer during the progress.

그러나, 반사 방지막의 형성시 고온 즉, 400℃ 이상의 온도에서 반사 방지막을 형성함으로써 고온에 의해 금속층에서의 힐록이 발생하여 금속 배선층의 결함이 증가할 뿐만 아니라 정확한 임계치의 CD(critical dimension) 구현이 어렵게 되는 문제점이 있다.However, when the anti-reflection film is formed, the anti-reflection film is formed at a high temperature, that is, 400 ° C. or higher, so that the hillock in the metal layer is generated due to the high temperature, thereby increasing the defects of the metal wiring layer and making it difficult to implement a critical dimension (CD) of an accurate threshold. There is a problem.

본 발명은 상술한 문제점을 해결하기 위해 안출한 것으로, 반도체 소자의 금속 배선층 제조시 힐록 발생을 억제하도록 한 반도체 소자의 금속 배선층 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object thereof is to provide a method for manufacturing a metal wiring layer of a semiconductor device to suppress the occurrence of hillock when the metal wiring layer of the semiconductor device is manufactured.

이러한 목적을 달성하기 위한 본 발명의 바람직한 실시예에 따르면, 접촉구를 포함한 층간 절연막 상부에 금속층을 증착하는 단계와, 금속층 상부에 200℃ 내지 390℃의 온도에서 반사 방지막을 증착하는 단계와, 반사 방지막 상부에 감광막 패턴을 형성하는 단계와, 감광막 패턴을 마스크로 드러난 반사 방지막과 금속층을식각하는 단계와, 감광막 패턴과 반사 방지막을 제거하는 단계를 포함하는 반도체 소자의 금속 배선층 제조 방법을 제공한다.According to a preferred embodiment of the present invention for achieving this object, the step of depositing a metal layer on the interlayer insulating film including a contact hole, the step of depositing an antireflection film at a temperature of 200 ℃ to 390 ℃ on the metal layer, and the reflection It provides a method of manufacturing a metal wiring layer of a semiconductor device comprising the step of forming a photoresist pattern on the protective film, etching the antireflection film and the metal layer exposed by the photoresist pattern as a mask, and removing the photoresist pattern and the antireflection film.

도 1a 및 도 1b는 본 발명의 바람직한 실시예에 따른 반도체 소자의 금속 배선층 제조 방법을 도시한 공정 단면도,1A and 1B are cross-sectional views illustrating a method of manufacturing a metal wiring layer of a semiconductor device according to a preferred embodiment of the present invention;

도 2는 본 발명의 바람직한 실시예에 따른 반도체 소자의 금속 배선층 제조 과정을 도시한 흐름도.2 is a flowchart illustrating a metal wiring layer manufacturing process of a semiconductor device according to a preferred embodiment of the present invention.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대하여 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

도 1a 및 도 1b는 본 발명의 바람직한 실시예에 따른 반도체 소자의 금속 배선층 제조 방법을 도시한 공정 단면도이고, 도 2는 본 발명의 바람직한 실시예에 따른 반도체 소자의 금속 배선층 제조 과정을 도시한 흐름도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a metal wiring layer of a semiconductor device according to a preferred embodiment of the present invention, and FIG. 2 is a flowchart illustrating a process of manufacturing a metal wiring layer of a semiconductor device according to a preferred embodiment of the present invention. to be.

도 2는 본 발명의 바람직한 실시예에 따른 하드마스크 제조 과정을 도시한 흐름도이다.2 is a flowchart illustrating a hard mask manufacturing process according to a preferred embodiment of the present invention.

먼저, 도 1a에 도시한 바와 같이, 반도체 기판에 형성된 소자의 전극과 금속 배선층을 전기적으로 접속하기 위한 콘택(미도시) 또는 금속 배선층과 금속 배선층을 전기적으로 접속하기 위한 비아(미도시) 등의 접촉구가 형성된 층간 절연막(100) 상에 금속 배선층 형성을 위한 금속층(102)을 증착한다(S200). 이때, 금속층(102)은 층간 절연막이 형성된 반도체 기판을 챔버로 장입하여 스퍼터링 방법에 형성하는 것이 바람직하다.First, as shown in FIG. 1A, a contact (not shown) for electrically connecting the electrode of the element formed on the semiconductor substrate and the metal wiring layer or a via (not shown) for electrically connecting the metal wiring layer and the metal wiring layer, etc. The metal layer 102 for forming the metal wiring layer is deposited on the interlayer insulating layer 100 having the contact hole (S200). At this time, the metal layer 102 is preferably formed in the sputtering method by charging the semiconductor substrate with the interlayer insulating film formed in the chamber.

그리고, 금속층(102) 상부 전면에 반사 방지막(104)을 형성한다(S202). 반사 방지막(104)의 형성은 금속층(102)이 형성된 반도체 기판을 챔버에 장입하여 PECVD(plasma enhanced chemical vapor deposition) 등의 CVD 방법에 의해 200℃ 내지 390℃의 온도에서 증착하는 것이 바람직하다. 따라서, 종래에 비해 저온에서반사 방지막(104)을 형성함으로써 금속층(102)에서의 힐록을 억제할 수 있으며, 그에 따라 결함 발생을 방지하며 포토리소그래피 공정에서 높은 해상도로 미세 패턴 형성에 있어서 정확한 임계치의 CD 구현이 가능하게 된다.In addition, an anti-reflection film 104 is formed on the entire upper surface of the metal layer 102 (S202). The anti-reflection film 104 may be deposited at a temperature of 200 ° C. to 390 ° C. by a CVD method such as plasma enhanced chemical vapor deposition (PECVD) by charging a semiconductor substrate on which the metal layer 102 is formed. Therefore, by forming the antireflection film 104 at a low temperature as compared with the conventional art, it is possible to suppress the hillock in the metal layer 102, thereby preventing the occurrence of defects, and in the photolithography process, at the high resolution in the photolithography process, CD implementation is possible.

이때, 반사 방지막(104)은 산화막으로 형성하는 것이 바람직하며, 챔버의 RF 파워를 30W 내지 70W, 압력을 2.0Torr 내지 3.0Torr로 유지한 상태에서 SiH4, N2O 및 N2의 소스 가스를 공급하여 형성하는 것이 바람직하다. 또한, 소스 가스인 SiH4는 8sccm 내지 14sccm으로 공급하며, N2O는 300sccm 내지 400sccm으로 공급하며, N2는 4500sccm 내지 5400sccm으로 공급하는 것이 바람직하다.At this time, the anti-reflection film 104 is preferably formed of an oxide film, the source gas of SiH 4 , N 2 O and N 2 while maintaining the RF power of the chamber 30W to 70W, the pressure of 2.0Torr to 3.0Torr It is preferable to supply and form. In addition, SiH 4 as a source gas is supplied at 8 sccm to 14 sccm, N 2 O is supplied at 300 sccm to 400 sccm, and N 2 is preferably supplied at 4500 sccm to 5400 sccm.

이후, 금속층(102)의 힐록 발생을 억제하며 형성된 반사 방지막(104) 상부에 감광막(106)을 도포한다(S204).Subsequently, the photosensitive film 106 is coated on the anti-reflection film 104 formed while suppressing the hillock generation of the metal layer 102 (S204).

그 다음 도 1b에 도시한 바와 같이, 감광막(106)을 금속 배선층 형성을 위한 마스크로 노광 현상하여 감광막 패턴(106)을 형성한다(S206). 이때, 반사 방지막(104)에 의해 노광시 금속층(102)에서 광의 반사를 방지하여 높은 해상도로 미세 패턴의 형성이 가능하게 되며 종래와는 달리 금속층(102)에서의 힐록의 발생이 억제되어 정확한 임계치의 CD 구현이 가능하게 된다.Next, as shown in FIG. 1B, the photosensitive film 106 is exposed and developed with a mask for forming a metal wiring layer to form the photosensitive film pattern 106 (S206). At this time, the antireflection film 104 prevents the reflection of light from the metal layer 102 during exposure, thereby enabling the formation of a fine pattern with high resolution. CD implementation of.

이후, 감광막 패턴(106)을 마스크로 드러난 반사 방지막(104)과 금속층(102)을 식각한다(S208). 그리고, 금속층(102) 상부의 감광막 패턴(106)과 반사 방지막(104)을 제거함으로써 금속 배선층을 형성한다.Thereafter, the anti-reflection film 104 and the metal layer 102 having the photoresist pattern 106 as a mask are etched (S208). Then, the metal wiring layer is formed by removing the photosensitive film pattern 106 and the anti-reflection film 104 on the metal layer 102.

본 발명은 반사 방지막을 일정 범위 이상 낮은 온도로 금속층상에 증착함으로써 힐록 발생률을 대폭 감소시킨 바, 반도체 수율을 향상시키고 보다 정확한 CD를 구현할 수 있는 효과가 있다.The present invention significantly reduces the hillock generation rate by depositing an anti-reflection film on a metal layer at a temperature lower than a predetermined range, thereby improving semiconductor yield and implementing a more accurate CD.

이상, 본 발명을 실시예에 근거하여 구체적으로 설명하였지만, 본 발명은 이러한 실시예에 한정되는 것이 아니라, 그 요지를 벗어나지 않는 범위내에서 여러 가지 변형이 가능한 것은 물론이다.As mentioned above, although this invention was concretely demonstrated based on the Example, this invention is not limited to this Example, Of course, various changes are possible within the range which does not deviate from the summary.

Claims (4)

접촉구를 포함한 층간 절연막 상부에 금속층을 증착하는 단계와,Depositing a metal layer on the interlayer insulating film including the contact hole; 상기 금속층 상부에 200℃ 내지 390℃의 온도에서 반사 방지막을 증착하는 단계와,Depositing an antireflection film on the metal layer at a temperature of 200 ° C. to 390 ° C .; 상기 반사 방지막 상부에 감광막 패턴을 형성하는 단계와,Forming a photoresist pattern on the anti-reflection film; 상기 감광막 패턴을 마스크로 드러난 상기 반사 방지막과 금속층을 식각하는 단계와,Etching the anti-reflection film and the metal layer having the photoresist pattern exposed as a mask; 상기 감광막 패턴과 반사 방지막을 제거하는 단계Removing the photoresist pattern and the anti-reflection film 를 포함하는 반도체 소자의 금속 배선층 제조 방법.Metal wiring layer manufacturing method of a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 반사 방지막을 산화막으로 형성하는 반도체 소자의 금속 배선층 제조 방법.The metal wiring layer manufacturing method of the semiconductor element which forms the said anti-reflective film as an oxide film. 제 2 항에 있어서,The method of claim 2, 상기 산화막의 형성은, 30W 내지 70W의 RF 파워, 2.0Torr 내지 3.0Torr의 압력 조건에서 SiH4, N2O, N2를 공급하여 형성하는 반도체 소자의 금속 배선층 제조 방법.The formation of the oxide film, 30W in to RF power, pressure of 2.0Torr to 3.0Torr of 70W SiH 4, N 2 O, a metal wiring method for fabricating a semiconductor device formed by the N 2 supply. 제 3 항에 있어서,The method of claim 3, wherein 상기 SiH4의 공급량은 8sccm 내지 14sccm, 상기 N2O의 공급량은 300sccm 내지 400sccm, 상기 N2의 공급량은 4500sccm 내지 5400sccm인 것을 특징으로 하는 반도체 소자의 금속 배선층 제조 방법.The supply amount of SiH 4 is 8sccm to 14sccm, the supply amount of N 2 O is 300sccm to 400sccm, the supply amount of N 2 is 4500sccm to 5400sccm The method of manufacturing a metal wiring layer of a semiconductor device.
KR10-2003-0033616A 2003-05-27 2003-05-27 Method for manufacturing metal layer in semiconductor device KR100532748B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103646849A (en) * 2013-11-18 2014-03-19 武汉新芯集成电路制造有限公司 Novel process for reducing hillock-shaped defects produced on aluminum film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103646849A (en) * 2013-11-18 2014-03-19 武汉新芯集成电路制造有限公司 Novel process for reducing hillock-shaped defects produced on aluminum film

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