KR20040101175A - array panel for liquid crystal displays and manufacturing method of the same - Google Patents

Abstract

PURPOSE: An array substrate for a liquid crystal display, and a method for manufacturing the same are provided to prevent damage of gate electrodes in a process of activating source and drain areas by forming gate lines with a metal material and forming the gate electrodes with a silicon. CONSTITUTION: An active layer(121) is formed of a polycrystalline silicon material. Source and drain areas(122,123) are placed on both sides of the active layer, being doped with impurities. Data lines(161) are connected with the source area and are formed in first direction. Gate electrodes are formed of a polycrystalline silicon material, and each gate electrode is formed of a first electrode part(141) placed to be overlapped with the active layer area in a state of being insulated with the active layer, and a second electrode part(142) placed to be overlapped with the data lines in a state of being insulated with the data lines. Gate lines(165) are formed between the data lines in second direction crossing the first direction, and are connected with the second electrode part of the gate electrode at a crossing area of the data line and the gate line. Pixel electrodes(181) are connected with the drain electrode.

Description

Array substrate for liquid crystal display device and manufacturing method therefor {array panel for liquid crystal displays and manufacturing method of the same}

The present invention relates to an array substrate for a liquid crystal display device and a method for manufacturing the same, and more particularly, to an array substrate including a thin film transistor made of polycrystalline silicon and a method for manufacturing the same.

Recently, with the rapid development of the information society, there is a need for a flat panel display having excellent characteristics such as thinness, light weight, and low power consumption. It is excellent in color display and image quality, and is actively applied to notebooks and desktop monitors.

In general, a liquid crystal display device is formed by arranging two substrates on which electric field generating electrodes are formed so that the surfaces on which two electrodes are formed face each other, injecting a liquid crystal material between the two substrates, and then applying voltage to the two electrodes. By moving the liquid crystal molecules by an electric field, the device expresses an image by the transmittance of light that varies accordingly.

The lower substrate of the liquid crystal display includes a thin film transistor which is a switching element. In general, an active layer used in the thin film transistor is made of amorphous silicon (a-Si: H). This is because amorphous silicon can be formed on a large substrate such as a low cost glass substrate at low temperature.

On the other hand, recently, liquid crystal display devices employing thin film transistors using polycrystalline silicon (poly-Si) have been researched and developed. Since the polycrystalline silicon has a field effect mobility of about 100 to 200 times greater than that of amorphous silicon, the response speed is fast and the stability to temperature and light is excellent. In addition, there is an advantage that the driving circuit can be formed on the same substrate.

As a method of forming polycrystalline silicon, a laser annealing method of growing an amorphous silicon thin film by applying an excimer laser while heating the substrate temperature to about 250 ° C., and depositing a metal on the amorphous silicon to produce polycrystalline silicon as a seed The metal induced crystallization (MIC) method to be formed, the solid phase crystallization (SPC) method of forming amorphous silicon by heat treatment for a long time at high temperature, and the method of depositing polycrystalline silicon directly on a substrate.

Recently, a method of crystallizing by sequential lateral solidification (hereinafter referred to as SLS method) using a laser has been proposed and widely studied. In the SLS method, the grain of silicon is the interface between the silicon liquid region and the solid state region of the silicon. Is a method of increasing the size of silicon grain by lateral growth of grain by a predetermined length by appropriately shifting the size of laser energy and the irradiation range of the laser beam. to be.

Hereinafter, an array substrate including a thin film transistor using polycrystalline silicon and a method of manufacturing the same will be described with reference to the accompanying drawings.

1 is a plan view of a conventional array substrate for a liquid crystal display device, and FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1.

1 and 2, polycrystalline silicon layers 21, 22, and 23 having an island shape are formed on a substrate 10, which is an active layer 21 of a thin film transistor. ) And the doped source and drain regions 22 and 23.

Subsequently, a gate insulating film 30 and a gate electrode 42 are formed on the active layer 21, and the gate electrode 42 is connected to the gate wire 41 extending in the horizontal direction.

An interlayer insulating film 50 is formed on and covers the gate electrode 42 and the gate wiring 41, and the interlayer insulating film 50 first and second contacts exposing portions of the source and drain regions 22 and 23, respectively. It has holes 51 and 52.

The data line 61 and the drain electrode 63 including the source electrode 62 are formed of a conductive material such as a metal on the interlayer insulating layer 50. Here, the data line 61 extends in the vertical direction and intersects with the gate line 41 to define a pixel region, the source electrode 62 is formed as part of the data line 61, and the drain electrode 63 is a gate. The electrode 42 is facing the source electrode 62. The source and drain electrodes 62 and 63 are connected to the source and drain regions 22 and 23 through the contact holes 51 and 52, respectively.

Subsequently, a passivation layer 70 is formed over the entire surface of the substrate 10 to cover the data line 61 and the source and drain electrodes 62 and 63, and the passivation layer 70 is formed on the second contact hole 52. And a third contact hole 71 exposing the drain electrode 63 of.

A pixel electrode 81 made of a transparent conductive material is formed in the pixel area on the passivation layer 70 through the third contact hole 71 and formed of a transparent conductive material.

A method of manufacturing the array substrate for a liquid crystal display device will be described in detail with reference to FIGS. 3A to 3F. 3A to 3F correspond to a cross section taken along the line II-II of FIG. 1.

First, as shown in FIG. 3A, an island-type polycrystalline silicon layer 20 is formed on the substrate 10. Here, the polycrystalline silicon layer 20 may be formed using one of the aforementioned polycrystalline silicon forming methods.

Subsequently, as illustrated in FIG. 3B, an insulating film such as a silicon oxide film or a silicon nitride film and a metal layer are sequentially deposited, and then the metal layer and the insulating film are patterned to form a gate electrode 42 and a gate insulating film below the polycrystalline silicon layer 20. 30) respectively. Next, ion doping is performed on the polycrystalline silicon layer 20 exposed by the gate electrode 42. At this time, a gate wiring (not shown) is also formed when the gate electrode 42 is formed.

Next, as shown in FIG. 3C, the polycrystalline silicon layer after ion doping is divided into ion-doped source and drain regions 22 and 23 and an ion-doped active layer 21. Here, a process for activating the doped ions in the source and drain regions 22 and 23 is required, and generally, an annealing method is used.

Meanwhile, since the semiconductor structure of the source and drain regions 22 and 23 may change from polycrystalline to amorphous due to the ion doping energy in the ion doping of FIG. 3B, a process of restoring it to the polycrystalline state is also required.

However, when the general heat treatment method is used to restore the amorphous source and drain regions back to the polycrystalline state, a long time heat treatment must be performed at a high temperature, resulting in deformation of the substrate. Therefore, in order to solve this problem, heat treatment is performed using a laser.

In this manner, heat treatment using a laser may not only activate doped ions, but also restore the amorphous source and drain regions 22 and 23 to a polycrystalline state.

Next, as shown in FIG. 3D, an interlayer insulating film 50 is formed of a silicon oxide film or a silicon nitride film and patterned to expose the first and second contact holes 51 and 52 to expose the source and drain regions 22 and 23, respectively. ).

Subsequently, as shown in FIG. 3E, a material such as a metal is deposited and patterned to form source and drain electrodes 62 and 63. In this case, a data line (not shown) is also formed, and the source and drain electrodes 62 and 63 contact the source and drain regions 22 and 23 through the first and second contact holes 51 and 52, respectively. Do it.

Next, as shown in FIG. 3F, a third contact hole exposing the drain electrode 63 by forming and patterning the passivation layer 70 over the entire surface of the substrate 10 on which the source and drain electrodes 62 and 63 are formed. After the 71 is formed, the pixel electrode 81 is formed on the transparent conductive material thereon. In this case, the pixel electrode 81 is connected to the drain electrode 63 through the third contact hole 71.

Such a thin film transistor using polycrystalline silicon has a high field effect mobility and a fast response speed. When the polycrystalline silicon thin film transistor is used in a liquid crystal display device, a driving circuit can be formed on the same substrate, thus manufacturing process and cost of the liquid crystal display device. Can be reduced.

However, in manufacturing such a polycrystalline silicon thin film transistor, as described above, when the gate electrode and the gate wiring are formed of a metal material, the gate electrode may be damaged if the laser energy density is too large during the laser activation process of FIG. 3C. Can be. Therefore, the density of the laser energy is not increased to some extent. In this case, the source and drain regions 22 and 23 of FIG. 3C may not be completely melted, and thus the degree of activation may be lowered. In particular, since polycrystalline silicon has high thermal conductivity, heat loss is severe in the source and drain regions 22 and 23 adjacent to the active layer (21 in FIG. 3C), and the activation degree in this portion is further lowered.

In order to prevent such a problem, when the gate electrode and the gate wiring are formed of polycrystalline silicon, the activation of the source and drain regions can be increased by increasing the density of laser energy. However, since polycrystalline silicon has a larger resistivity than metal materials, problems such as signal delay may occur, which makes it difficult to apply to a display device having a large area.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to manufacture a polycrystalline silicon thin film transistor, and a liquid crystal display device capable of preventing damage to wiring during an activation process of a source and a drain region. The present invention provides an array substrate and a method of manufacturing the same.

Further, another object of the present invention relates to an array substrate for a liquid crystal display device and a method of manufacturing the same, in which the number of steps does not increase while improving the characteristics of the thin film transistor.

1 is a plan view showing a part of a conventional array substrate for a liquid crystal display device;

FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1. FIG.

3A to 3F are cross-sectional views illustrating a manufacturing process of a conventional array substrate for a liquid crystal display device.

4 is a plan view showing a part of an array substrate for a liquid crystal display device according to the present invention;

FIG. 5 is a cross-sectional view taken along the line VV of FIG. 4. FIG.

6A to 6G are plan views illustrating a manufacturing process of an array substrate for a liquid crystal display according to the present invention.

7A to 7G are cross-sectional views illustrating a manufacturing process of an array substrate for a liquid crystal display device according to the present invention.

In order to achieve the above object, the present invention provides an active layer comprising a polycrystalline silicon material on a substrate; An impurity doped source and drain region on both sides of the active layer in an integrated pattern with the active layer; A data line connected to the source region and formed in a first direction; A gate electrode made of a polycrystalline silicon material, comprising a first electrode portion positioned to overlap with the active layer region in an insulated state from the active layer, and a second electrode portion positioned overlapping in an insulated state from the data line. and; It is formed of the same material in the same process as the data line, and is formed in a pattern separated in the spaced apart area between the data lines in a second direction crossing the first direction, and in the cross region with the data line, A gate wiring connected to the two electrode portions; An array substrate for a liquid crystal display device including a pixel electrode connected to the drain region is provided.

In another aspect, the present invention provides a method for forming a polycrystalline silicon layer on a substrate, the method comprising: forming a polycrystalline silicon layer in island form using a polycrystalline silicon material; On a region exposing both sides of the polycrystalline silicon layer, a gate insulating film, a first electrode part made of amorphous silicon, positioned in a first direction, and a second located in a second direction crossing the first direction Sequentially forming a gate electrode composed of an electrode portion; By using the gate electrode as a mask, impurity treatment is performed on both exposed sides of the polycrystalline silicon layer to form the polycrystalline silicon layer as an active layer positioned corresponding to the gate electrode, and the source and drain regions treated with the impurity. Making a step; Activating the source and drain regions and crystallizing a gate electrode in the activation step; Forming a data line connected to the source region in the first direction, and having a pattern structure separated in the interval between the data lines in the second direction by using the same material as the data line; Forming a gate wiring connected to the second electrode portion; A method of manufacturing an array substrate for a liquid crystal display device, the method including forming a pixel electrode connected to the drain region.

As described above, in the present invention, in forming a thin film transistor using polycrystalline silicon as an active layer, the gate wiring is formed of a metal material and the gate electrode is formed of silicon, thereby preventing the gate electrode from being damaged during laser activation. The degree of activation of the source and drain regions can be improved.

In addition, since the gate wiring is made of a metal material, while preventing signal delay of the wiring, the gate wiring is formed when the data wiring is formed, so that a process is not added, thereby reducing manufacturing costs.

Hereinafter, an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings.

4 is a plan view of an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along the line VV of FIG. 4.

As shown in FIGS. 4 and 5, the active layer 121 and the source and drain regions 122 and 123 positioned on both sides of the active layer 121 of the thin film transistor made of island-shaped polycrystalline silicon are disposed on the substrate 110. Formed. Here, the source and drain regions 122 and 123 are doped with impurities.

A gate insulating film 130 made of a silicon oxide film or a silicon nitride film is formed on the active layer 121 of the thin film transistor, and gate electrodes 141 and 142 made of polycrystalline silicon are formed thereon. The gate electrodes 141 and 142 consist of a first electrode part 141 extending in the horizontal direction and a second electrode part 142 extending in the vertical direction to form a '-' shape. Although not shown, the gate insulating layer 130 is formed. ) Has the same shape as the gate electrodes 141 and 142.

Next, an interlayer insulating film 150 covering the gate electrodes 141 and 142 is formed thereon. Like the gate insulating layer 130, the interlayer insulating layer 150 may be formed of any one of a silicon oxide layer and a silicon nitride layer, and the first and second contact holes 151 and 152 exposing the source and drain regions 122 and 123, respectively. And a third contact hole 153 exposing both ends of the first electrode portion 141 of the gate electrode.

The data line 161 including the source electrode 162, the drain electrode 163, and the gate line 165 are formed of a conductive material such as a metal on the interlayer insulating layer 150. The data line 161 extends in the vertical direction to overlap the first electrode portion 141 of the gate electrode, and the source electrode 162 is formed as part of the data line 161 and is formed through the first contact hole 151. The drain electrode 163 is connected to the source region 122, and the drain electrode 163 is connected to the drain region 123 through the second contact hole 152. On the other hand, the gate wiring 165 extends in the horizontal direction and is positioned between the neighboring data wirings 161, and both ends thereof overlap with both ends of the first electrode portion 141 of the gate electrode, thereby forming the third contact hole 153. It is connected to the first electrode portion 141 of the gate electrode through. Here, the source electrode 162 may be part of the data line 161, but may extend from the data line 161, and the drain electrode 163 may be omitted.

Next, a protective layer 170 is formed over the entire surface of the substrate 110, and the protective layer 170 has a fourth contact hole 171 exposing the drain electrode 163.

A pixel electrode 181 made of a transparent conductive material is formed on the passivation layer 170. The pixel electrode 181 is positioned in a pixel area defined by the gate line 165 and the data line 161. It is connected to the drain electrode 163 through four contact holes 171.

As described above, in the present invention, the signal wiring of the wiring can be prevented by using the gate wiring as a metal material and only the gate electrode portion of the thin film transistor as polycrystalline silicon.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 6A to 6G and 7A to 7G. 6A to 6G are plan views illustrating the manufacturing process of the array substrate according to the present invention, and FIGS. 7A to 7G are cross-sectional views illustrating the manufacturing process of the array substrate according to the present invention, and FIGS. 6A to 6G, respectively. Fig. 1 shows a cross section taken along the lines VIIa-VIIa to VIIg-VIIg.

First, as shown in FIGS. 6A and 7A, a polycrystalline silicon layer 120 having an island shape is formed on the substrate 110.

As mentioned above, the polycrystalline silicon layer 120 may be formed in various ways. In particular, as the method of depositing and recrystallizing the amorphous silicon layer, the polycrystalline silicon layer 120 may be formed by a laser annealing method or an SLS method.

In this case, when the amorphous silicon layer is recrystallized into a polycrystalline silicon layer, alkali ions, for example, potassium ions (K +), sodium ions (Na +), etc. present in the substrate 110 may be generated by heat. In order to prevent the film quality of the polycrystalline silicon layer 120 from deteriorating, a buffer layer may be further formed between the substrate 110 and the polycrystalline silicon layer 120.

6B and 7B, an insulating film such as a silicon oxide film or a silicon nitride film is deposited, amorphous silicon is deposited thereon, and then the amorphous silicon and the insulating film are patterned to form the amorphous silicon on the polycrystalline silicon layer 120. The gate electrodes 141 and 142 and the gate insulating layer 130 are formed. Next, an impurity is implanted into the polycrystalline silicon layer 120 by ion doping the gate electrodes 141 and 142 using a mask. At this time, impurities are also implanted into the gate electrodes 141 and 142. Here, the gate electrodes 141 and 142 are formed of a first electrode portion 141 in the horizontal direction and a second electrode portion 142 in the vertical direction to have a '-' shape.

As such, the reason for the ion doping of the polycrystalline silicon layer 120 is to reduce the contact resistance between the source and drain electrodes and the polycrystalline silicon layer 120 to be formed in a later process, while providing electrical characteristics to the polycrystalline silicon layer 120. It is to give.

Ion doping uses elements of Groups 3 and 5, and an n-type semiconductor is formed when the Group 5 elements are doped in the source and drain regions 32 and 33, and a p-type semiconductor is formed when the Group 3 elements are doped.

As shown in FIGS. 6C and 7C, the doped polycrystalline silicon layer is divided into impurity regions 122 and 123 and intrinsic region 121. The doped polycrystalline silicon layer activates doped ions in the impurity regions 122 and 123 and is crystalline. In order to recover the laser beam, the laser beam is irradiated. Here, the impurity regions 122 and 123 become source and drain regions, respectively, and the intrinsic region 121 becomes an active layer of the thin film transistor.

In this process, the gate electrodes 141 and 142 made of amorphous silicon are crystallized by a laser to become polycrystalline silicon. In this case, in order to improve crystallinity of the gate electrodes 141 and 142, the laser beam irradiation may use an SLS crystallization method.

Next, as illustrated in FIGS. 6D and 7D, a silicon oxide film or a silicon nitride film is deposited to form an interlayer insulating film 150, and patterned to form first and second contacts exposing source and drain regions 122 and 123, respectively. Third contact holes 153 exposing both ends of the holes 151 and 152 and the first gate wiring 141 are formed.

6E and 7E, the metal layer is deposited and patterned to form the data line 161 including the source electrode 162, the drain electrode 163, and the gate line 165. In this case, the data line 161 extends in the vertical direction to intersect the first electrode portion 141 of the gate electrode, define a pixel region together with the gate line 165, and the source electrode 162 may have a first contact hole. The source region 122 is contacted through the 151, and the drain electrode 163 is in contact with the drain region 123 through the second contact hole 152. Meanwhile, the horizontal gate line 165 is positioned between two neighboring data lines 161, and both ends of the first electrode part 141 of the gate electrode overlap each other and are connected through the third contact hole 153. It is. Here, the drain electrode 163 may be omitted.

Next, as shown in FIGS. 6F and 7F, the passivation layer 170 is formed over the entire surface of the substrate 110 on which the source and drain electrodes 162 and 163 are formed, and then patterned to form the second contact hole 152. A fourth contact hole 171 exposing the upper drain electrode 163 is formed. The passivation layer 170 may use an organic insulating material having excellent flatness.

6G and 7G, the pixel electrode 181 is formed of a transparent conductive material such as indium-tin-oxide in the pixel area on the passivation layer 170. In this case, the pixel electrode 181 is in contact with the drain electrode 163 through the fourth contact hole 171.

As described above, in forming the thin film transistor including polycrystalline silicon as an active layer, the activation degree of the source and drain regions can be improved while preventing the gate electrode from being damaged, and no process is added.

The present invention is not limited to the above embodiments, and various changes and modifications can be made without departing from the spirit of the present invention.

In the array substrate for a liquid crystal display device according to the present invention, in forming a thin film transistor using polycrystalline silicon as an active layer, the gate wiring is formed of a metal material and the gate electrode is formed of silicon. This damage can be prevented, and by increasing the energy density of the laser beam, all source and drain regions can be melted to improve the degree of activation.

In addition, since the gate wiring is made of a metal material, while preventing signal delay of the wiring, the gate wiring is formed when the data wiring is formed, so that a process is not added, thereby reducing manufacturing costs.

Claims (16)

An active layer made of a polycrystalline silicon material on the substrate; An impurity doped source and drain region on both sides of the active layer in an integrated pattern with the active layer; A data line connected to the source region and formed in a first direction; A gate electrode made of a polycrystalline silicon material, comprising a first electrode portion positioned to overlap with the active layer region in an insulated state from the active layer, and a second electrode portion positioned overlapping in an insulated state from the data line. and; It is formed of the same material in the same process as the data line, and is formed in a pattern separated in the spaced apart area between the data lines in a second direction crossing the first direction, and in the cross region with the data line, A gate wiring connected to the two electrode portions; A pixel electrode connected to the drain region Array substrate for a liquid crystal display device comprising a. The method of claim 1, And the gate electrode is on a lower layer of the source electrode and the data line. The method of claim 2, And a gate insulating layer disposed between the active layer and the gate electrode. The method of claim 1, And the gate electrode is deposited using an amorphous silicon material and crystallized through activation of the source and drain regions. The method of claim 1, And an interlayer insulating layer having first and third contact holes respectively exposing the source and drain regions and the gate electrode in a region covering the gate electrode. The method of claim 5, wherein And a protective layer having a fourth contact hole at a position corresponding to a second contact hole exposing the drain region partially, in a region covering the data line. The method according to any one of claims 5 to 6, The source region and the data wiring are connected through the first contact hole, the drain region and the pixel electrode are connected through the second and fourth contact holes, and the gate electrode and the gate wiring are connected through the third contact hole. The array substrate for liquid crystal display device connected to this. The method of claim 7, wherein And the third contact holes are located at both sides of the first electrode portion of the gate electrode, respectively. The method of claim 1, And the drain region and the pixel electrode are connected to each other by a drain electrode made of the same material as that of the data line. The method of claim 1, And a source electrode substantially connected to the source region in the data line. The method of claim 9, And the fourth contact hole is a contact hole exposing the drain electrode. Forming an island-shaped polycrystalline silicon layer on the substrate using a polycrystalline silicon material; On a region exposing both sides of the polycrystalline silicon layer, a gate insulating film, a first electrode part made of amorphous silicon, positioned in a first direction, and a second located in a second direction crossing the first direction Sequentially forming a gate electrode composed of an electrode portion; By using the gate electrode as a mask, impurity treatment is performed on both exposed sides of the polycrystalline silicon layer to form the polycrystalline silicon layer as an active layer positioned corresponding to the gate electrode, and the source and drain regions treated with the impurity. Making a step; Activating the source and drain regions and crystallizing a gate electrode in the activation step; Forming a data line connected to the source region in the first direction, and having a pattern structure separated in the interval between the data lines in the second direction by using the same material as the data line; Forming a gate wiring connected to the second electrode portion; Forming a pixel electrode connected to the drain region Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 12, Between the forming of the gate electrode and the forming of the data line and the gate line, first and second contact holes covering the gate electrode and exposing the source and drain regions, respectively, and exposing a portion of the gate electrode are exposed. A method of manufacturing an array substrate for a liquid crystal display device comprising forming an interlayer insulating film having a third contact hole. The method of claim 13, Between the forming of the gate wiring and the data wiring and forming the pixel electrode, a protective layer covering the gate wiring and the data wiring and having a fourth contact hole at a position corresponding to the second contact hole is formed. A method of manufacturing an array substrate for a liquid crystal display device comprising the step of. The method of claim 12, The impurity treatment step is performed by an ion implantation method, and the activation step is a step of activating the ions. The method according to any one of claims 12 to 15, The activation step is a method of manufacturing an array substrate for a liquid crystal display device using a laser.