KR101021693B1 - Liquid crystal display panel and method for fabricating thereof - Google Patents

Abstract

The liquid crystal display panel of the present invention is to reduce the resistance of the signal wiring without increasing the parasitic capacitance in the liquid crystal display panel integrated with the driving circuit by forming a dummy pattern with respect to the parallel signal wiring, divided into a pixel portion and a driving circuit portion An array substrate; A switching element formed in the pixel portion of the array substrate; A plurality of signal wires formed in a driving circuit portion of the array substrate; A plurality of dummy patterns formed in an insulating film under each of the signal wires and electrically connected to the signal wires; A plurality of driving circuit elements receiving signals from an external signal input terminal through the signal wires; And a color filter substrate bonded to the array substrate, wherein the plurality of dummy patterns are arranged to be staggered between neighboring signal lines in order to reduce coupling capacitance between dummy patterns of neighboring signal lines.

Liquid crystal display panel with integrated driving circuit, signal wiring, dummy pattern

Description

Liquid crystal display panel and its manufacturing method {LIQUID CRYSTAL DISPLAY PANEL AND METHOD FOR FABRICATING THEREOF}

1 is a plan view schematically illustrating a structure of a general liquid crystal display panel.

FIG. 2A is a plan view schematically illustrating signal wiring formed in a driving circuit unit of the liquid crystal display panel shown in FIG. 1; FIG.

FIG. 2B is a view showing a cross section taken along the line II-II 'of the signal wiring shown in FIG. 2A; FIG.

3 is an exemplary view schematically showing signal wiring according to an embodiment of the present invention.

4A and 4B are exemplary views showing cross sections taken along lines IIIa-IIIa 'and IIIb-IIIb' of the signal wiring shown in FIG.

5A to 5E are exemplary views sequentially illustrating a manufacturing process of a signal wiring according to an embodiment of the present invention.

DESCRIPTION OF REFERENCE NUMERALS

110: array substrate 115A to 115C: insulating film

150: signal wiring 155: dummy pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel and a method of manufacturing the same, and more particularly, to a driving circuit enabling a large area liquid crystal display panel by reducing wiring resistance without increasing coupling capacitance of signal wiring. An integrated liquid crystal display panel and a method of manufacturing the same.

Recently, with increasing interest in information display and increasing demand for using a portable information carrier, a lightweight flat panel display (FPD), which replaces a conventional display device, a cathode ray tube (CRT), is used. The research and commercialization of Korea is focused on. In particular, the liquid crystal display (LCD) of the flat panel display device is an image representing the image using the optical anisotropy of the liquid crystal, is excellent in resolution, color display and image quality, and is actively applied to notebooks or desktop monitors have.

The liquid crystal display is largely composed of a color filter substrate as a first substrate, an array substrate as a second substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

In this case, a thin film transistor (TFT) is generally used as a switching element of the liquid crystal display, and amorphous silicon or polycrystalline silicon is used as a channel layer of the thin film transistor. .

Hereinafter, a liquid crystal display will be described in detail with reference to FIG. 1.                         

1 is a plan view schematically illustrating a structure of a general liquid crystal display panel, and illustrates a driving circuit-integrated liquid crystal display device in which a driving circuit unit is integrated on an array substrate.

As shown in the drawing, the driving circuit-integrated liquid crystal display panel 5 has a large liquid crystal layer formed between the array substrate 10 and the color filter substrate 20 and the array substrate 10 and the color filter substrate 20. Not shown).

The array substrate 10 includes a pixel portion 35, which is an image display area in which unit pixels are arranged in a matrix form, a gate driving circuit portion 34 and a data driving circuit portion 33 positioned outside the pixel portion 35. It consists of a driving circuit part.

In this case, although not shown in the drawings, the pixel units 35 of the array substrate 10 are arranged horizontally and horizontally on the substrate 10 to define a plurality of gate lines and data lines, and the gate lines and data. A thin film transistor, which is a switching element formed in an intersection region of a line, and a pixel electrode formed in the pixel region.

The thin film transistor is a switching element that applies and cuts off a signal voltage to a pixel electrode and is a type of field effect transistor (FET) that controls the flow of current by an electric field.

In the driving circuit units 33 and 34 of the array substrate 10, the data driving circuit unit 33 is positioned at one long side of the array substrate 10 protruding from the color filter substrate 20. The gate driving circuit unit 34 is positioned at one end side of the array substrate 10.

In this case, the gate driving circuit part 34 and the data driving circuit part 33 use a thin film transistor having a complementary metal oxide semiconductor (CMOS) structure as an inverter to properly output the input signal.

For reference, the CMOS is an integrated circuit having a MOS structure which is used for a thin film transistor of a driving circuit unit requiring high speed signal processing, and requires a transistor of a P channel and an N channel, and the characteristics of speed and density are intermediate between NMOS and PMOS. It shows form.

The gate driving circuit unit 34 and the data driving circuit unit 33 are devices for supplying scan signals and data signals to pixel electrodes through gate lines and data lines, respectively, and are connected to an external signal input terminal (not shown). It controls the external signal input through the external signal input terminal to output to the pixel electrode.

In addition, although not shown in the drawing, an image display area 35 of the color filter substrate 20 includes a color filter for implementing color and a common electrode that is opposite to the pixel electrode formed on the array substrate 10.

As described above, the liquid crystal display panel configured as described above requires a plurality of signal wires to transfer signals from the external signal input terminal to each element of the driving circuit unit, which is generally disposed outside the driving circuit unit. In implementing a system on panel (SOP) using transistors, it is essential to reduce the area occupied by the signal wires and to reduce the resistance of the signal wires in order to form more circuits.

Hereinafter, the signal wiring will be described in detail with reference to the drawings.

FIG. 2A is a plan view schematically illustrating signal wires formed in a driving circuit unit of the liquid crystal display panel illustrated in FIG. 1, and FIG. 2B is a cross-sectional view taken along line II-II ′ of the signal wires illustrated in FIG. 2A.

In this case, the signal wires are arranged in the same direction and at the same interval for convenience of description.

As shown in the figure, the first insulating film 15A and the second insulating film 15B are formed on the array substrate 10, and the signal wiring 50 is equidistantly spaced on the second insulating film 15B. Are arranged in parallel.

The signal line 50 is generally disposed outside the driving circuit part using the same metal material as that of the data line (not shown).

In this case, a low RC value is required for suppressing signal delay, and in particular, a resistance of a wiring is required to be small. This requires a basic approach to increase the wiring width or increase the thickness of the wiring, but the former has a disadvantage that affects the increase of the circuit area, which is difficult to implement, and the latter is thick, which may cause integration problems. Can be.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problem, and includes a driving circuit-integrated liquid crystal display panel which can cope with the implementation of a large-area liquid crystal display panel by reducing wiring resistance without increasing the coupling capacitance with respect to the signal wiring of the driving circuit unit. It is an object to provide a method of manufacturing the same.

Other objects and features of the present invention will be described in the configuration and claims of the invention to be described later.

In order to achieve the above object, the liquid crystal display panel of the present invention comprises an array substrate divided into a pixel portion and a driving circuit portion; A switching element formed in the pixel portion of the array substrate; A plurality of signal wires formed in a driving circuit portion of the array substrate; A plurality of dummy patterns formed in an insulating film under each of the signal wires and electrically connected to the signal wires; A plurality of driving circuit elements receiving signals from an external signal input terminal through the signal wires; And a color filter substrate bonded to the array substrate, wherein the plurality of dummy patterns are arranged to be staggered between neighboring signal lines in order to reduce coupling capacitance between dummy patterns of neighboring signal lines.

In addition, the manufacturing method of the liquid crystal display panel of the present invention comprises the steps of providing an array substrate divided into a pixel portion and a driving circuit portion; Forming an active layer divided into a source / drain region and a channel region on the array substrate; Forming a first insulating film on the active layer; Forming a gate electrode on the channel region over the first insulating layer; Forming a second insulating film on an entire surface of the array substrate including the gate electrode; Patterning the second insulating film and the first insulating film to form a first contact hole and a second contact hole exposing the source / drain regions in a pixel portion of the array substrate, and a plurality of bars in a driving circuit portion of the array substrate. Forming a hole in the form; A plurality of source electrodes formed on the second insulating layer to form a source electrode connected to the source region through the first contact hole, a drain electrode connected to the drain region through the second contact hole, and filling the plurality of holes Forming a dummy pattern and a plurality of signal wires electrically connected to the plurality of dummy patterns thereon; And bonding the array substrate and the color filter substrate.

Hereinafter, exemplary embodiments of a driving circuit-integrated liquid crystal display panel and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

3 is an exemplary view schematically showing signal wiring according to an embodiment of the present invention.

As shown in the figure, a bar pattern dummy pattern 155 is formed under each signal line 150 in order to implement a large area liquid crystal display panel integrated with a driving circuit.

 The dummy pattern 155 is electrically connected to the upper signal line 150 and a coupling capacitance between adjacent wirings (that is, the signal line 150 or the dummy pattern 155) according to the formation of the dummy pattern 155. The dummy bar patterns 155 are alternately arranged for each wire in order to reduce the number of wirings.

The dummy patterns 155 formed under the respective signal wires 150 are formed such that neighboring dummy patterns 155 do not overlap each other (that is, not disposed at the same position under the signal wires 150). Since the value of D is minimized, the dummy pattern 155 may be electrically connected to the upper signal line 150 to reduce the resistance due to the increase in the thickness of the wires 150 and 155.

That is, the resistance component is reduced by increasing the thickness of the signal wire 150, and as shown, the reason for disposing the dummy pattern 155 with respect to the adjacent wire 150 is adjacent to the adjacent wire due to the increase in the effective thickness. This is to reduce the coupling capacity between 150 and 155).

By forming in this way, the wiring resistance can be reduced only by the thickness of the existing wiring 150 without increasing the parasitic capacitance, thereby reducing the RC delay of the wiring, and in the case of the arrangement having the same RC delay, the wiring width can be reduced. The area can be reduced. In addition, the dummy pattern 155 does not need to be separated in the case where the increase in the coupling capacity according to the increase in thickness is allowed.

In this case, the dummy pattern 155 is arranged to be alternately arranged one by one with respect to the signal line 150 in a bar shape having a predetermined length, for example, but the present invention is not limited thereto and the adjacent signal line ( The present invention is applied in any case where the dummy patterns 155 are alternated between 150 to reduce the resistance of the wiring. In this case, in order to minimize the coupling capacitance and have the same value, the dummy pattern 155 may be arranged in the same shape with respect to each signal line 150.

That is, for example, the dummy pattern 155 having the shape as shown in the figure may be arranged in the same staggered form as the two embodiments.

In addition, the present exemplary embodiment illustrates a case in which the dummy pattern 155 is formed to have a smaller width than the signal wiring 150 thereon, but the present invention is not limited thereto. The width of the signal wire 150 may be equal to or larger than that of the signal wire 150.

4A and 4B are exemplary views showing cross sections taken along lines IIIa-IIIa 'and IIIb-IIIb' of the signal wiring shown in FIG. 3.

As shown in the drawing, the first insulating film 115A and the second insulating film 115B are formed on the array substrate 110, and the signal wiring 150 is disposed on the second insulating film 115B.

In this case, a dummy pattern 155 in a line form is disposed under the signal wire 150 to be alternated for each wire, and the signal wire 150 and the dummy pattern 155 are the same as the data line (not shown). The metal material may be disposed outside the driving circuit unit.

The dummy pattern 155 selectively etches the first insulating film 115A and the second insulating film 115B under the signal line 150 when the source / drain contact is opened, and then, when the data metal is deposited. The region may be formed in such a manner that the region is filled, which will be described in detail through the following manufacturing process.

5A through 5E are exemplary views sequentially illustrating a manufacturing process of a signal line according to an exemplary embodiment of the present invention. For convenience of description, the left side shows a process of forming a thin film transistor in a pixel portion of an array substrate. The process of forming a signal wiring in the signal wiring part of a board | substrate is shown.

In this case, the signal wiring portion refers to an outer region of the driving circuit portion in which the signal wiring is disposed.

The thin film transistor is a type of field effect transistor and includes a source region supplying electrons or holes, a channel region through which the electrons or holes pass, and a drain region through which electrons or holes pass through the channel.                     

At this time, there is a gate region that is electrically insulated on the channel but controls the flow of electrons or holes by changing the potential of the channel at a distance very close to the channel. Since a method of controlling the flow of electrons or holes in the channel through the gate region uses an electric field formed by a voltage applied to the gate region, such a structure is called a field effect transistor.

In addition, although only the manufacturing process of the thin film transistor of the pixel portion is shown in the drawings for convenience of description, the present embodiment may be applied to the liquid crystal display panel integrated with the driving circuit portion, so that the N-type and P-type thin film transistors are formed in the driving circuit portion through a similar process. do.

As shown in FIG. 5A, an active layer 124 to be used as a channel layer is formed by patterning a pixel portion of a substrate 110 made of a transparent insulating material such as glass through a photolithography process.

In this case, after forming a buffer layer formed of a silicon oxide film (SiO ₂ ) on the substrate 110, an active layer 124 may be formed on the buffer layer. The buffer layer serves to block impurities such as sodium (natrium) from the glass substrate 110 from penetrating into the upper layer during the process.

The active layer 124 may be formed of an amorphous silicon thin film or a crystallized silicon thin film. However, in the present embodiment, a thin film transistor is formed using the crystallized silicon thin film. The polycrystalline silicon thin film may be formed using various crystallization methods after depositing an amorphous silicon thin film on the substrate 110. This will be described below.

First, an amorphous silicon thin film may be formed by depositing in various ways. Representative methods of depositing the amorphous silicon thin film include a low pressure chemical vapor deposition (LPCVD) method and a plasma chemical vapor deposition (Plasma Enhanced). Chemical Vapor Deposition (PECVD) method.

Subsequently, crystallization is performed after a dehydrogenation process for removing hydrogen atoms present in the amorphous silicon thin film. At this time, as a method of crystallizing an amorphous silicon thin film, a solid phase crystallization (SPC) method for thermally treating an amorphous silicon thin film in a high temperature furnace and an excimer laser annealing method using a laser are employed. have.

On the other hand, as the laser crystallization, an excimer laser annealing method using a pulse-type laser is mainly used. In recent years, sequential horizontal crystallization (SLS), which greatly improves crystallization characteristics by growing grain in the horizontal direction, has been performed. The method has been proposed and widely studied.

The sequential horizontal crystallization takes advantage of the fact that grain grows in a direction perpendicular to the interface at the interface between the liquid phase silicon and the solid phase silicon, and appropriately controls the size of the laser energy and the irradiation range of the laser beam. It is a crystallization method that can improve the size of the silicon grain by controlling the side growth of the grain by a predetermined length.                     

Next, as shown in FIGS. 5B and 5C, after the first insulating film 115A, which is a gate insulating film, is formed on the entire surface of the substrate 110, a conductive metal material is formed on the first insulating film 115A of the pixel portion. The gate electrode 121 is formed. In this case, the gate electrode 121 is formed of aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), chromium (Cr), molybdenum (molybdenum) on the first insulating layer 115A. After depositing a conductive metal material such as Mo), it can be formed by patterning the conductive metal material using a photolithography process.

In addition, a high concentration of impurity ions are implanted into a predetermined region of the active layer 124 to form a source region 124A and a drain region 124B, which are ohmic contact layers.

Field effect transistors are largely divided into N-type and P-type according to the type of carrier through which current flows, and the electrons and holes become carriers through which current flows, respectively. In the case of an N-type transistor, the source / drain regions 124A and 124B are implanted with phosphorus (P) or arsenic (As) to form an N-type. In the case of a P-type transistor, the source / drain regions 124A and 124B are used. ) Is used by injecting boron (B) or BF ₂ to form a P-type. This process of adding phosphorus, arsenic, boron, etc. to silicon is called doping, which physically changes the work function of silicon.

In this case, the gate electrode 121 serves as an ion stopper that prevents the dopant from penetrating into the channel region 124C of the active layer 124.

In the present embodiment, for example, a manufacturing process of a thin film transistor in the case where no lightly doped drain (LDD) region is formed between the channel region 124C and the source / drain regions 124A and 124B will be described. However, the present invention is not limited thereto, and an LED region is additionally formed by injecting a low concentration of impurity ions into the active layer 124 before or after forming the source / drain regions 124A and 124B as described above. It may be formed.

Next, as shown in FIG. 5D, the second insulating film 115B is deposited on the entire surface of the substrate 110, and then the second insulating film 115B and the first insulating film 115A of the pixel portion are formed through a photolithography process. The first contact hole 140A and the second contact hole 140B exposing a portion of the source region 124A and the drain region 124C are removed to form a portion of the second region, and the second insulating layer ( A plurality of holes 140C are formed by removing some regions of the 115B and the first insulating film 115A.

At this time, the hole 140C is filled with a preliminary space for forming a dummy pattern, which will be described later, at the time of data metal deposition, and is electrically connected to the signal line.

In addition, the holes 140C may be alternately formed so that the dummy patterns are alternately formed for each wire. In the present embodiment, the holes 140C are formed by adjusting the width of the hole 140C so that the dummy patterns are narrower than the signal wires. can do.

Subsequently, as illustrated in FIG. 5E, a conductive metal material is deposited on the entire surface of the substrate 110, and then patterned by using a photolithography process to form the first contact hole 140A in the pixel portion of the array substrate 110. A source electrode 122 connected to the source region 124A and a drain electrode 123 connected to the drain region 124B are formed through the second contact hole 140B.

At the same time, in the signal wiring portion of the array substrate 110, the conductive metal material is filled in the hole 140C and then patterned together when the source / drain electrodes 122 and 123 are patterned to connect the plurality of signal wires 150. To form.

The signal wire 150 is electrically connected to the dummy pattern 155 filled with the conductive metal material in the hole 140C, thereby obtaining the same effect as the thickness of the wires 150 and 155 is increased. The resistance of the signal wire 150 is reduced.

As described above, the dummy pattern 155 for reducing the resistance of the signal wire 150 is formed at the same time in the form of a line in the process of forming the contact hole, and thus is formed in the form of being filled during data metal deposition. There is this.

Next, although not shown in the drawing, an organic film such as benzocyclobutene (BCB) or photo acryl may be disposed on the entire surface of the substrate 110 including the source electrode 122 and the drain electrode 123. After the third insulating layer is formed, a second contact hole exposing a portion of the drain electrode may be formed by removing a portion of the third insulating layer through a photolithography process.

In this case, the third insulating film may be formed of an inorganic insulating film such as a silicon oxide film or a silicon nitride film (SiN _x ), or may be formed of a double layer of an organic insulating film and an inorganic insulating film.

Thereafter, a transparent conductive material having excellent transmittance, such as indium tin oxide (ITO) or indium zinc oxide (IZO), is deposited on the entire surface of the substrate 110, followed by a photolithography process. The pixel electrode may be formed to be electrically connected to the drain electrode 123 through the second contact hole.

On the other hand, the array substrate formed through the process as described above is provided with a cell gap (cell gap) to be uniformly spaced by the spacer (spacer) and the color filter substrate produced by a different color filter process than the array process, The liquid crystal display panel may be bonded to each other by a seal pattern formed on an outer side of the array substrate to form a unit liquid crystal display panel.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

As described above, the driving circuit-integrated liquid crystal display panel and the method of manufacturing the same according to the present invention can enable low resistance signal wiring without additional processing, reduce the RC delay and reduce the line width of the wiring itself. This has the advantage that can be applied to high-definition, large area wiring through this.

Claims (11)

An array substrate divided into a pixel portion and a driving circuit portion; A switching element formed in the pixel portion of the array substrate; A plurality of signal wires formed in a driving circuit portion of the array substrate; A plurality of dummy patterns formed in an insulating film under each of the signal wires and electrically connected to the signal wires; A plurality of driving circuit elements receiving signals from an external signal input terminal through the signal wires; And And a color filter substrate bonded to the array substrate, wherein the plurality of dummy patterns are arranged to be staggered between neighboring signal lines to reduce coupling capacitance between the dummy pattern of neighboring signal lines. . delete The liquid crystal display panel of claim 1, wherein the elements of the pixel portion and the driving circuit portion of the array substrate are formed of a thin film transistor. The thin film transistor of claim 3, wherein the thin film transistor An active layer formed on the array substrate and divided into a source / drain region and a channel region; A first insulating film formed on the active layer; A gate electrode formed over the channel region on the first insulating layer; A second insulating layer formed on the substrate including the gate electrode and including a first contact hole and a second contact hole exposing a portion of the source / drain region; And And a source electrode formed on the second insulating layer and electrically connected to the source region through the first contact hole, and a drain electrode electrically connected to the drain region through the second contact hole. . The liquid crystal display panel of claim 4, wherein the dummy pattern is made of the same conductive metal material as the source / drain electrodes. The liquid crystal display panel of claim 4, wherein the signal line is made of the same conductive metal material as the source / drain electrodes. The liquid crystal display panel of claim 1, wherein the signal line is electrically connected to the dummy pattern to increase thickness by the dummy pattern, thereby reducing its resistance. Providing an array substrate divided into a pixel portion and a driving circuit portion; Forming an active layer divided into a source / drain region and a channel region on the array substrate; Forming a first insulating film on the active layer; Forming a gate electrode on the channel region over the first insulating layer; Forming a second insulating film on an entire surface of the array substrate including the gate electrode; Patterning the second insulating film and the first insulating film to form a first contact hole and a second contact hole exposing the source / drain regions in a pixel portion of the array substrate, and a plurality of bars in a driving circuit portion of the array substrate. Forming a hole in the form; A plurality of source electrodes formed on the second insulating layer to form a source electrode connected to the source region through the first contact hole, a drain electrode connected to the drain region through the second contact hole, and filling the plurality of holes Forming a dummy pattern and a plurality of signal wires electrically connected to the plurality of dummy patterns thereon; And And attaching the array substrate and the color filter substrate to each other. 10. The method of claim 8, wherein the dummy pattern is formed by filling the same conductive metal material as that of the source / drain electrodes in the holes formed in the second insulating film and the first insulating film. The method of claim 8, wherein the plurality of dummy patterns are alternately formed between neighboring signal lines to reduce coupling capacitance between the dummy pattern of neighboring signal lines. The method of claim 8, wherein the dummy pattern is disposed under each signal line at equal intervals.

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