KR20040100624A - Method for manufacturing isolation in semiconductor device - Google Patents
Method for manufacturing isolation in semiconductor device Download PDFInfo
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- KR20040100624A KR20040100624A KR1020030033040A KR20030033040A KR20040100624A KR 20040100624 A KR20040100624 A KR 20040100624A KR 1020030033040 A KR1020030033040 A KR 1020030033040A KR 20030033040 A KR20030033040 A KR 20030033040A KR 20040100624 A KR20040100624 A KR 20040100624A
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- 238000000034 method Methods 0.000 title claims abstract description 69
- 238000002955 isolation Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title 1
- 150000004767 nitrides Chemical class 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 21
- 239000010703 silicon Substances 0.000 claims abstract description 21
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 14
- 125000006850 spacer group Chemical group 0.000 claims abstract description 13
- 238000001039 wet etching Methods 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 230000003647 oxidation Effects 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 7
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000004140 cleaning Methods 0.000 description 5
- 230000003628 erosive effect Effects 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
- H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Chemical Kinetics & Catalysis (AREA)
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Abstract
Description
본 발명은 반도체 소자의 소자 분리막 형성 방법에 관한 것으로, 보다 상세하게는 필드 산화막의 손실에 의한 모트 발생으로 나타나는 험프 현상을 방지함으로써 소자의 동작의 신뢰성을 확보할 수 있도록 하는 반도체 소자의 소자 분리막 형성 방법에 관한 것이다.The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to forming a device isolation film of a semiconductor device to prevent the hump phenomenon caused by the generation of a mott caused by the loss of the field oxide film to ensure the reliability of the device operation. It is about a method.
소자 분리 공정은 크게 반도체 기판에 패드 산화막과 질화막을 형성한 후 마스크 공정으로 질화막을 식각하고 그 식각된 부위에 산화 공정을 진행하여 소자분리막을 형성하는 LOCOS(Local Oxidation of Silicon) 공정과, 반도체 기판에 일정한 깊이를 갖는 트렌치를 형성하고 나서 이 트렌치에 산화 물질을 증착시키고 CMP 공정을 통해 산화막의 불필요한 부분을 식각하여 소자 분리막을 형성하는 STI(Shallow Trench Isolation) 공정이 있다.The device isolation process includes a LOCOS (Local Oxidation of Silicon) process in which a pad oxide film and a nitride film are formed on a semiconductor substrate, and then the nitride film is etched by a mask process and an oxidation process is performed on the etched portion to form a device isolation film. There is a shallow trench isolation (STI) process in which a trench having a constant depth is formed in the trench, and an oxide material is deposited in the trench, and an unnecessary portion of the oxide layer is etched through the CMP process to form an isolation layer.
LOCOS 공정은 장시간 고온 산화로 인하여 채널저지 이온의 측면 확산 및 측면 산화에 의해 소자의 전기적인 특성을 저하시키는 원인으로 작용하는 버즈 빅(Bird's Beak)이 발생하여 약 0.25㎛ 이하의 공정에는 한계가 있다. 또한 소자 분리막의 깊이를 늘릴때는 과도한 스트레스가 발생하고 평탄성이 좋지 않아 특성을 저하시키는 문제점을 갖고 있다.The LOCOS process has a limitation in the process of about 0.25 μm or less due to the occurrence of Bird's Beak, which acts as a cause of deterioration of the electrical characteristics of the device due to side diffusion and lateral oxidation of channel blocking ions due to prolonged high temperature oxidation. . In addition, when the depth of the device isolation layer is increased, there is a problem that excessive stress occurs and flatness is not good, thereby deteriorating characteristics.
LOCOS의 이러한 문제점을 해결하기 위해 현재 0.25㎛ 이하의 미세 공정에서는 소자 분리 형성 방법으로 STI(Shallow Trench Isolation) 공정이 많이 사용되고 있다. 다면 상기 STI 공정 적용시에는 LOCOS의 단점인 버즈 빅은 발생하지 않고 절연 특성이 우수하지만, 탑 코너(Top Corner) 및 바텀 코너(Bottom Coener)에 스트레스가 집중되어 소자 특성이 저하되는 문제점이 있다.In order to solve this problem of LOCOS, the Shtre Trench Isolation (STI) process is widely used as a device isolation method in the micro process of 0.25 μm or less. When the STI process is applied, the Buzz big, which is a disadvantage of LOCOS, does not occur and the insulation property is excellent, but stress is concentrated on the top corner and the bottom corner, resulting in a deterioration of device characteristics.
또한, 트렌치의 탑코너에서의 에지 모트의 발생으로 소자의 비정상적 동작을 유발하는 험프(HUMP), INWE 현상이 발생하는데 험프 현상은 액티브 코너에서 전기장의 집중으로 인해 생기는 현상이고, INWE(Inverse Narrow Width Effect)는 트랜지스터의 폭이 감소함에 따라 문턱 전압이 변화하는 현상이다.In addition, Hump and INWE, which causes abnormal operation of the device, are caused by the generation of edge mortise in the top corner of the trench. Effect) is a phenomenon in which the threshold voltage changes as the width of the transistor decreases.
이에 따라 현재 코너 라운딩을 개선하는 방안으로 STI (Shallow Trench Isolation) 식각시 탑 코너 라운딩을 하거나 CMP 후에 HDP 산화막의 밀도를 증가시키기 위한 어닐 공정을 통한 코너 라운딩 방법 등이 이용되고 있으나, 이러한 방법에 의해서도 STI의 탑코너에서 발생하는 에지 모트(Edge Moat)를 억제할 수 없는 문제점이 있었다.Accordingly, the corner rounding method through an annealing process to improve the top corner rounding during shallow trench isolation (STI) etching or to increase the density of the HDP oxide layer after CMP has been used as a method for improving corner rounding. There was a problem in that edge moat generated at the top corner of STI could not be suppressed.
이하 예시된 도면을 참조하여 종래 기술에 의한 반도체 소자의 소자 분리막 형성 방법의 문제점을 설명하면 다음과 같다.Hereinafter, a problem of the device isolation film forming method of a semiconductor device according to the prior art will be described with reference to the illustrated drawings.
도 1a 내지 1f는 종래 기술에 의한 반도체 소자의 소자 분리막 형성 공정을 도시한 단면도들이다.1A to 1F are cross-sectional views illustrating a device isolation film forming process of a semiconductor device according to the prior art.
먼저, 도 1a에 도시한 바와 같이, 후속 공정에서의 증착되는 막과 실리콘 기판(100)과의 완충막 역할을 하는 패드 산화막(101)을 실리콘 기판(100) 상에 증착한 후, 그 상부에 패드 질화막(102)을 증착한다.First, as shown in FIG. 1A, a pad oxide film 101 serving as a buffer film between a film to be deposited in a subsequent process and a silicon substrate 100 is deposited on the silicon substrate 100, and then on top thereof. The pad nitride film 102 is deposited.
이어서, 도 1b에 도시한 바와 같이, 트렌치 식각용 하드 마스크 패턴을 형성하기 위하여 패드 질화막(102) 상부에 포토레지스트(103)를 도포한 후, 패터닝 공정을 실시한다. 그리고 나서, CHF3/CF4/O2/Ar 가스의 조합으로 활성화된 플라즈마를이용하여 패드 질화막(102)을 건식 식각한다. 그리고 나서, 패터닝된 패드 질화막(102)을 하드 마스크로 이용하여 실리콘 기판(100)에 대한 식각을 진행하여, 실리콘 기판(100) 내의 소정 영역에 트렌치(A)를 형성한다. 이때, STI 건식 식각은 Cl2/O2/Ar 가스의 조합으로 활성화된 플라즈마로 건식 식각을 진행한다.Subsequently, as shown in FIG. 1B, the photoresist 103 is coated on the pad nitride film 102 to form a hard mask pattern for trench etching, and then a patterning process is performed. Then, the pad nitride film 102 is dry-etched using the plasma activated by the combination of CHF 3 / CF 4 / O 2 / Ar gas. Thereafter, the silicon substrate 100 is etched using the patterned pad nitride film 102 as a hard mask to form a trench A in a predetermined region of the silicon substrate 100. In this case, the STI dry etching is performed by dry etching with a plasma activated by a combination of Cl 2 / O 2 / Ar gas.
상기 트렌치(A)를 형성한 후에 도 1c에 도시한 바와 같이, 포토레지스트(103)를 제거하고 트렌치(A) 내부가 충분히 매립되도록 필드 산화막(104)을 증착한 다. 이때, 상기의 필드 산화막(104)은 갭필링 특성이 좋은 물질을 이용하되, 바람직하게는 화학 기상 증착법(high density plasma chemical vapoer deposition; HDP CVD)을 이용한 HDP 산화막을 이용한다.After forming the trench A, as shown in FIG. 1C, the photoresist 103 is removed and a field oxide film 104 is deposited so that the inside of the trench A is sufficiently filled. In this case, the field oxide film 104 may be formed of a material having good gap peeling characteristics, and preferably, an HDP oxide film using high density plasma chemical vapoer deposition (HDP CVD).
다음 단계로, 도 1d에 도시한 바와 같이, 트렌치(A) 내부에 매립된 상기 필드 산화막(104)에 대하여 상기 패드 질화막(102)을 정지막으로 이용한 화학적 기계적 연마(chemical mechanical polishing; CMP)를 통하여 평탄화를 시킨다.Next, as shown in FIG. 1D, chemical mechanical polishing (CMP) using the pad nitride film 102 as a stop film is performed on the field oxide film 104 embedded in the trench A. FIG. Plane through.
그런 다음 도 1e에 도시한 바와 같이, H3PO4와 같은 식각액을 사용하여 남겨진 패드 질화막(102)을 제거한다. 이 경우 H3PO4는 산화막과의 선택비가 우수한 특성을 보이기 때문에 소자 분리막인 필드 산화막(104)과 패드 산화막(101)은 약간만이 제거되게 된다.Then, as shown in FIG. 1E, the remaining pad nitride film 102 is removed using an etchant such as H 3 PO 4 . In this case, since H 3 PO 4 has excellent selectivity with respect to the oxide film, only a small amount of the field oxide film 104 and the pad oxide film 101 which are the device isolation films are removed.
전술한 바와 같이 STI를 형성하기 위한 공정을 수행하고 나면, 습식 식각 용액을 이용하여 패드 질화막(102)을 제거하게 되는데, 이때, 액티브의 에지 부분에서 필드 산화막이 많이 손실되어 액티브 에지 부분이 침식되는 에지 모트(edgemoat : B)가 발생하게 된다.As described above, after the process for forming the STI is performed, the pad nitride layer 102 is removed using a wet etching solution. In this case, a large amount of field oxide is lost at the edge portion of the active layer, and the active edge portion is eroded. Edge moat (B) occurs.
이와 같이 종래 기술에 의한 반도체 소자의 소자 분리막 형성 방법에 의하면, 소자 분리막 형성후 패드 질화막 제거 공정시에 습식 식각액에 대한 식각 속도가 빠른 필드 산화막이 일부 손실되어 액티브 에지에 모트가 발생하게 된다. 이에 따라 소자 특성상 험프(hump) 및 INWE(inverse narrow width effect)가 발생하여 소자의 비정상적인 동작을 유발하여 트랜지스터의 특성을 열화시키는 문제점이 존재하게 된다.As described above, according to the method of forming a device isolation layer of a semiconductor device according to the related art, a portion of a field oxide film having a high etching rate with respect to a wet etching solution is partially lost during the pad nitride film removal process after the device isolation layer is formed, resulting in mott at the active edge. Accordingly, there is a problem in that a hump and an inverse narrow width effect (INWE) occur due to device characteristics, causing abnormal operation of the device and deteriorating the characteristics of the transistor.
상기와 같은 문제점을 해결하기 위한 본 발명은 STI 공정시 로코스(LOCOS) 공정의 일부인 열산화막 형성 공정을 적용하여 액티브 에지부에 세정 용액 및 나이트라이드 식각액에 대해 식각 속도가 느린 열산화막을 형성함으로써, 식각 공정 또는 세정 공정에 의한 침식 현상을 방지하여 트랜지스터의 전기적 특성 열화를 방지할 수 있도록 하는 반도체 소자의 소자 분리막 형성 방법을 제공하기 위한 것이다.The present invention for solving the above problems by forming a thermal oxide film having a slow etching rate for the cleaning solution and the nitride etching solution in the active edge portion by applying a thermal oxide film forming process that is part of the LOCOS process during the STI process The present invention provides a method of forming a device isolation layer of a semiconductor device capable of preventing degradation of an electrical property of a transistor by preventing erosion caused by an etching process or a cleaning process.
도 1a 내지 1f는 종래 기술에 의한 반도체 소자의 소자 분리막 형성 공정을 도시한 단면도들이다.1A to 1F are cross-sectional views illustrating a device isolation film forming process of a semiconductor device according to the prior art.
도2a 내지 도2e는 본 발명에 의한 반도체 소자의 소자 분리막 형성 방법을 나타낸 공정 단면도들이다.2A through 2E are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
200 : 실리콘 기판 201 : 버퍼 산화막200: silicon substrate 201: buffer oxide film
202 : 나이트라이드막 203 : 열산화막202: nitride film 203: thermal oxide film
204 : 트렌치 205 : 필드 산화막204 trench 205 field oxide film
상기와 같은 목적을 실현하기 위한 본 발명은 실리콘 기판 상에 버퍼 산화막과 나이트라이드막을 증착하는 단계와, 상기 나이트라이드막을 패터닝하여 필드 영역의 실리콘 기판을 오픈하는 단계와, 상기 필드 영역이 오픈된 결과물 상에 스페이서용 물질을 증착하는 단계와, 상기 스페이서용 물질 및 버퍼 산화막을 식각하여상기 오픈된 필드 영역의 나이트라이드 측벽에 스페이서를 형성하는 단계와, 상기 스페이서가 형성된 실리콘 기판 대한 습식 식각 공정을 진행하는 단계와, 상기 식각된 부분에 열산화막을 형성하는 단계와, 상기 열산화막 및 실리콘 기판을 소정 깊이로 식각하여 트렌치를 형성하는 단계와, 상기 트렌치가 매립되도록 필드 산화막을 증착한 후 평탄화 공정을 진행하는 단계와, 상기 나이트라이드막을 식각 공정으로 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 소자 분리막 형성 방법에 관한 것이다.According to an aspect of the present invention, there is provided a method of depositing a buffer oxide film and a nitride film on a silicon substrate, patterning the nitride film to open a silicon substrate in a field region, and opening the field region. Depositing a spacer material on the spacer, etching the spacer material and the buffer oxide layer to form a spacer on a nitride sidewall of the open field region, and performing a wet etching process on the silicon substrate on which the spacer is formed. Forming a trench by etching the thermal oxide film and the silicon substrate to a predetermined depth; forming a trench; depositing a field oxide film so as to fill the trench; Proceeding, and removing the nitride film by an etching process Relates to a device isolation method for forming a semiconductor device characterized in that comprises a.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.
도2a 내지 도2h는 본 발명에 의한 반도체 소자의 소자 분리막 형성 방법을 나타낸 공정 단면도들이다.2A through 2H are cross-sectional views illustrating a method of forming an isolation layer of a semiconductor device in accordance with the present invention.
우선 도2a에 도시된 바와 같이 실리콘 기판(200) 상에 소정의 습식 산화 공정으로 버퍼 산화막(201)을 50~100Å의 두께로 형성하고, 버퍼 산화막 상부에 제 1 나이트라이드막(202)을 증착한다. 그리고 나서 소정의 감광막 패턴(PR)을 이용하여 상기 제 1 나이트라이드막(202)에 대한 식각 공정을 진행한다.First, as shown in FIG. 2A, a buffer oxide film 201 is formed on the silicon substrate 200 by a predetermined wet oxidation process to a thickness of 50 to 100 GPa, and the first nitride film 202 is deposited on the buffer oxide film. do. Thereafter, an etching process is performed on the first nitride film 202 by using a predetermined photoresist pattern PR.
이어서, 도2b에 도시된 바와 같이 제 2 나이트라이드막(203)을 증착하고 나서, 이방성 전면 식각 공정을 진행하여 버퍼 산화막(201)이 식각되도록 하고 나면, 도2c와 같은 스페이서(203')가 형성이 된다. 이후, 버퍼 산화막(203') 식각 후 실리콘 기판(200)을 100~200Å 식각되도록 오버 식각을 진행할 수 있다.Subsequently, as shown in FIG. 2B, after the second nitride layer 203 is deposited, the anisotropic front side etching process is performed to etch the buffer oxide layer 201, and then the spacer 203 ′ as shown in FIG. 2C is formed. Formation. Thereafter, after etching the buffer oxide layer 203 ′, the over-etching may be performed to etch the silicon substrate 200 at 100˜200 μs.
그런 다음, 도2d에 도시된 바와 같이 SC-1 용액을 이용한 습식 식각 공정을 진행하여 실리콘 기판이 500Å 깊이로 등방성 식각되도록 한다.Next, as shown in FIG. 2D, the wet etching process using the SC-1 solution is performed to allow the silicon substrate to be isotropically etched to a depth of 500 μs.
그런 다음, 도2e에 도시된 바와 같이 열산화 공정을 진행하여 500~1000Å 산화막(204)이 형성되도록 하되, 상기 열산화 공정은 H2O를 포함하는 습식 열산화 공정으로 진행하거나, O2를 포함하는 건식 열산화 공정으로 진행한다.Then, as shown in Figure 2e to proceed to the thermal oxidation process to form a 500 ~ 1000Å oxide film 204, the thermal oxidation process proceeds to a wet thermal oxidation process including H 2 O, or O 2 Proceed to a dry thermal oxidation process that includes.
상기 열산화 공정을 진행한 후에 도2f에 도시된 바와 같이 상기 나이트라이드막(202)을 베리어막으로 이용하여 필드 영역의 열산화막(204)과 실리콘 기판을 소정 깊이로 식각하여 트렌치(205)를 형성한다.After the thermal oxidation process, the trench 205 is etched by etching the thermal oxide film 204 and the silicon substrate in the field region to a predetermined depth using the nitride film 202 as a barrier film as shown in FIG. 2F. Form.
이어서, 도2g에 도시된 바와 같이 상기 트렌치(205)가 매립되도록 필드 산화막(206)을 증착하고 상기 나이트라이드막(202)과 열산화막(204)이 드러나도록 평탄화 공정을 진행한다. 이때, 상기 필드 산화막(206)은 갭필 특성이 HDP(High density plasma) 산화막 또는 TEOS(Tetra ethyl ortho silicate)를 사용한다.Next, as shown in FIG. 2G, the field oxide film 206 is deposited to fill the trench 205 and the planarization process is performed so that the nitride film 202 and the thermal oxide film 204 are exposed. In this case, the field oxide layer 206 uses a high density plasma (HDP) oxide layer or tetra ethyl ortho silicate (TEOS).
그후, 상기 나이트라이드막(202)을 인산 용액을 이용한 습식 식각 공정으로 제거하면 도2h에 도시된 바와 같이 소자 분리막 액티브의 에지부에 열산화막(204)이 남아 있게되어, 식각 속도가 느린 열산화막에 의해 후속 세정 공정등에 의한 액티브 에지부의 침식 현상을 최소화 할 수 있게된다.Thereafter, when the nitride film 202 is removed by a wet etching process using a phosphoric acid solution, the thermal oxide film 204 remains at the edge portion of the device isolation film active as shown in FIG. This can minimize the erosion of the active edge portion due to the subsequent cleaning process.
이와 같은 본 발명에 의한 소자 분리막 형성 방법에 의하면, 나이트라이드 스페이서를 이용하여 액티브 영역 감소를 방지할 뿐만 아니라, 트렌치 소자 분리막에 LOCOS 공정의 일부를 적용하여 액티브 에지부에 식각 속도가 느린 열산화막을 형성함으로써, 식각액 또는 세정 용액에 의한 침식 작용을 최대한 방지할 수 있고, 이로 인해 액티브 에지부의 모트(Moat) 발생을 방지할 수 있게된다.According to the method of forming an isolation layer according to the present invention, not only the active spacer is reduced by using nitride spacers, but also a portion of the LOCOS process is applied to the trench isolation layer to form a thermal oxide film having a slow etching rate at the active edge portion. By forming, the erosion action by the etching liquid or the cleaning solution can be prevented as much as possible, thereby preventing the occurrence of moat of the active edge portion.
상기한 바와 같이 본 발명은 액티브 에지 부분의 필드산화막을 일반 산화막보다 식각 속도가 낮은 열산화막으로 형성하여 나이트라이드막 제거시 및 세정 공정시 액티브 에지 부분이 침식되는 현상을 최소화함으로써, 에지 모트에 의한 험프(hump), INWE(inverse narrow width effect)와 같은 트랜지스터의 전기적 특성을 열화 현상을 방지하여 소자의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, the present invention forms the field oxide film of the active edge portion as a thermal oxide film having a lower etching rate than the general oxide layer, thereby minimizing the erosion of the active edge portion during the removal of the nitride layer and the cleaning process, thereby reducing the It is possible to improve the reliability of the device by preventing deterioration of the electrical characteristics of the transistor, such as a hump and an inverse narrow width effect (INWE).
Claims (7)
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