KR20040099618A - ESD protection device of semiconductor device and memufacturing method thereof - Google Patents

Abstract

PURPOSE: An ESD(ElectroStatic Discharge) part of a semiconductor device and a manufacturing method thereof are provided to prevent failure of the device due to over-current and over-voltage by increasing current paths of the device using a deep tap region, restraining the punch-through using pocket regions, and preventing a parasitic diode from being operated using an n junction region of high concentration. CONSTITUTION: A deep tap region(45) of the second conductive type is formed under the second conductive type drain(44). The second conductive type well region(46) of low concentration is formed within a BJT region of a semiconductor substrate(30). The second conductive type region(47) of high concentration is formed at one side of the second conductive type well region. The first conductive type junction region(53) of high concentration is formed under the second conductive type well region. The first conductive type pocket regions(50,51) are formed between the deep tap region and the second conductive type well region.

Description

Electrostatic discharge protection device for semiconductor device and manufacturing method thereof {ESD protection device of semiconductor device and memufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic discharge (hereinafter referred to as ESD) protection device of a semiconductor device and a method of manufacturing the same, and in particular, a current path of a transistor during ESD of a field transistor used as an input pad protection transistor. The present invention relates to an ESD protection device of a semiconductor device which can improve the reliability of device operation by preventing the occurrence of device failure due to overcurrent-overvoltage by increasing parasitic diode operation.

In general, a semiconductor device is used after a plurality of chips are manufactured together in a wafer state and then cut and packaged for each chip. When a static electricity generated by a device or a human body is applied during a manufacturing process or a transport in a wafer state or a package state, an instantaneous voltage is 4000V. The above high voltage is applied to destroy the device.

As semiconductor devices become more integrated, countermeasures for preventing the destruction of the device against ESD are subject to many restrictions in design.

Conventional ESD protection devices typically include field transistors (Tf), which consume most of the current during ESD zapping between input pads (IP) and internal circuits (IC), and gate-ground NMOS to protect gate oxides of internal circuits. And a transistor (Tn) and a resistor (R) for preventing excessive current flow into the NMOS transistor (Tn).

1 is a cross-sectional view of an ESD protection device of a semiconductor device according to the prior art.

First, a high concentration n well 12 is formed on a semiconductor substrate 10 such as a silicon wafer, and a plurality of element isolation oxide films 14 are formed on the high concentration n well 12 to form a BJT region and a well bias region. The high concentration n + well bias 16 is formed on the semiconductor substrate 10 of the well bias region, and the BJT having a double gate structure is formed in the BJT region.

In the BJT, a lower gate electrode 22 electrically fluted is formed on the gate oxide layer 20 formed on the semiconductor substrate 10, and the semiconductor substrate 10 on one side of the lower gate electrode 22 is formed. ), A high concentration p + drain 24 formed on the p-well 26, a P-well 26 formed on the semiconductor substrate 10 on the other side of the lower gate electrode 22, and a high concentration p + formed on the p-well 26 A source composed of a region 27, an interlayer insulating film 28 applied to the entire surface of the structure, and an upper gate electrode 29 partially overlapping the lower gate electrode 22 and the p-well 26. The well bias 16, the emitter 24, and the upper gate electrode 29 are connected to an input terminal of the chip, and the high concentration p + region 27 is connected to an internal circuit.

In the prior art as described above, the internal circuit must be protected by the parasitic pnp BJT, but a parasitic diode is formed between the high concentration p + region of the collector and the well bias, thereby preventing effective ESD protection.

In addition, the conventional ESD protection device has a limit in miniaturization of the device because the size of the device is determined in proportion to the current capability, there is a problem that the miniaturization of the high-voltage device is difficult when considering the punch-through or short channel effect.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to form a deep tap region under the drain of a field transistor for ESD protection, and to prevent the inter-junction punch-through resulting from the formation of a parasitic pnp BJT. The present invention provides an electrostatic protection device for a semiconductor device and a method of manufacturing the same, which are advantageous for the miniaturization of devices by forming the device more efficiently, and are useful for high voltage, and can be prevented by the operation of parasitic diodes.

1 is a cross-sectional view of an electrostatic discharge protection device according to the prior art.

2 is a cross-sectional view of an electrostatic discharge protection device according to the present invention.

Figure 3a to 3g is a manufacturing process of the electrostatic discharge protection device according to the present invention.

<Description of Symbols for Major Parts of Drawings>

10, 30: semiconductor substrate 12, 32: high concentration n well

14, 34: device isolation oxide film 16, 36: well bias

20, 40: gate oxide film 22, 42: lower gate electrode

24, 44 drain 26, 46 p-well

27, 47: high concentration p + region 28, 48: interlayer insulating film

29, 49: upper gate electrode 45: deep tap

50, 51: Pocat area 53: High concentration n junction area

Features of the electrostatic protection device of a semiconductor device according to the present invention for achieving the above object,

In the electrostatic discharge protection device of a semiconductor device having a well bias and BJT,

A highly-concentrated well region of the first conductivity type formed in a portion of the semiconductor substrate, which is intended as an ESD protection element,

A device isolation oxide film separating a well bias region and a BJT region in the high concentration well region;

A well bias of the first conductivity type formed on the semiconductor substrate defined by the well bias region;

A drain of the second conductive type formed on one side of the semiconductor substrate, which is intended to be the BJT region;

A deep tap region of a second conductivity type formed under the drain;

A low concentration second conductive well region formed on the semiconductor substrate on the other side of the BJT region;

A high concentration second conductive region formed on one side of the low concentration second conductivity type well region,

A high concentration first conductive junction region formed under the low concentration second conductive well region,

First conductive type focusing regions formed under the channel side surface of the deep tap region and the low concentration second conductive well region;

A gate oxide film formed on the semiconductor substrate between the drain and the low concentration second conductive well region;

An electrically fluted lower gate electrode formed on the gate oxide layer;

An interlayer insulating film formed on the entire surface of the structure;

And an upper gate electrode formed on the interlayer insulating layer so as to overlap a portion of the lower gate electrode and a portion of the low concentration second conductive type well region.

In addition, the features of the method for manufacturing an electrostatic discharge protection device of a semiconductor device according to the present invention,

In the manufacturing method of the electrostatic discharge protection device of a semiconductor device having a well bias and a double-gate structure BJT,

Forming a high concentration first conductive well region on a portion of the semiconductor substrate that is intended as an ESD protection device;

Forming a low concentration second conductivity type well region in a portion of the high concentration first conductivity type well region that is supposed to be a source of BJT;

Forming a high concentration first conductivity type junction region under the low concentration second conductivity type well region;

Forming a deep tap region of a second conductivity type in a lower portion of the high concentration first conductivity type well region that is intended to be a drain of the BJT;

Forming a device isolation oxide film on the predetermined device isolation region of the semiconductor substrate to separate the ESD protection device region from the device region, and to separate the BJT region and the well bias region of the ESD protection device;

Forming a gate oxide film on the BJT region of the semiconductor substrate;

Forming an electrically fluted lower gate electrode on the gate oxide film;

Forming pocket regions at a lower side of the channel side of the low concentration second conductive well region deep tap region by injecting a gradient ion of a next first conductive impurity;

Applying an interlayer insulating film to the entire surface of the structure;

Forming an upper gate electrode overlapping the lower gate electrode and a portion of the low concentration second conductive well region on the interlayer insulating film;

Forming a well bias of a high concentration first conductivity type on a portion of the semiconductor substrate which is intended as a well bias region;

And forming a high concentration second conductive type drain region on the deep tap region and a high concentration second conductive type junction region on an upper side of the low concentration second conductive type well region.

Hereinafter, an electrostatic protection device of a semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view of an ESD protection device of a semiconductor device according to the present invention, wherein the ESD protection field transistor is a parasitic pnp BJT, and is composed of a well bias and a BJT.

First, a high concentration n well 32 is formed on a portion of the semiconductor substrate 30 such as a silicon wafer, which is intended as an ESD protection element, and an element isolation oxide film is formed on the semiconductor substrate 30 on the high concentration n well 32. 34 is formed to distinguish the BJT region and the well bias region of the ESD protection device.

Here, a well-concentrated well bias 36 having a high concentration n + is formed on the semiconductor substrate 30 in the well bias region, and a BJT having a double gate structure is formed in the BJT region.

In the BJT, a high concentration p + drain 44 is formed at one side of the BJT region I of the semiconductor substrate 30, and a dip tab 45 is formed at a lower portion of the drain 44 having a high concentration p +. On the semiconductor substrate 30 on the other side of the BJT region I, a source composed of a P-well 46 and a high concentration p + region 47 formed on the p-well 46 is formed. A gate oxide film 40 is formed on the semiconductor substrate 30 between the drain 44 and the P-well 46, and an electrically floated lower gate electrode 42 is formed on the gate oxide film 40. The interlayer insulating film 48 is coated on the entire surface of the structure.

In addition, an upper gate electrode 49 overlapping a portion of the lower gate electrode 42 and a portion of the p-well 46 is formed on the interlayer insulating layer 48, and the dip tab 45 and the P-well ( Pocket regions 50 and 51 made of n-type impurities are formed under the surface channel of the channel-side semiconductor substrate 30 of 46, and a high concentration n-junction region 53 is formed below the P-well 46. Formed.

The high concentration n junction region 53 reduces the depletion width to reduce avalanche current, thereby suppressing pn diode formation, and the format regions 50 and 51 suppress punch through.

The well bias 36, the drain 44, and the upper gate electrode 49 are connected to an external input terminal to apply static electricity, and the high concentration p + region 47 of the source is connected to an internal circuit.

3A to 3G are diagrams illustrating a manufacturing process of an ESD protection device according to the present invention.

First, a high concentration n well 32 is formed by an ion implantation process using a mask on a portion of the semiconductor substrate 30 that is intended as an ESD protection element, and a source of BJT is planned in the high concentration n well 32. An ion implantation process using each mask in the portion forms a p-well 46 and a high concentration n junction region 53 located under the p-well 46. The high concentration n junction region 53 reduces the depletion width to reduce avalanche current, thereby inhibiting pn diode formation. (See FIG. 3A).

Then, a p-type deep tap 45 is formed by an ion implantation process using a mask on the lower portion of the high concentration n well 32 that is intended to drain the BJT, and the device isolation oxide film 34 is formed by performing a device isolation process. It is formed to separate the ESD protection device region from the device region, and to distinguish the BJT region and the well bias region of the ESD protection device. (See Figure 3b).

Thereafter, the gate oxide layer 40 and the electrically gated lower gate electrode 42 and the insulating spacer 43 are sequentially disposed between the p-well 46 and the deep tab 45 on the BJT region of the semiconductor substrate 30. To form. (See FIG. 3C).

Then, pocket regions 50 and 51 for punch-through prevention in the lower portion of the channel region of the lower channel semiconductor substrate 30 adjacent to the p-well 46 and the dip tab 45 by the gradient ion implantation process of the n-type impurity. To form. Here, when the stress is applied, the path is doubled up and down to form the path faster. (See FIG. 3D).

Thereafter, an interlayer insulating film 48 is applied to the entire surface of the structure, and the upper gate electrode 49 overlapping the lower gate electrode 42 and a part of the p-well 46 on the interlayer insulating film 48. To form. (See Figure 3E).

Then, a high concentration n-type well bias 36 is formed by ion implantation fixing using a mask on a portion of the semiconductor substrate 30 that is intended as the well bias region II (see FIG. 3F), and then again the source / A high concentration p-type impurity is ion-implanted using a mask on a portion intended as a drain region to form a p + drain 44 on the dip tab 45 and a high concentration p + on one side of the p-well 46. Area 47 is formed. (See FIG. 3G).

As described above, the ESD protection device of the semiconductor device and the method of manufacturing the same according to the present invention form a deep tap under the drain of the BJT, and form a high concentration n junction region under the P-well of the source, and the deep tap and the p Since the pore region is formed in the lower channel side of the well, the high concentration n junction region reduces the depletion width to reduce the avalanche current, thereby suppressing pn diode formation, and the pore region suppresses punchthrough. The pass is also formed through the deep tap, and the effect of the ESD is increased, and the size of the device can be reduced by the increased path, so that high integration of the device is advantageous.

Claims (2)

In the electrostatic discharge protection device of a semiconductor device having a well bias and BJT, A highly-concentrated well region of the first conductivity type formed in a portion of the semiconductor substrate, which is supposed to be an ESD protection element, A device isolation oxide film separating a well bias region and a BJT region in the high concentration well region; A well bias of a first conductivity type formed on a semiconductor substrate which is intended to be the well bias region; A drain of the second conductive type formed on one side of the semiconductor substrate, which is intended to be the BJT region; A deep tap region of a second conductivity type formed under the drain; A low concentration second conductive well region formed on the semiconductor substrate on the other side of the BJT region; A high concentration second conductive region formed on one side of the low concentration second conductivity type well region, A high concentration first conductive junction region formed under the low concentration second conductive well region, Pocket regions of the first conductive type formed under the channel-side surface of the semiconductor substrate between the deep tap region and the low concentration second conductive well region; A gate oxide film formed on the semiconductor substrate between the drain and the low concentration second conductive well region; An electrically floated lower gate electrode formed on the gate oxide layer; An interlayer insulating film formed on the entire surface of the structure; And an upper gate electrode formed on the interlayer insulating layer so as to overlap a portion of the lower gate electrode and a portion of the second concentration well-conducting well region. In the manufacturing method of the electrostatic discharge protection device of a semiconductor device having a well bias and a double-gate structure BJT, Forming a high concentration first conductive well region on a portion of the semiconductor substrate that is intended as an ESD protection device; Forming a low concentration second conductivity type well region in a portion of the high concentration first conductivity type well region that is supposed to be a source of BJT; Forming a high concentration first conductivity type junction region under the low concentration second conductivity type well region; Forming a deep tap region of a second conductivity type in a lower portion of the high concentration first conductivity type well region that is intended to be a drain of the BJT; Forming a device isolation oxide film on the predetermined device isolation region of the semiconductor substrate to separate the ESD protection device region from the device region, and separating the BJT region and the well bias region of the ESD protection device; Forming a gate oxide film on the BJT region of the semiconductor substrate; Forming an electrically fluted lower gate electrode on the gate oxide film; Forming pocket regions between the low concentration second conductive well region deep tap regions by inclined ion implantation of a first conductive impurity in a lower portion of the channel side of the semiconductor substrate; Applying an interlayer insulating film to the entire surface of the structure; Forming an upper gate electrode overlapping the lower gate electrode and a portion of the low concentration second conductive well region on the interlayer insulating film; Forming a well bias of a high concentration first conductivity type on a portion of the semiconductor substrate which is intended as a well bias region; Forming a drain region of a high concentration second conductive type on the deep tap region and forming a high concentration second conductive type junction region on an upper side of the low concentration second conductive type well region. Method of manufacturing the device.