KR20040095944A - Cmos image sensor and method of manufacturing the same - Google Patents

Abstract

PURPOSE: A CMOS(Complementary Metal Oxide Semiconductor) image sensor and a method for manufacturing the same are provided to reduce reference broadening effect due to RC delay of a drive and a select transistors connected to an output terminal by forming a mini P-well in a portion of the transistor. CONSTITUTION: A transistor region(200) for a drive and a select transistor is designated in a high doped P-type substrate(50). A low doped P-type epitaxial layer(51) is formed in the substrate. A mini P-well(57) is partially formed in a portion of the transistor region. A high doped N-type region(58) is formed in both surface of the mini P-well and surface of the epitaxial layer.

Description

CMOS image sensor and its manufacturing method {CMOS IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME}

The present invention relates to a CMOS image sensor and a method of manufacturing the same, and more particularly, to a CMOS image sensor and a method of manufacturing the same that can suppress the reference magnification effect.

In general, a complementary metal oxide semiconductor (CMOS) image sensor is a semiconductor device that converts an optical image into an electrical signal, and processes a light sensing portion and a sensed light into an electrical signal. It consists of a logic circuit part to make data, and adopts a switching method of making MOS transistors by the number of pixels using CMOS technology and sequentially detecting output using them.

The CMOS image sensor includes a pixel region and a peripheral region, a pixel array is formed in the pixel region, and NMOS and PMOS transistors are formed in the peripheral region, respectively, and the unit pixels of the pixel array are shown in FIG. Similarly, it is composed of one photodiode PD and four transistors Tx, Rx, Dx, and Sx, which are light-receiving elements, and four transistors transport the photocharges focused on the photodiode to the floating node F. Transistor (Tx), Reset transistor (Rx) for discharging and resetting charges stored in floating node (F), Drive transistor acting as source follower buffer amplifier (Source follower buffer amplifier) Dx) and a select transistor (Sx) that plays a role of switching and addressing. In addition, a capacitance Cfd is present at the floating node F of the unit pixel, and a load transistor is formed outside the unit pixel to read an output signal.

Here, the NMOS transistor in the peripheral region is a normal NMOS transistor, and the transfer and reset transistors Tx and Rx of the unit pixel are NMOSs of low threshold voltage or depletion mode for complete reset of the floating node F. The transistors, and the driving and selection transistors Dx and Sx, are made of a conventional enhancement mode NMOS transistor. Accordingly, the transfer and reset transistors Tx and Rx are formed as native NMOS transistors without forming P wells, and P wells are formed in the NMOS transistors of the peripheral region and the driving and selection transistors Dx and Sx regions. Typically, the P wells in the peripheral region are called normal P wells, and the P wells of the driving and selection transistors Dx and Sx are smaller than the normal P wells.

On the other hand, the CMOS image sensor described above typically detects an electrical signal corresponding to the photocharge by a correlated double sampling (CDS) method. However, when the predetermined voltage of the output terminal Vo is set as the reference level in the CDS method, the RC delay caused by the driving transistor Dx and the selection transistor Sx connected to the output terminal Vo is used. As a result, a so-called Reference Broadening Effect or Reference Bending Effect may occur, in which the reference level does not increase rapidly to a certain level but is widely distributed.

In more detail, for example, in the case of an RC circuit in which a resistor and a capacitor are connected in series, as shown in the following equation (1) (2) and the graph of FIG. The time to reach (V / R) e ^-1 at V / R increases, indicating that the RC value has a significant effect on the device delay.

i (t) = (V / R) e- ^{(1 / RC) t} ...

τ = RC ‥‥‥‥‥‥‥‥‥‥‥‥‥‥ equation (2)

Here, i represents a current (A) that changes with time, R represents a resistance value (Ω), V represents an applied voltage (V), C represents capacitance (F), t represents time, and τ represents time constant.

In addition, the RC delay is not only generated by reducing the pulse waveform of the reference level as shown in FIG. 3, but also differently observed in the same pixel as in the case of A and B, so that a specific clock for reading the reference level is shown. When the clock time is τ, A and B have different reference level values of A 'and B' at τ, and due to the difference in these reference level values, as shown in FIG. The distribution of does not achieve an ideal distribution with a sharp increase, and it has a form that is less attracted in the distribution, that is, a tail, thus causing a reference expansion effect having a practically wide distribution range.

Such a reference expansion effect limits the amplification of the image signal by limiting the width that can give a gain to the CMOS image sensor, thereby causing deterioration of the characteristics of the CMOS image sensor.

The present invention has been proposed to solve the above problems of the prior art, and provides a CMOS image sensor and a method of manufacturing the same that can suppress the reference expansion effect by reducing the RC delay of the drive and the selection transistor connected to the output stage. There is a purpose.

1 is a circuit diagram showing a unit pixel of a general CMOS image sensor.

2 is a graph showing a current pulse waveform of a general series RC circuit.

3 is a graph showing pulse waveforms of reference levels according to clock time in the same pixel.

4 is a graph showing a conventional reference level distribution.

5A to 5C are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to an embodiment of the present invention.

※ Explanation of symbols for main parts of drawing

50 semiconductor substrate 51 p-type epi layer

52: field oxide film 53, 56: first and second photoresist patterns

54: normal P well 55: buffer layer pattern

57: Mini P well 58: N-type junction area

100: NMOS transistor area

200: drive and select transistor area

According to an aspect of the present invention for achieving the above technical problem, an object of the present invention is a high-concentration P-type semiconductor substrate in which the drive and the selection transistor region is defined; A low concentration P-type epi layer formed on the substrate; A mini P well partially formed only on one epi layer of the drive and select transistor regions; And a high concentration N-type junction region formed on the surface of the mini P well and epi layer in the drive and select transistor regions, the portion in contact with the mini P well and the other portion in contact with the epi layer.

Here, the other portion of the N-type junction region has a relatively large depletion width compared to the portion in operation.

In addition, the object of the present invention is to prepare a high-concentration P-type semiconductor substrate in which the NMOS transistor region of the peripheral region, the driving and selection transistor region of the pixel region are defined, and the low-concentration P-type epi layer is formed; Forming a field oxide film on the substrate to separate the regions from each other; Forming a first photoresist pattern on the substrate to open the NMOS transistor region; Forming a normal P well by implanting P-type impurity ions into a region opened by first to fourth rotatable ion implantation using a first photoresist pattern; Removing the first photoresist pattern; Forming a buffer layer pattern and a second photoresist pattern on the substrate to open the NMOS transistor region and the drive and select transistor region; P-type impurity ions are implanted into the normal P well by implanting P-type impurity ions into a region opened by the first and second gradient ion implantations in a unidirectional direction so that shadowing occurs using a second photoresist pattern and a buffer layer pattern. Simultaneously forming a mini P well only on one side of the driving and selection transistor region; And sequentially removing the photoresist pattern and the buffer layer pattern.

Herein, the first and second rotatable ion implantation are performed in four directions of rotation by 1/4 concentration, and the third and fourth rotatable ion implantation are omitted by rotation of the same direction as the gradient ion implantation, and the third and fourth rotatable ion implantation Perform in directional rotation. Preferably, the first rotary ion implantation is carried out at a concentration of 5.0E12 × 4 / cm 3 and an energy of 350 keV, and the second rotary ion implantation is performed at a concentration of 1.5E12 × 4 / cm 3 and an energy of 150 keV, and the third rotation Ion implantation is performed at a concentration of 5.0E11 × 3 / cm 3 and an energy of 80 keV, and the fourth rotary ion implantation is performed at a concentration of 2.0E12 × 3 / cm 3 and an energy of 20 keV.

In addition, the buffer layer pattern is made of a nitride film, wherein the nitride film has a thickness of 1000 to 1500 kPa.

In addition, the first gradient ion implantation is performed at a concentration of 2.0E12 / cm 3 and an energy of 80 keV, and the second gradient ion implantation is performed at a concentration of 8.0E12 / cm 3 and an energy of 20keV.

P-type impurity ions are boron ions.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

5A to 5C are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to an exemplary embodiment of the present invention.

Referring to FIG. 5A, a high-concentration P-type semiconductor substrate in which a NMOS transistor region 100 in a peripheral region, a driving and selection transistor region 200 of a pixel region are defined, and a low concentration P-type epitaxial layer 51 is formed ( A field oxide film 52 is formed on 50 to separate regions 100 and 200 from each other. Next, a first photoresist film is coated on the substrate, and a first photoresist pattern 53 is formed by exposing and developing using a normal P well mask (not shown) to open the NMOS transistor region 100. Then, P-type impurity ions, preferably boron, are injected by the first to fourth rotational ion implantations that rotate clockwise around the gate of the drive and select transistors with different concentration and energy conditions into the open region. B) ions are implanted in steps to form a normal P well 54. In this case, the first and second rotary ion implants are performed in four-direction rotations by 1/4 concentration, and the third and fourth rotary ion implants are omitted by one-fourth concentration by omitting the rotation in one of the horizontal directions with the gate. The process time is shortened by 3-way rotation. That is, the first rotary ion implantation is performed at a concentration of 5.0E12 × 4 / cm 3 and an energy of 350 keV, the second rotary ion implantation is performed at a concentration of 1.5E12 × 4 / cm 3 and an energy of 150 keV, and the third rotary ion Injection is carried out at a concentration of 5.0E11 x 3 / cm 3 and an energy of 80 keV, and the fourth rotary ion implantation is performed at a concentration of 2.0E12 x 3 / cm 3 and an energy of 20 keV.

Referring to FIG. 5B, the first photoresist pattern 53 is removed by a known method, a buffer layer is formed of a nitride film having a thickness of 1000-1500 Å on the entire surface of the substrate, and a second photoresist film is applied on the buffer layer. Next, instead of the conventional mini P well mask which opens only the drive and select transistor region 200, a new mini P well mask (not shown) which opens the NMOS transistor region 100 and the drive and select transistor region 200 is then replaced. The second photoresist film is exposed and developed to form the second photoresist pattern 56. Thereafter, the lower buffer layer is etched using the second photoresist pattern 56 as a mask to form the buffer layer pattern 55 to open the NMOS transistor region 100 and the driving and selection transistor region 200. Then, using the second photoresist pattern 56 and the buffer layer pattern 55, the unidirectional, i.e., the third and fourth rotatable implants having different concentration and energy conditions to cause the shading to occur. P-type impurity ions, i.e., B ions, are injected into the region opened by the first and second tilt ion implantation in the same direction as that omitted, and the P-type impurity ions of the normal P well 54 are supplemented. At the same time, the mini P well 57 is partially formed on only one side of the driving and selection transistor region 200. Preferably, the first gradient ion implantation is performed at a concentration of 2.0E12 / cm 3 and an energy of 80 keV, and the second gradient ion implantation is performed at a concentration of 8.0E12 / cm 3 and an energy of 20keV.

Referring to FIG. 5C, the second photoresist pattern 56 and the buffer layer pattern 55 are sequentially removed by a known method, and although not shown, gate oxide films, gates, and gate spacers are formed, respectively. Next, a high concentration of the N-type junction region 58 is formed on the surface of the mini P well 57 and the P-type epi layer 51 of the driving and selective transistor region 200 by a mask process and an ion implantation process. That is, a portion of the N-type junction region 58 is in contact with the mini P well 57 and the other portion is in contact with the P-type epi layer 51 having a relatively low concentration compared to the mini P well 57, thereby operating the device. A portion of the N-type junction region 58 decreases in the depletion width, whereas the depletion width of the other portion increases relatively to have a large depletion width, thereby significantly reducing the junction capacitance. On the other hand, the resistance of the substrate is slightly increased by such a partial mini-P well 57, but the resistance of the substrate is increased because the resistance value fluctuates in the positive integer range but the capacitance fluctuates in the order unit. However, the RC delay can be significantly reduced due to the reduction in the relatively large capacitance.

According to the above embodiment, the mini-P well is partially formed only on one side of the epi layer of the driving and selective transistor region, unlike the conventional method, by unidirectional gradient ion implantation using a new mini P well mask and shadowing by a buffer layer pattern. By increasing the depletion width of the portion of the N-type junction region relatively large, it is possible to significantly reduce the junction capacitance, thereby reducing the RC delay. Accordingly, it is possible to suppress the pulse waveform reduction of the reference level caused by the RC delay and the effect of expanding the reference, thereby widening the gain width of the CMOS image sensor and facilitating amplification of the image signal.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The above-described present invention partially reduces the RC delay of the driving and selection transistors connected to the output stage by partially forming the mini P well on only one side of the driving and selection transistor region, thereby suppressing the reference magnification effect caused by the RC delay. The characteristics of the image sensor can be improved.

Claims (9)

A high concentration P-type semiconductor substrate having drive and select transistor regions defined therein; A low concentration P-type epi layer formed on the substrate; A mini P well partially formed on only one epi layer of the driving and selection transistor region; And And a high concentration N-type junction region formed on a surface of the mini P well and the epi layer of the driving and selective transistor region, the portion being in contact with the mini P well and the other portion being in contact with the epi layer. The method of claim 1, And the other portion of the N-type junction region has a relatively larger depletion width than the portion in operation. Preparing a high concentration P-type semiconductor substrate having an NMOS transistor region in the peripheral region, a driving and selection transistor region of the pixel region defined therein, and a low concentration P-type epitaxial layer formed; Forming a field oxide film on the substrate to separate the regions from each other; Forming a first photoresist pattern on the substrate to open the NMOS transistor region; Forming a normal P well by implanting P-type impurity ions into the open region by first to fourth rotatable ion implantation using the first photoresist pattern; Removing the first photoresist pattern; Forming a buffer layer pattern and a second photoresist pattern on the substrate to open the NMOS transistor region and the driving and selection transistor region; P-type impurity ions are implanted into the open region by first and second gradient ion implantation in a unidirectional manner to induce shadowing using the second photoresist pattern and the buffer layer pattern. Replenishing impurity ions and simultaneously forming a mini P well on only one side of the driving and selection transistor regions; And And sequentially removing the photoresist pattern and the buffer layer pattern. The method of claim 3, wherein The first and second rotatable ion implantation are performed in four directions of rotation by 1/4 concentration, and the third and fourth rotatable ion implantation are performed by 1/4 concentration by omitting rotation in the same direction as the warp ion implantation. A method of manufacturing a CMOS image sensor, characterized in that it is carried out by directional rotation. The method of claim 4, wherein The first rotary ion implantation is performed at a concentration of 5.0E12 × 4 / cm 3 and an energy of 350 keV, and the second rotary ion implantation is performed at a concentration of 1.5E12 × 4 / cm 3 and an energy of 150 keV, and the third rotation Ion implantation is performed at a concentration of 5.0E11 × 3 / cm 3 and energy of 80keV, and the fourth rotary ion implantation is performed at a concentration of 2.0E12 × 3 / cm 3 and energy of 20keV. Way. The method of claim 3, wherein The buffer layer pattern is a manufacturing method of the CMOS image sensor, characterized in that consisting of a nitride film. The method of claim 6, The nitride film has a thickness of 1000 to 1500Å, the manufacturing method of the CMOS image sensor. The method of claim 3, wherein The first gradient ion implantation is performed at a concentration of 2.0E12 / cm 3 and an energy of 80 keV, and the second gradient ion implantation is performed at a concentration of 8.0E12 / cm 3 and an energy of 20keV. Way. The method according to claim 5 and 8, The p-type impurity ion is a manufacturing method of the CMOS image sensor, characterized in that the boron ion.