KR20040093775A - Bus-width downsizing converter - Google Patents

Abstract

PURPOSE: A circuit for reductively converting a bus width is provided to reduce a size of the bus width for transmitting a signal between blocks divided for integrating the FPGA(Field Programmable Gate Arrays) by using a coding circuit inserted into a side for transmitting a signal and a decoding circuit inserted into the side receiving the signal. CONSTITUTION: A (n/2)-1 bit counter(111) receives an n/2 speed clock compared to a reference clock. The first multiplexer(113) selectively outputs an inputted M bit signal to a 2M/n bit by an output signal of the counter. The second multiplexer(115) selectively outputs the output of the first multiplexer to an M/n bit by the n/2 speed clock. An M/n bit flip-flop(121) outputs the 2M/n bit by combination with an M/n bit signal bypassed by delaying the M/n bit signal output from the second multiplexer with the n/2 speed clock. 2M/n bit flip-flops(123/1-123/(n/2-1)) output the M bit by the combination with a bypassing input signal of each flip-flop.

Description

Bus width reduction conversion circuit {BUS-WIDTH DOWNSIZING CONVERTER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus-width reduction conversion circuit, and more particularly, to transmit a signal in blocks partitioned into different FPGAs in order to integrate a system to be integrated into a single semiconductor chip into a plurality of FPGAs. A bus width reduction conversion circuit is provided in which an encoding circuit is inserted into a side and a decoding circuit is inserted into a receiving side to reduce the width of a bus for signal transmission between blocks.

In general, when designing a system to be integrated into a semiconductor chip, a prototype is implemented using a field programmable gate array (FPGA) before mass production to verify the operation and performance of the system.

In this prototype implementation, chips more than one million gates are difficult to integrate into one FPGA, so the original designed system as shown in FIG. 1A is divided into a plurality of FPGAs as shown in FIG.

However, the width of the signal transmission bus between the divided blocks becomes an important consideration during the partitioning process for integrating the original system into the FPGA.

Because the system originally expected to be integrated into one semiconductor chip (IC) as shown in Figure 1a, the width of the bus (a, b, c) for the signal transmission between the blocks (BLK1, BLK2, BLK3) is generally large, Therefore, when integrating into the FPGA1 and FPGA2 without reducing the bus width (b, c) between the blocks (BLK1 and BLK3, BLK2 and BLK3) that are integrated in different FPGAs, the integration is not possible due to the limited number of pins of the FPGA. This is because there are problems that are often impossible or difficult.

The present invention has been proposed to solve such a conventional problem, and is inserted into a coding circuit and a receiver receiving a signal for inserting a signal to reduce the width of a bus for signal transmission between the divided blocks for FPGA integration. It is an object of the present invention to provide a bus width reduction conversion circuit which reduces the width of a bus to an arbitrary size by using a decoding circuit.

The bus width reduction conversion circuit according to the present invention for realizing the above object is a bus width for reducing the bus width to M / n bits in a system that receives a reference clock and performs signal transmission between blocks through a M bit bus width. 9. A reduced conversion circuit, comprising: a (n / 2) -1 bit counter receiving an n / 2 times faster clock than the reference clock; A first multiplexer which selects an input M bit signal according to an output signal of the counter and outputs the 2 M / n bit; A second multiplexer which receives an output of the first multiplexer and selects the output of the first multiplexer by using an n / 2-speed clock and outputs M / n bits; M / n bit flip-flop that receives the M / n bit signal output from the second multiplexer and outputs 2M / n bit in combination with the bypassed M / n bit signal by delaying by n / 2 times the clock. ; 2M / n flip-flops that receive the 2M / n bit output of the M / n bit flip-flop and are delayed and output by the n / 2-speed clock are arranged in a structure in which the output of the front flip-flop is connected to the input of the rear flip-flop And (n / 2) -1 2M / n bit flip-flops for outputting M bits in combination with input signals of each flip-flop to be bypassed.

1A and 1B are diagrams illustrating system division for prototyping a system to be integrated into a semiconductor chip;

2 is a configuration diagram of a bus width reduction conversion circuit according to the present invention;

3 is a block diagram of a bus width reduction conversion circuit according to a first embodiment of the present invention;

4 is a signal timing diagram of the bus width reduction conversion circuit shown in FIG. 3;

5 is a configuration diagram of a bus width reduction conversion circuit according to a second embodiment of the present invention;

FIG. 6 is a signal timing diagram of the bus width reduction conversion circuit shown in FIG. 5; FIG.

There may be a plurality of embodiments of the present invention. Hereinafter, preferred embodiments will be described in detail with reference to the accompanying drawings. This embodiment allows for a better understanding of the objects, features and advantages of the present invention.

The bus width reduction conversion circuit according to the present invention is to reduce the bus width to M / n bits in the system for performing the signal transmission between blocks through the M bus width by receiving a reference clock as shown in the configuration of FIG. The encoding circuit 110 is inserted into a block for transmitting a signal and the decoding circuit 120 is inserted into a block for receiving a signal.

The encoding circuit 110 outputs an (n / 2) -1 bit counter 111 to which an n / 2-speed clock is applied and an M-bit signal to be input as an output signal of the (n / 2) -1 bit counter 111. The first multiplexer 113, which selects and outputs 2M / n bits, and the second multiplexer, which receives the output of the first multiplexer 113, selects by n / 2 times the clock and outputs M / n bits. It consists of 115.

The decoding circuit 120 receives the M / n bit signal output from the second multiplexer 115 and delays it by n / 2 times the clock to combine the 2 M / n bit signal with the bypassed M / n bit signal. Output M / n bit flip-flop 121 and 2M / n flip-flops that receive the 2M / n bit output of the M / n bit flip-flop 121 and are delayed by an n / 2-speed clock to output the front flip (N / 2) -1 2M / n bit flip-flops (n / 2) -1 which are arranged in a structure connected to the input of the rear flip-flop and output as M bits in combination with input signals of each flip-flop bypassed. 1, 123/2, ..., 123 / ((n / 2) -1) In the drawing, the connection point at which the bus line is reduced indicates the connection point at which the number of wiring lines is reduced in the FPGA.

In the bus width reduction conversion circuit according to the present invention configured as described above, the encoding circuit 110 positioned on the transmission block reduces and transmits the M bit signal to the M / n bit signal, and the decoding circuit 120 located on the reception block side Extends the M / n bit signal back to the M bit signal. In order to help understand the process of converting the bus width reduction, the following description will be given to the first embodiment and the second embodiment.

3 is a configuration diagram of a bus width reduction conversion circuit according to a first embodiment of the present invention, in which a 10-bit bus width is reduced to 5 bits of 1/2. Thus, when the bus width is reduced to 1/2, the (n / 2) -1 bit counter 111, the first multiplexer 113, and the 2M / n bit flip-flops 123-1, shown in FIG. 123/2, ..., 123 / ((n / 2) -1) are omitted, and it can be seen that the n / 2-speed clock is the same speed as the reference clock.

The operation of the bus width reduction conversion circuit shown in FIG. 3 will be described with reference to the signal timing diagram shown in FIG. 4.

First, the 10-bit input signal of the transmission block is input to each of the two input terminals of the multiplexer 211 in the encoding circuit 210 by 5 bits, respectively, the multiplexer 211 transmits 5 bits in the high phase period of the clock and low The remaining 5 bits are transmitted in the phase section.

Then, the 5-bit signal is transmitted to the receiving block, bypassed by the decoding circuit 220, and output. The negative-edge flip-flop 221 delays the 5-bit signal from the falling signal of the clock and outputs the delayed 5-bit signal. do.

As such, the receiving block can recover the original 10-bit signal by taking data in the low phase section of the clock.

5 is a configuration diagram of a bus width reduction conversion circuit according to a second embodiment of the present invention, in which an 8-bit bus width is reduced to 2 bits of 1/4. Since n is 4, the (n / 2) -1 bit counter 111 of FIG. 2 is embodied as a 1-bit counter 311, and (n / 2) -1 2M / n bit flip-flops 123-. It can be seen that 1, 123/2, ..., 123 / ((n / 2) -1) are embodied as one flip-flop, and the n / 2-speed clock uses a double-speed clock.

The operation of the bus width reduction conversion circuit shown in FIG. 5 will be described with reference to the signal timing diagram shown in FIG. 6.

First, the 8-bit input signal of the transmission block is input to the two input terminals of the first multiplexer 313 in the encoding circuit 310 by 4 bits, respectively, and the counter 311 receives the input signal of the first multiplexer 313. The first multiplexer 313 outputs four bits in one cycle of the double clock.

Next, the second multiplexer 315 receives two 4-bit outputs of the first multiplexer 313 into two input terminals, respectively, and transmits two bits in a high phase section of a double clock, and in a low phase section. Transmit the remaining two bits.

Then, the 2-bit signal is transmitted to the receiving block so that the negative-edge first flip-flop 321 of the decoding circuit 320 delays and outputs the 2-bit signal inputted from the falling signal of the double clock, thereby bypassing. The 4-bit signal is input to the second flip-flop 323 in combination with the 2-bit signal.

Next, the positive-edge second flip-flop 323 delays and outputs the 4-bit signal input from the rising signal of the double clock, so that the receiving block outputs the even-numbered low phase section of the double clock. In operation, the original 8-bit signal may be restored by taking a 4-bit signal bypassed with the output of the second flip-flop 323.

In the above description, but limited to one embodiment of the present invention, it is obvious that the technology of the present invention can be easily modified by those skilled in the art. Such modified embodiments should be included in the technical spirit described in the claims of the present invention.

As described above, the present invention uses an encoding circuit inserted on the transmitting side and a decoding circuit inserted on the receiving side to reduce the width of the bus for signal transmission between the divided blocks. It is effective to reduce.

Claims (2)

In a bus width reduction conversion circuit for reducing a bus width to M / n bits in a system that receives a reference clock and performs signal transmission between blocks through a M bit bus width, A (n / 2) -1 bit counter receiving an n / 2 times faster clock than the reference clock; A first multiplexer which selects an input M bit signal according to an output signal of the counter and outputs the 2 M / n bit; A second multiplexer which receives an output of the first multiplexer and selects the output of the first multiplexer by using an n / 2-speed clock and outputs M / n bits; M / n bit flip-flop that receives the M / n bit signal output from the second multiplexer and outputs 2M / n bit in combination with the bypassed M / n bit signal by delaying by n / 2 times the clock. ; 2M / n flip-flops that receive the 2M / n bit output of the M / n bit flip-flop and are delayed and output by the n / 2-speed clock are arranged in a structure in which the output of the front flip-flop is connected to the input of the rear flip-flop And (n / 2) -1 2M / n bit flip-flops for outputting M bits in combination with input signals of each flip-flop to be bypassed. In a bus width reduction conversion circuit for reducing a bus width to M / 2 bits in a system receiving a reference clock and performing signal transmission between blocks through a bus width of M bits, A multiplexer which selects an input M bit signal by the reference clock and outputs M / 2 bits in each of a high phase section and a low phase section of the reference clock; And a flip-flop that receives the M / 2 bit signal output from the multiplexer and outputs the M bit in combination with the bypassed M / 2 bit signal by being delayed by the reference clock.