KR20040085344A - Method for forming gate in semiconductor device - Google Patents
Method for forming gate in semiconductor device Download PDFInfo
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- KR20040085344A KR20040085344A KR1020030019992A KR20030019992A KR20040085344A KR 20040085344 A KR20040085344 A KR 20040085344A KR 1020030019992 A KR1020030019992 A KR 1020030019992A KR 20030019992 A KR20030019992 A KR 20030019992A KR 20040085344 A KR20040085344 A KR 20040085344A
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 239000010410 layer Substances 0.000 claims abstract description 57
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 229920005591 polysilicon Polymers 0.000 claims abstract description 26
- 239000011229 interlayer Substances 0.000 claims abstract description 10
- 125000006850 spacer group Chemical group 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 229910052721 tungsten Inorganic materials 0.000 claims description 20
- 239000010937 tungsten Substances 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 19
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 15
- 238000000059 patterning Methods 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- -1 tungsten nitride Chemical class 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 239000012535 impurity Substances 0.000 claims 1
- 238000007689 inspection Methods 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract 3
- 101001027622 Homo sapiens Protein adenylyltransferase FICD Proteins 0.000 abstract 1
- 102100037689 Protein adenylyltransferase FICD Human genes 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 description 15
- 238000000151 deposition Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
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- E—FIXED CONSTRUCTIONS
- E06—DOORS, WINDOWS, SHUTTERS, OR ROLLER BLINDS IN GENERAL; LADDERS
- E06B—FIXED OR MOVABLE CLOSURES FOR OPENINGS IN BUILDINGS, VEHICLES, FENCES OR LIKE ENCLOSURES IN GENERAL, e.g. DOORS, WINDOWS, BLINDS, GATES
- E06B7/00—Special arrangements or measures in connection with doors or windows
- E06B7/28—Other arrangements on doors or windows, e.g. door-plates, windows adapted to carry plants, hooks for window cleaners
- E06B7/36—Finger guards or other measures preventing harmful access between the door and the door frame
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- E—FIXED CONSTRUCTIONS
- E05—LOCKS; KEYS; WINDOW OR DOOR FITTINGS; SAFES
- E05Y—INDEXING SCHEME ASSOCIATED WITH SUBCLASSES E05D AND E05F, RELATING TO CONSTRUCTION ELEMENTS, ELECTRIC CONTROL, POWER SUPPLY, POWER SIGNAL OR TRANSMISSION, USER INTERFACES, MOUNTING OR COUPLING, DETAILS, ACCESSORIES, AUXILIARY OPERATIONS NOT OTHERWISE PROVIDED FOR, APPLICATION THEREOF
- E05Y2800/00—Details, accessories and auxiliary operations not otherwise provided for
- E05Y2800/40—Physical or chemical protection
- E05Y2800/41—Physical or chemical protection against finger injury
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- Engineering & Computer Science (AREA)
- Civil Engineering (AREA)
- Structural Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체소자의 게이트 형성방법에 관한 것으로, 보다 상세하게는 반도체 제조공정중 텅스텐을 이용하여 반도체소자의 게이트를 형성하는 방법에 관한 것이다.The present invention relates to a method of forming a gate of a semiconductor device, and more particularly, to a method of forming a gate of a semiconductor device using tungsten during a semiconductor manufacturing process.
종래의 게이트 형성방법을 설명하면 다음과 같다.A conventional gate forming method is described below.
먼저, 실리콘기판상에 게이트용 폴리실리콘층, 텅스텐질화막 또는 텅스텐막, 질화막 하드마스크층 및 SiON막을 순차적으로 적층한 후 상기 SiON막과 상기 질화막 하드마스크층을 식각하여 패터닝한다.First, a polysilicon layer for gate, a tungsten nitride film or a tungsten film, a nitride film hard mask layer, and a SiON film are sequentially stacked on a silicon substrate, and the SiON film and the nitride film hard mask layer are etched and patterned.
그 다음, 상기 패터닝된 질화막 하드마스크층을 마스크로 하여 게이트전극층으로 사용되는 상기 텅스텐막과 게이트물질층인 상기 폴리실리콘층을 식각하여 게이트를 형성한다.Next, a gate is formed by etching the tungsten film used as the gate electrode layer and the polysilicon layer, which is a gate material layer, using the patterned nitride film hard mask layer as a mask.
그러나, 이러한 종래의 게이트 식각기술은 질화막 하드마스크층, 텅스텐막과 폴리실리콘층등의 많은 층을 식각함으로 인해 FICD를 제어하는 어려움이 있으며, 또한 텅스텐막 식각을 위해 사용되는 플루오린 함유 가스가 폴리실리콘층에 대한 식각선택비가 낮음으로 인해 폴리실리콘층의 프로파일 및 식각량을 제어하기 어렵다는 문제점이 있다.However, such a conventional gate etching technique has difficulty in controlling FICD by etching many layers such as a nitride hard mask layer, a tungsten film, and a polysilicon layer, and the fluorine-containing gas used for etching tungsten film Due to the low etching selectivity with respect to the silicon layer, it is difficult to control the profile and the etching amount of the polysilicon layer.
또한, 식각장비의 상태에 따른 질화막 하드마스크층의 불규칙한 식각으로 인해 그 두께가 일정하게 형성되지 않아 후속의 SAC공정을 제어하기 어렵다는 문제점이 있다.In addition, due to the irregular etching of the nitride film hard mask layer according to the state of the etching equipment, there is a problem that it is difficult to control the subsequent SAC process because the thickness thereof is not formed uniformly.
또한, 상기 텅스텐막은 산화가 잘 일어나기 때문에 게이트패턴 형성 후 플라즈마에 의한 손상완화를 위한 열처리공정을 수행할 수 없으므로 소자특성이 열화되는 문제점이 있다.In addition, since the tungsten film is easily oxidized, a heat treatment process for alleviating damage by plasma may not be performed after the gate pattern is formed, thereby deteriorating device characteristics.
따라서, 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 게이트물질층인 폴리실리콘층만 먼저 증착하여 식각함으로써 FICD(Final Inspection Critical Dimension) 제어를 용이하게 할 수 있으며, 폴리실리콘층의 식각 후 열처리공정을 진행할 수 있어 소자특성 및 수율을 향상시킬 수 있는 반도체소자의 게이트 형성방법을 제공함에 그 목적이 있다.Therefore, the present invention has been made in order to solve the above problems of the prior art, it is possible to facilitate the FICD (Final Inspection Critical Dimension) control by depositing and etching only the polysilicon layer that is a gate material layer first, the polysilicon layer It is an object of the present invention to provide a method for forming a gate of a semiconductor device capable of performing a heat treatment process after etching to improve device characteristics and yield.
도 1a 내지 도 1i는 본 발명에 따른 반도체소자의 게이트 형성방법을 도시한 공정별 단면도.1A to 1I are cross-sectional views illustrating processes for forming a gate of a semiconductor device according to the present invention.
(도면의 주요부분에 대한 부호설명)(Code description of main parts of drawing)
100 : 반도체기판 120 : 폴리실리콘층100 semiconductor substrate 120 polysilicon layer
120a : 잔류 폴리실리콘층 140 : 측벽 스페이서120a: remaining polysilicon layer 140: sidewall spacer
160 : 층간절연막 170 : 제 1 리세스부분160: interlayer insulating film 170: first recessed portion
180 : 텅스텐막 180a : 잔류 텅스텐막180: tungsten film 180a: residual tungsten film
190 : 제 2 리세스부분 200, 200a : 절연막190: second recessed portion 200, 200a: insulating film
상기 목적을 달성하기 위한 본 발명은, 반도체기판상에 형성된 게이트물질층을 패터닝한 후 상기 패터닝된 게이트물질층 양측에 측벽스페이서를 형성하는 단계; 상기 게이트물질층과 측벽스페이서를 포함한 반도체기판상에 층간절연막을 형성한 후 이를 평탄화하여 상기 게이트물질층의 상면을 노출시키는 단계; 상기 노출된 게이트물질층 상부부분을 일부 제거하여 리세스하는 단계; 상기 리세스된 게이트물질층의 상부에 게이트전극층을 형성한 후 이를 평탄화하여 상기 게이트전극층 상면을 노출시키는 단계; 상기 노출된 게이트전극층 상부부분을 일부 제거하여 리세스하는 단계; 및 상기 리세스된 게이트전극층의 상부에 절연막을 형성한 후 이를 평탄화하는 단계를 포함하여 구성됨을 특징으로 한다.According to an aspect of the present invention, there is provided a method including: forming a sidewall spacer on both sides of a patterned gate material layer after patterning a gate material layer formed on a semiconductor substrate; Forming an interlayer insulating film on the semiconductor substrate including the gate material layer and sidewall spacers, and then planarizing the interlayer insulating film to expose an upper surface of the gate material layer; Removing a portion of the upper portion of the exposed gate material layer to recess the upper portion; Forming a gate electrode layer on the recessed gate material layer and then planarizing the gate electrode layer to expose an upper surface of the gate electrode layer; Removing a portion of the upper portion of the exposed gate electrode layer and recessing it; And forming an insulating film on the recessed gate electrode layer and then planarizing the insulating film.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1i는 본 발명에 따른 반도체소자의 게이트 형성방법을 도시한 공정별 단면도이다.1A to 1I are cross-sectional views illustrating processes of forming a gate of a semiconductor device according to the present invention.
먼저, 도 1a에 도시된 바와 같이, 반도체기판(100)상에 게이트용 폴리실리콘층을 후속의 텅스텐 및 질화막 하드마스크층의 두께 만큼 증착 및 패터닝하여 폴리실리콘 게이트(120)를 형성한 후, 플라즈마에 의한 손상을 완화하기 위해 열처리 산화공정을 실시한다.First, as shown in FIG. 1A, a polysilicon gate 120 is formed by depositing and patterning a gate polysilicon layer on the semiconductor substrate 100 by the thickness of a subsequent tungsten and nitride hardmask layer. A heat treatment oxidation process is performed to alleviate the damage caused.
그 다음, 도 1b 및 1c에 도시된 바와 같이, 상기 폴리실리콘 게이트(120)를 포함한 반도체기판(100)상에 게이트측벽으로 사용될 제 1 질화막(140)을 증착한 후 이를 식각하여 상기 폴리실리콘 게이트(120)의 양측에 질화막 스페이서(140)를 형성하고나서 상기 폴리실리콘 게이트(120)와 질화막 스페이서(140)를 마스크로 한 이온주입공정을 수행하여 접합영역(미도시)을 형성한다.1B and 1C, a first nitride film 140 to be used as a gate sidewall is deposited on the semiconductor substrate 100 including the polysilicon gate 120 and then etched to form the polysilicon gate. After forming the nitride film spacer 140 on both sides of the 120, an ion implantation process using the polysilicon gate 120 and the nitride film spacer 140 as a mask is performed to form a junction region (not shown).
이어서, 도 1d에 도시된 바와 같이, 상기 결과물의 전체상부에 층간산화막(160)을 증착한 후 상기 폴리실리콘 게이트(120)의 상면이 노출될 때 까지 상기 층간산화막(160)을 CMP(Chemical & Mechanical Polishing)방식에 의해 평탄화한다.Subsequently, as shown in FIG. 1D, the interlayer oxide layer 160 is deposited on the entire surface of the resultant material, and then the interlayer oxide layer 160 is deposited until the upper surface of the polysilicon gate 120 is exposed. Mechanical polishing).
그 다음, 도 1e에 도시된 바와 같이, 상기 폴리실리콘 게이트(120)의 상부부분을 산화막과 질화막의 높은 식각선택비를 갖는 조건으로 일부 식각하여 리세스함으로써 폴리실리콘 게이트(120a)를 잔류시켜 제 1 리세스부분(170)을 형성한다.Next, as shown in FIG. 1E, the upper portion of the polysilicon gate 120 is partially etched and recessed under conditions having a high etching selectivity between the oxide layer and the nitride layer to thereby retain the polysilicon gate 120a. 1 recess portion 170 is formed.
이때, 상기 폴리실리콘 게이트(120)의 일부 식각은 후속의 텅스텐막 증착두께와 SAC(Self Align Contact)공정에서 요구되는 제 2 질화막 증착두께 만큼 진행한다.In this case, some etching of the polysilicon gate 120 proceeds as much as the thickness of the subsequent deposition of the tungsten film and the thickness of the second nitride film required in the self alignment contact (SAC) process.
이어서, 도 1f에 도시된 바와 같이, 상기 제 1 리세스부분(170)을 포함한 결과물의 상부에 게이트전극 물질인 텅스텐막(W) 또는 텅스텐질화막(WN)(180)을 CVD방식으로 증착한다.Subsequently, as illustrated in FIG. 1F, a tungsten film (W) or a tungsten nitride film (WN) 180, which is a gate electrode material, is deposited on the resultant including the first recess portion 170 by CVD.
그 다음, 도 1g에 도시된 바와 같이, 상기 층간산화막(160)의 상면이 노출될 때 까지 상기 텅스텐막(180)을 CMP방식에 의해 평탄화한 후, 플루오린 함유 가스를 이용한 건식식각에 의해 상기 제 1 리세스부분(170)내 텅스텐막(180)의 상부부분을 일부 제거하여 리세스함으로써 텅스텐막(180a)을 잔류시켜 제 2 리세스부분(190)을 형성한다.Next, as shown in FIG. 1G, the tungsten film 180 is planarized by a CMP method until the top surface of the interlayer oxide film 160 is exposed, and then, by dry etching using a fluorine-containing gas, the tungsten film 180 is planarized. The upper portion of the tungsten film 180 in the first recessed portion 170 is partially removed and recessed, so that the tungsten film 180a is left to form the second recessed portion 190.
이어서, 도 1h 및 도 1i에 도시된 바와 같이, 상기 잔류 텅스텐막(180a)을 포함한 결과물의 상부에 후속의 SAC공정에 필요한 제 2 질화막(200)을 PECVD(Plasma Enhanced Chemical Vapor Deposition)방식에 의해 증착한 후 상기 층간산화막(160)의 상면이 노출될 때 까지 상기 제 2 질화막(200)을 CMP방식에 의해 평탄화시켜 상기 제 2 리세스부분(190)내에 제 2 질화막(200a)을 잔류시킨다.Subsequently, as shown in FIGS. 1H and 1I, the second nitride film 200 required for the subsequent SAC process on the top of the resultant product including the residual tungsten film 180a by PECVD (Plasma Enhanced Chemical Vapor Deposition) method. After the deposition, the second nitride film 200 is planarized by the CMP method until the upper surface of the interlayer oxide film 160 is exposed, thereby leaving the second nitride film 200a in the second recess portion 190.
상술한 바와 같이, 본 발명은 게이트물질로 게이트 폴리실리콘층만 먼저 증착하여 식각함으로써 FICD 제어를 용이하게 할 수 있으며, 게이트 폴리실리콘츠의 식각 후 열처리를 실시할 수 있게 됨으로써 소자특성 및 수율향상에 기여할 수 있다는 효과가 있다.As described above, the present invention can facilitate FICD control by first depositing and etching the gate polysilicon layer as the gate material, and improving the device characteristics and yield by performing heat treatment after etching the gate polysilicon. The effect is that you can contribute.
또한, 후속의 SAC공정에서 요구되는 제 2 질화막이 일정 두께로 조절될 수 있어 수율이 개선되는 효과가 있다.In addition, since the second nitride film required in the subsequent SAC process can be adjusted to a predetermined thickness, the yield is improved.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
Claims (8)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030019992A KR20040085344A (en) | 2003-03-31 | 2003-03-31 | Method for forming gate in semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030019992A KR20040085344A (en) | 2003-03-31 | 2003-03-31 | Method for forming gate in semiconductor device |
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| KR20040085344A true KR20040085344A (en) | 2004-10-08 |
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2003
- 2003-03-31 KR KR1020030019992A patent/KR20040085344A/en not_active Application Discontinuation
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