KR20040084510A - Mode start circuit and method using code matching method - Google Patents

Abstract

PURPOSE: A mode access circuit using a code matching method and a method for the same are provided to reduce the number of mode access pins by using a serial interface. CONSTITUTION: An internal clock signal generator(10) is used for receiving an external clock signal and a reset signal and generating an internal clock signal. An edge detector(20) is used for detecting an edge of the reset signal. A clear signal generator(30) is used for receiving a matching signal of N-bit data and an output signal of the edge detector and generating a clear signal. An N-bit data storage unit(40) receives and stores data from the outside in response to the internal clock signal and is reset by the clear signal. A matching decision unit(50) compares the N-bit data with a stored code value and generates a data matching signal. A mode signal generator(60) is used for generating a mode signal by an output signal of the matching decision unit and an output signal of the clear signal generator.

Description

Mode entry circuit and method using code matching {MODE START CIRCUIT AND METHOD USING CODE MATCHING METHOD}

The present invention relates to a method of entering a specific mode, such as a test mode, and more specifically, a mode entry circuit using code matching that can secure the stability of circuit operation by preventing the occurrence of errors during mode entry using code matching. And to a method.

In order to ensure the operational stability of various modes such as the test mode of the circuit, the switching method to the corresponding operation mode is very important. These modes must be protected from error signals and hatching, such as noise or glitches in the input signal.

A method of entering a specific mode which is most applied in various conventional circuits is a method of decoding a state of a plurality of pins in a reset section and determining a desired mode according to the decoding result. Such a mode entry method has been widely used because of its simple circuit configuration, which is vulnerable to error signals such as external noise and glitches, and is easily hacked.

For example, in the conventional method of entering a specific mode, when the reset signal of the chip is disabled, the state conditions of the mode selection pins A, B, C, and D are When the low state L, the low state, the low state and the high state H are satisfied, the mode A is determined and the operation of the mode A is performed. On the other hand, if the state of the mode selection pins A, B, C, and D satisfies the low state, low state, high state and low state, respectively, at the moment when the reset signal of the chip is disabled, the mode B is determined to be mode B. Performs the operation of.

However, in the conventional mode entry method, if the state condition of the mode selection pins coincides with the condition for determining the specific mode by chance during normal chip reset operation, the chip transitions to an undesired operation mode and the system malfunctions. There was a problem.

Accordingly, an object of the present invention is to provide an operation entry circuit and a method using a code matching method which can maintain the security of a circuit due to noise and the like.

Another object of the present invention is to provide an operation entry circuit and a method capable of preventing a malfunction of a system by allowing entry into a specific operation mode using a code matching method.

Another object of the present invention is to provide an operation entry circuit and a method using a code matching method for setting a test mode and a program mode of a chip in various ways by reducing the number of pins used to enter various modes.

1 is a block diagram of a mode entry circuit using a code matching method according to an embodiment of the present invention;

2 is an operation waveform diagram for explaining a mode entry method using the code matching method of the present invention;

* Description of the symbols for the main parts of the drawings *

10: internal clock signal generation means 20: edge detection means

30: clear signal generating means 40: N-bit data storage means

50: matching discrimination means for N-bit data 60: mode signal generating means

In order to achieve the above object, the present invention comprises: an internal clock signal generation means for generating an internal clock signal by inputting a clock signal and a reset signal applied from the outside; Edge detecting means for detecting an edge of the reset signal; Clear signal generation means for inputting a matching signal of N-bit data and an output signal of the edge detection means to generate a clear signal; N-bit data storage means for inputting and storing data from the outside in response to the internal clock signal generated by the internal clock signal generation means, and being reset by the clear signal generated from the clear signal generation means; Matching discrimination means for N-bit data for generating a data matching signal by comparing the N-bit data provided from said N-bit data storage means with a code value for a specific mode previously stored; A mode entry circuit using a code matching method comprising a mode signal generating means for generating a mode signal by the output signal of the matching discriminating means of the N-bit data and the output signal of the clear signal generating means is provided.

The internal clock signal generating means comprises an AND gate for generating an internal clock signal by using a clock signal and a reset signal applied from the outside, and the edge detecting means is configured to detect rising edges of the reset signal. A rising edge detector; And a falling edge detector for detecting a falling edge of the reset signal. The clear signal generating means includes an AND gate having two inputs, a data matching signal and an output signal of a falling edge detector of the edge detection means; The output signal of the AND gate and the output signal of the rising edge detector of the edge detection means are NOR gates having two inputs.

In addition, the N-bit data storing means shifts the data applied from the outside in response to the internal clock signal generated from the internal clock signal generating means and provides the N-bit data to the matching discriminating means of the N-bit data. It consists of an N-bit shift register reset by a clear signal generated by. The matching means for discriminating the N-bit data includes an N-bit data register for storing a code value for a specific mode; And a comparator for outputting a data matching signal by comparing the code value for the specific mode stored in the data register with the N-bit data provided from the N-bit data storage means. The mode signal generating means comprises an RS flip-flop which is set and reset respectively by an output signal of the matching discriminating means of the N-bit data and an output signal of the clear signal generating means to generate a mode signal.

In addition, the present invention comprises the steps of generating an internal clock signal by inputting a clock signal and a reset signal applied from the outside; Inputting and storing data from the outside in response to the internal clock signal; Comparing the N-bit data with a code value for a specific mode previously stored; Generating a mode signal when the comparison result is matched; If the result of the comparison does not match, a mode entry method using a code matching method comprising the step of disabling the mode signal is provided.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram of a mode entry circuit using a code matching method according to an embodiment of the present invention.

Referring to FIG. 1, the mode entry circuit using the code matching method of the present invention includes an internal clock signal generating means 10, an edge detecting means 20, a clear signal generating means 30, and an N-bit data storing means 40. ), Matching means for discriminating N-bit data 50 and mode signal generating means 60.

The internal clock signal generating means 10 includes an end gate for generating an internal clock signal CIN by inputting a clock signal CEXT and a reset signal RST applied from the outside, and the edge detecting means 20. ) Is a rising edge detector 21 for detecting a rising edge of the reset signal RST, and a falling edge detector for detecting a falling edge of the reset signal RST. 22).

The clear signal generating means 30 includes an AND gate 31 having two input signals of a matching signal MTCB of N-bit data and an output signal of the falling edge detector 22 of the edge detecting means 20, The output signal of the AND gate 31 and the output signal of the rising edge detector 22 of the edge detecting means 20 are composed of a NOR gate 32 having two inputs.

The N-bit data storage means 40 shifts a specific data value of the N-bit provided as input data DIN in response to the internal clock signal CIN generated from the internal clock signal generation means 10, The shift register is reset by the clear signal CLRB generated from the clear signal generating means 30.

The matching means for discriminating the N-bit data 50 includes a data register for storing a code value for a specific mode, a code value for a specific mode stored in the data register and the N-bit data storage means 40. Comparing the provided N-bit data to determine whether the data match.

The mode signal generating means 60 is connected to the output signal MCCB of the matching discriminating means 50 of the N-bit data and the output signal CLRB of the clear signal generating means 30 inverted through the inverter 61. RS flip-flops that are set and reset respectively to generate a mode signal MODE.

The operation of the mode entry circuit using the code matching method of the present invention having the configuration as described above will be described with reference to the waveform diagram of FIG.

First, when the reset signal RST transitions from the low state to the high state in the reset period, which is the initialization period, the rising edge detector 21 of the edge detecting means 20 raises the rising edge of the reset signal RST. It detects and outputs high signal. The clear signal detecting means 30 inputs a high state output signal from the rising edge detector 210 of the edge detecting means 20 to generate a low clear signal CLRB through the NOR gate 32. Accordingly, the RS flip-flop, which is the matching discrimination means 60 of the shift register and the N-bit data, which is the N-bit data storage means 40, is initialized.

After initialization, the AND gate of the internal clock signal generation means 10 inputs an external clock signal CEXT to generate an internal clock signal CIN, and the N-bit shift register 40 generates the AND gate 10. N-bit data DIN input from the outside is stored in response to the internal clock signal CIN.

As shown in the waveform diagram of FIG. 2, the shift register 40 inputs and shifts external data DIN in response to the internal clock signal CIN only in a section in which a reset signal RST is in a high state. The matching discrimination means 50 of the N-bit data is provided.

The matching means for discriminating the N-bit data 50 stores a code value for a specific mode in an N-bit data register in advance, and when N-bit data is provided from the shift register 40, it is stored in a data register. The code value for a particular mode is compared with the N-bit data provided from the shift register 40 through a comparator.

Therefore, each time the internal clock signal CIN is applied, the shift register 40 inputs and shifts the data DIN to provide the matching discrimination means 50 of the N-bit data, and the N-bit. The data matching and discriminating means 50 repeats the operation of comparing the N-bit data provided from the shift register 40 with a code value for a specific mode stored in advance.

As a result of the data comparison, when the N-bit data provided from the shift register 40 and the code value for the specific mode stored in advance match, the matching discrimination means 50 of the N-bit data generates a high state signal. do. The output signal of the matching discrimination means 50 is inverted through the inverter 65 and applied to the set terminal SETB of the mode signal generating means 60 as the data matching signal MTCB, and at the same time, the clear signal generating means 30 is provided. Is provided.

Therefore, the RS flip-flop of the mode signal generating means 60 is set to generate the mode signal MODE in the high state. On the other hand, the AND gate 31 of the clear signal generating means 30 inputs the data matching signal MTCB in the low state and outputs the low state signal to the NOR gate 32, so that the clear signal generating means 30 Subsequently, a high clear signal CLRB is generated. Accordingly, the clear signal CLRB provided to the N-bit shift register 40 and the RS flip-flop 60 is blocked to maintain the high mode signal MODE. do.

As such, the data matching signal MTCB in the low state is generated through the matching discrimination means 50, and the reset section is terminated when the mode signal generating means 60 generates the mode signal MODE. When the signal RST transitions from the high state to the low state, the falling edge detector 22 of the edge detecting means 20 detects the falling edge.

On the other hand, as a result of comparing the data through the matching determination means 50, when the output data of the N-bit shift register 40 and the code value for the specific mode stored in advance do not match, the data matching signal (MTCB) is It goes high. At this time, when the reset signal RST transitions from the high state to the low state, the high falling edge detection signal output from the falling edge detector 22 of the edge detecting means 20 is clear signal generating means 30. And gate 31 is provided. Therefore, the AND gate 31 inputs the data matching signal MTCB of the high state and the falling edge detection signal of the high state to provide the output signal of the high state to the NOR gate 32, so that the clear signal generating means 30 The N-bit shift register 40 and the RS flip-flop 60 are cleared by outputting a low clear signal CLRB. Accordingly, since the RS flip-flop 60 generates the mode signal MODE in the low state, mode entry is disabled.

As described above, the mode entry circuit of the present invention is used as a 1-bit data pin (DIN) for inputting specific data from the outside, a clock pin (CEXT) for inputting a clock signal from the outside, and a code matching detection determination section. It consists of a 3-bit input pin of the reset pin (RST) for inputting the reset signal, and an output pin of 1 bit of the mode pin (MODE PIN) that generates a mode signal indicating whether the mode has been entered. By determining the operation mode of the chip in the reset period, the operation of various modes of the chip is assured to the maximum.

According to the embodiment of the present invention as described above, the number of pins required to enter the mode can be reduced to two by using the serial interface to enter the various modes required for driving the chip, and thus the configuration of the various modes. Since this is possible, there is an advantage that the test mode and the program mode of the chip can be set in various ways. In addition, it is possible to enter a specific mode only when data that matches a predetermined code value is input, thereby preventing the specific mode of the chip from being disclosed due to external factors such as noise or hacking. It is very effective in maintaining security.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (8)

Internal clock signal generation means for inputting a clock signal and a reset signal applied from the outside to generate an internal clock signal; Edge detection means for detecting an edge of the reset signal; Clear signal generating means for inputting a matching signal of N-bit data and an output signal of the edge detection means to generate a clear signal; N-bit data storage means for inputting and storing data from the outside in response to the internal clock signal generated from the internal clock signal generation means, and being reset by the clear signal generated from the clear signal generation means; Matching means for discriminating N-bit data which generates a data matching signal by comparing the N-bit data provided from said N-bit data storage means with a code value for a specific mode previously stored; And Mode signal generating means for generating a mode signal by the output signal of the matching discriminating means of the N-bit data and the output signal of the clear signal generating means. Mode entry circuit using a code matching method characterized in that it comprises a. The method of claim 1, And the internal clock signal generating means comprises an AND gate for generating an internal clock signal using two clock signals and a reset signal applied from the outside. The method of claim 1, The edge detection means A rising edge detector for detecting a rising edge of the reset signal; And And a falling edge detector for detecting a falling edge of the reset signal. The method of claim 3, wherein The clear signal generating means An AND gate having two inputs, a data matching signal and an output signal of a falling edge detector of the edge detection means; And a Noah gate having two inputs, an output signal of the AND gate and an output signal of the rising edge detector of the edge detection means. The method of claim 1, The N-bit data storing means shifts the data applied from the outside in response to the internal clock signal generated from the internal clock signal generating means, and provides the N-bit data to the matching discriminating means of the N-bit data. A mode entry circuit using a code matching method, comprising: an N-bit shift register reset by a generated clear signal. The method of claim 1, The matching discrimination means of the N-bit data An N-bit data register for storing code values for specific modes; And A mode entry circuit using a code matching method, comprising: a comparator for comparing a code value for a specific mode stored in the data register with N-bit data provided from the N-bit data storage means and outputting a data matching signal; . The method of claim 1, And the mode signal generating means comprises an RS flip-flop which is set and reset by an output signal of the matching discriminating means of the N-bit data and an output signal of the clear signal generating means, respectively, to generate a mode signal. Mode entry circuit using Generating an internal clock signal by inputting a clock signal and a reset signal applied from the outside; Inputting and storing data from the outside in response to the internal clock signal; Comparing the N-bit data with a code value for a specific mode previously stored; Generating a mode signal if the comparison result is matched; And Disabling the mode signal if the comparison result does not match Mode entry method using a code matching method characterized in that it comprises a.