KR20040084225A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
KR20040084225A
KR20040084225A KR1020030019134A KR20030019134A KR20040084225A KR 20040084225 A KR20040084225 A KR 20040084225A KR 1020030019134 A KR1020030019134 A KR 1020030019134A KR 20030019134 A KR20030019134 A KR 20030019134A KR 20040084225 A KR20040084225 A KR 20040084225A
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KR
South Korea
Prior art keywords
active region
word line
semiconductor device
width
bit line
Prior art date
Application number
KR1020030019134A
Other languages
Korean (ko)
Inventor
김대식
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020030019134A priority Critical patent/KR20040084225A/en
Publication of KR20040084225A publication Critical patent/KR20040084225A/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor

Abstract

PURPOSE: A semiconductor device is provided to be capable of reducing parasitic capacitance between a word line and a bit line. CONSTITUTION: An I-type active region(100) is formed on a semiconductor substrate. A word line(200) including an overlap portion and a non-overlap portion to the active region is elongated vertically to the I-type active region. At this time, the width of the overlap portion is narrower than the width of the non-overlap portion. A bit line(300) is elongated parallel to the I-type active region.

Description

반도체 소자{SEMICONDUCTOR DEVICE}Semiconductor device {SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자에 관한 것으로, 특히 활성 영역 상부의 워드 라인의 폭을 작게 형성함으로써 워드라인과 비트라인 사이의 캐패시턴스를 감소시켜 향상된 특성을 가지는 반도체 소자에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having improved characteristics by reducing the capacitance between the word line and the bit line by making the width of the word line above the active region small.

도 1은 종래 기술에 따른 반도체 소자를 도시한 평면도이며, 도 3은 도 1의 랜딩 플러그(50) 및 그 주변을 확대하여 도시한 평면도이다.1 is a plan view illustrating a semiconductor device according to the related art, and FIG. 3 is an enlarged plan view of the landing plug 50 and its periphery of FIG. 1.

도 1을 참조하면, 반도체 기판 상부에 I형 활성 영역(10)이 구비되어 있으며, 활성 영역(10) 상부에 활성 영역(10)과 수직하게 연장되는 워드라인(20)이 형성되어 있다. 도 3에 도시된 바와 같이, 워드라인(20)과 랜딩 플러그(50) 사이의간격은 랜딩 플러그(50)와 워드라인(20)의 간격은 d2이다. 워드 라인(20)에 수직하며 활성 영역(10)에 평행하게 연장되는 비트라인(30)이 구비되어 있다.Referring to FIG. 1, an I-type active region 10 is provided on a semiconductor substrate, and a word line 20 extending perpendicular to the active region 10 is formed on the active region 10. As shown in FIG. 3, the spacing between the word line 20 and the landing plug 50 is d 2 between the landing plug 50 and the word line 20. A bit line 30 is provided that is perpendicular to the word line 20 and extends parallel to the active region 10.

상술한 종래 기술에 따른 반도체 소자는 랜딩 플러그의 측벽과 인접하는 워드라인 측벽과의 인접 효과에 의하여 워드라인과 비트라인 사이의 기생 캐패시턴스가 증가하게 된다는 문제점이 있다.The semiconductor device according to the related art described above has a problem in that parasitic capacitance between the word line and the bit line is increased due to the adjacent effect between the sidewall of the landing plug and the adjacent wordline sidewall.

상기 문제점을 해결하기 위하여, 활성 영역과 중첩되는 부분의 워드라인 폭을 중첩되지 않는 부분의 워드라인 폭보다 작게 형성함으로써 워드라인과 비트라인 사이의 기생 캐패시턴스를 감소시켜 향상된 특성을 가지는 반도체 소자를 제공하는 것을 그 목적으로 한다.In order to solve the above problems, by forming the word line width of the portion overlapping the active region smaller than the word line width of the non-overlapping portion, the parasitic capacitance between the word line and the bit line is reduced to provide a semiconductor device having improved characteristics. It is for that purpose.

도 1은 종래 기술에 따른 반도체 소자를 도시한 평면도.1 is a plan view showing a semiconductor device according to the prior art.

도 2는 본 발명에 따른 반도체 소자를 도시한 평면도2 is a plan view showing a semiconductor device according to the present invention

도 3은 도 1의 랜딩 플러그(50) 및 그 주변을 확대하여 도시한 평면도3 is an enlarged plan view of the landing plug 50 and its periphery of FIG. 1.

도 4는 도 2의 랜딩 플러그(500) 및 그 주변을 확대하여 도시한 평면도4 is an enlarged plan view of the landing plug 500 and its periphery of FIG. 2.

본 발명에 따른 반도체 소자는 반도체 기판 상부에 형성된 I형 활성 영역과, 상기 활성 영역과 수직하게 연장되며, 상기 활성 영역과 중첩되는 부분의 폭이 상기 활성 영역과 중첩되지 않는 부분의 폭보다 작은 워드라인 및 상기 워드 라인에 수직하며 상기 활성 영역에 평행하게 연장되는 비트라인을 포함하는 것을 특징으로 한다.According to the present invention, a semiconductor device includes a I-type active region formed on an upper surface of a semiconductor substrate, a word extending vertically to the active region, and a width of a portion overlapping with the active region is smaller than a width of a portion not overlapping with the active region. And a bit line perpendicular to the line and the word line and parallel to the active region.

이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

도 2는 본 발명에 따른 반도체 소자를 도시한 평면도이며, 도 4는 도 2의 랜딩 플러그(500) 및 그 주변을 확대하여 도시한 평면도이다.2 is a plan view illustrating a semiconductor device according to the present invention, and FIG. 4 is an enlarged plan view of the landing plug 500 and its periphery of FIG. 2.

도 2를 참조하면, 반도체 기판 상부에 I형 활성 영역(100)이 구비되어 있으며, 활성 영역(100) 상부에 활성 영역(100)과 수직하게 연장되는 워드라인(200)이 형성되어 있다. 여기서, 워드라인(200)은 활성 영역(100)과 중첩되는 부분의 폭이 활성 영역(100)과 중첩되지 않는 부분의 폭보다 작도록 형성된다. 즉, 도 4에 도시된 바와 같이, 랜딩 플러그(500)와 워드라인(200)의 간격은 d2로서 도 3의 d1보다 크므로, 랜딩 플러그(500)와 워드라인(200) 사이의 절연막의 두께가 증가하여 기생 캐패시턴스는 감소하게 된다. 또한, 워드 라인(200)에 수직하며 활성 영역(100)에 평행하게 연장되는 비트라인(300)이 구비되어 있다. 여기서, 비트라인(300)은 랜딩 플러그(500)에 의하여 활성 영역(100)과 전기적으로 접속된다.Referring to FIG. 2, an I-type active region 100 is provided on a semiconductor substrate, and a word line 200 extending perpendicular to the active region 100 is formed on the active region 100. Here, the word line 200 is formed such that the width of the portion overlapping with the active region 100 is smaller than the width of the portion not overlapping with the active region 100. That is, as shown in FIG. 4, the distance between the landing plug 500 and the word line 200 is greater than d 1 of FIG. 3 as d 2 , and thus, an insulating film between the landing plug 500 and the word line 200. The parasitic capacitance decreases with increasing thickness. In addition, a bit line 300 perpendicular to the word line 200 and extending parallel to the active region 100 is provided. Here, the bit line 300 is electrically connected to the active region 100 by the landing plug 500.

본 발명에 따른 반도체 소자는 활성 영역과 중첩되는 부분의 워드라인 폭을 중첩되지 않는 부분의 워드라인 폭보다 작게 형성함으로써 워드라인과 비트라인 사이의 기생 캐패시턴스를 감소시켜 향상된 특성을 제공한다.The semiconductor device according to the present invention provides improved characteristics by reducing the parasitic capacitance between the word line and the bit line by forming the word line width of the portion overlapping the active region smaller than the word line width of the non-overlapping portion.

Claims (1)

반도체 기판 상부에 형성된 I형 활성 영역;An I-type active region formed on the semiconductor substrate; 상기 활성 영역과 수직하게 연장되며, 상기 활성 영역과 중첩되는 부분의 폭이 상기 활성 영역과 중첩되지 않는 부분의 폭보다 작은 워드라인; 및A word line extending perpendicular to the active region and having a width of a portion overlapping with the active region being smaller than a width of a portion not overlapping with the active region; And 상기 워드 라인에 수직하며 상기 활성 영역에 평행하게 연장되는 비트라인A bit line perpendicular to the word line and extending parallel to the active region 을 포함하는 것을 특징으로 하는 반도체 소자.A semiconductor device comprising a.
KR1020030019134A 2003-03-27 2003-03-27 Semiconductor device KR20040084225A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100719379B1 (en) * 2006-03-30 2007-05-17 삼성전자주식회사 Nonvolatile memory device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100719379B1 (en) * 2006-03-30 2007-05-17 삼성전자주식회사 Nonvolatile memory device
US7989869B2 (en) 2006-03-30 2011-08-02 Samsung Electronics Co., Ltd. Non-volatile memory devices having improved operational characteristics
US8610192B2 (en) 2006-03-30 2013-12-17 Samsung Electronics Co., Ltd. Non-volatile memory devices having charge storage layers at intersecting locations of word lines and active regions

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