KR20040077174A - Apparatus and method driving of liquid crystal display device - Google Patents

Abstract

PURPOSE: An apparatus for driving a liquid crystal display device and a method therefor are provided to improve definition by changing driving method of an LCD according to input signal. CONSTITUTION: An apparatus for driving a liquid crystal display device includes a liquid crystal panel(102), a system(130), a determination unit, a data driving unit and a gate driving unit. The liquid crystal panel(102) is provided with a plurality of liquid crystal cells arranged in the form of matrix. The system(130) supplies images to the liquid crystal panel(102). The determination unit determines whether the image signal is a dynamic image or a still image. The data driving unit supplies the image signal to the liquid crystal panel(102) in response to the determination signal of the determination unit. And, the gate driving unit supplies the scan signal to the liquid crystal panel in response to the determination signal of the determination unit.

Description

A device and method for driving a liquid crystal display device {APPARATUS AND METHOD DRIVING OF LIQUID CRYSTAL DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device and a method of a liquid crystal display device, and more particularly to a driving device and a method of a liquid crystal display device in which a driving method of a liquid crystal panel can be changed according to an input signal.

An active matrix drive type liquid crystal display device (LIQUID CRYSTALDISPLAY: referred to as "LCD") displays a natural moving image using a thin film transistor ("TFT") as a switching element. . Such a liquid crystal display device can be miniaturized compared to a CRT and commercialized as a monitor such as a portable television or a laptop-type personal computer.

An LCD of an active matrix type displays an image corresponding to a video signal such as a television signal on a pixel matrix (Picture Element Matrix or Pixel Matrix) in which pixels are arranged at intersections of gate lines and data lines. Each of the pixels includes a liquid crystal cell that adjusts the amount of transmitted light according to the voltage level of the data signal from the data line. The TFT is provided at the intersection of the gate line and the data lines to switch the data signal to be transmitted toward the liquid crystal cell in response to the scan signal (gate pulse) from the gate line.

Such LCDs are connected to data lines and gate lines, and are provided with a plurality of driving integrated circuits (D-ICs) for supplying data signals and scan signals to data lines and gate lines, respectively. Will be required. The D-ICs are installed between the printed circuit board (hereinafter referred to as "PCB") and the liquid crystal panel to scan data signals and scan data lines and gate lines of the liquid crystal panel in response to control signals supplied from the PCB. Will supply a signal. As a method of mounting D-ICs, a tape automated bonding method ("TAB"), which can increase the effective area of a panel and has a relatively simple mounting process, is most commonly used.

Referring to FIG. 1, a conventional LCD includes a liquid crystal panel 2 having a liquid crystal cell formed at each intersection of gate lines GL1 to GLn and data lines DL1 to DLm, and a data line of the liquid crystal panel 2. A plurality of data tape carrier packages 10 and a plurality of data tape carrier packages that are connected to the respective ones DL1 to DLm and are mounted with data D-ICs 8 for driving the data lines DL1 to DLm. A gate D-IC 12 connected to the data PCB 6 connected to the 10 and the gate lines GL1 to GLn of the liquid crystal panel 2 and for driving the gate lines GL1 to GLn. ) Are mounted on a plurality of gate tape carrier packages 14, a gate PCB 4 connected to a plurality of gate tape carrier packages 14, and a plurality of data D-ICs 8 disposed on the data PCB 6. ) And a timing controller 20 for controlling the gate D-IC 12.

The liquid crystal panel 2 is formed at each intersection of the liquid crystal cells arranged in a matrix form and the gate lines GL1 to GLn and the data lines DL1 to DLm, and is connected to each of the liquid crystal cells TFT. ).

The thin film transistor TFT is turned on when the scan signal from the gate line GL, that is, the gate high voltage VGH is supplied, and supplies the pixel signal from the data line DL to the liquid crystal cell. The thin film transistor TFT is turned off when the gate low voltage VGL is supplied from the gate line GL to maintain the pixel signal charged in the liquid crystal cell.

The liquid crystal cell is equivalently represented by a liquid crystal capacitor Clc, and includes a common electrode facing the liquid crystal and a pixel electrode connected to the thin film transistor TFT. The liquid crystal cell further includes a storage capacitor Cst so that the charged pixel signal is stably maintained until the next pixel signal is charged. The storage capacitor Cst is formed between the pixel electrode and the previous gate line. The liquid crystal cell realizes gray scale by adjusting light transmittance by changing an arrangement state of liquid crystal having dielectric anisotropy according to a pixel signal charged through a thin film transistor (TFT).

The timing controller 20 generates gate control signals GSP, GSC, and GOE to control the plurality of gate D-ICs 12, and generates data control signals SSP, SSC, SOE, and POL. To control the data D-IC (8). In addition, the timing controller 20 aligns the pixel data R, G, and B to supply the plurality of data D-ICs 8.

Each of the plurality of gate D-ICs 12 sequentially applies the gate high voltage VGH to the gate lines GL1 to GLn in response to the gate control signals GSP, GSC, and GOE from the timing controller 20. Supply. Accordingly, each of the plurality of gate D-ICs 12 causes the thin film transistor TFT connected to the gate lines GL1 to GLn to be driven in units of the gate line GL.

Specifically, each of the plurality of gate D-ICs 12 shifts the gate start pulse GSP according to the gate shift pulse GSC to generate a shift pulse. Each of the plurality of gate D-ICs 12 supplies the gate high voltage VGH to the corresponding gate line GL for each horizontal period H1, H2,... In response to the shift pulse. In this case, each of the plurality of gate D-ICs 12 supplies the gate high voltage VGH only during the enable period in response to the gate output enable signal GOE. Each of the plurality of gate D-ICs 12 supplies the gate low voltage VGL in the remaining period in which the gate high voltage VGH is not supplied to the gate lines GL1 through GLn. In addition, each of the plurality of gate D-ICs 12 supplies a gate low voltage VGL to a gate line (not shown) formed at the uppermost side for the storage capacitor Cst of the first scan line.

Each of the plurality of data D-ICs 8 corresponds to one line for each horizontal period H1, H2, ... in response to the data control signals SSP, SSC, SOE, and POL from the timing controller 20. The pixel signal is supplied to the data lines DL1 to DLm. In particular, each of the plurality of data D-ICs 8 uses the digital pixel data R, G, and B from the timing controller 20 by using a gamma voltage from a gamma voltage generator (not shown). To be supplied.

Specifically, each of the plurality of data D-ICs 8 generates a sampling signal by shifting the source start pulse SSP according to the source shift clock SSC. Subsequently, each of the plurality of data D-ICs 8 sequentially receives and latches the pixel data signals R, G, and B in predetermined units in response to the sampling signal. Each of the plurality of data D-ICs 8 converts the latched one-line pixel data R, G, and B into an analog pixel signal and supplies them to the data lines DL1 through DLm. In this case, each of the plurality of data D-ICs 8 is converted into the positive and negative pixel signals in response to the polarity control signal POL.

In such an LCD, three types of frame inversion method, line inversion method, and dot inversion method are used to drive the liquid crystal cells LC on the liquid crystal panel 2. The driving method is mainly used.

The liquid crystal panel driving method of the frame inversion method inverts the polarity of the data signal supplied to the liquid crystal cells whenever the frame is changed. In the line inversion type liquid crystal panel driving method, polarities of data signals supplied to liquid crystal cells are reversed according to a line on the liquid crystal panel, that is, a gate line.

In the dot inversion scheme, data signals having opposite polarities are supplied to adjacent liquid crystal cells, and polarities of data signals supplied to the liquid crystal cells are inverted every frame. Among the three liquid crystal panel driving methods, the dot inversion method is configured to supply a liquid crystal cell by supplying a data signal having a polarity opposite to the data signals supplied to adjacent liquid crystal cells in the vertical and horizontal directions. Compared with the line inversion schemes, it provides an image of superior image quality.

In the LCD using the 1-dot inversion method, polarity pulses and data output enable signals are input to the plurality of data D-ICs 8 as shown in FIG. 2. In the one-dot inversion scheme, the data output enable signal input to the data D-IC 8 has a frequency twice the polarity pulse. The data D-IC 8 receiving the polarity pulse and the data output enable signal supplies the video signal to the data lines DL1 to DLm in synchronization with the falling edge (or rising edge) of the data output enable signal. In this case, in the video signal supplied from the data D-IC 8 to the data lines DL1 through DLm, positive and negative polarities are alternately shown in FIG. 2. In addition, the gate output enable signal having the same frequency as the data output enable signal is supplied to the gate D-IC 12, and the gate D-IC 12 uses the gate output enable signal supplied thereto to gate the output signal. The driving pulses are generated, and the generated gate driving pulses are sequentially supplied to the gate lines GL1 to GLn. The LCD driving method using the 1-dot inversion method is positioned adjacent to each other with the liquid crystal cell LC positioned adjacent to each other with the gate lines GL1 to GLn interposed therebetween, and the data lines DL1 to DLm interposed therebetween. The opposite polarity data signals are supplied to all of the liquid crystal cells LC to display an image.

However, this one-dot inversion method consumes a lot of power since the polarities of all adjacent liquid crystal cells are different. To compensate for this drawback, a two-dot inversion scheme is used.

Similarly, in the LCD using the line inversion method, as shown in FIG. 3, the positive, positive, negative and negative polarities are alternately repeated on the horizontal axis of the liquid crystal panel 2, and the positive and negative polarities are on the vertical axis. Signal is repeated alternately. Therefore, the power consumption can be reduced compared to the one-dot inversion method in which opposite polarities are supplied to all of the liquid crystal cells LC.

The LCD driving method according to the related art drives the liquid crystal cell of the liquid crystal panel 2 in response to the polarity pulse supplied from the timing controller 20 regardless of the type of the input signal supplied to the data D-IC. do. That is, the LCD driving method according to the related art drives the liquid crystal cell in the one-dot inversion method when the polarity pulse from the timing controller 20 is the one-dot inversion method, and lines the liquid crystal cell in the line inversion method. It will run in inversion mode.

In the LCD driving method according to the related art, the 1-dot inversion driving method shows excellent image quality in the case of a still image, while desired data is changed in one frame when data is changed from one level to another level with a slow response time when the video is implemented. The luminance cannot be reached so that the desired color and luminance cannot be expressed. As a result, the motion blurring phenomenon appears in the moving picture, and the display quality is degraded due to the decrease in the contrast ratio, thereby degrading the visual perception characteristic of the user. In order to solve the slow response speed of the LCD, U.S. Patent No. 5,495,265 and PCT International Publication No. WO 99/09967 proposed a method for driving the LCD at high speed using a lookup table that modulates the voltage of the input data. .

Accordingly, the LCD according to the related art must further include a high speed driving circuit including a lockup table in order to solve the slow response speed of the liquid crystal. Accordingly, the conventional LCD has an additional cost due to the high speed driving circuit for implementing the video.

On the other hand, in the case of the line inversion, the slow response speed of the liquid crystal is solved by using a capacitively coupled (CC) driving method when implementing a video. In detail, the CC driving improves the response speed of the liquid crystal by controlling the gate pulses supplied from the gate D-IC 12 to the gate lines under the control from the timing controller 20 without additional circuitry. To this end, a gate pulse having four voltage levels is supplied to the front gate line GLn-1 to which a storage capacitor (not shown) is connected. The driving waveform of the CC driving is composed of a voltage for turning on / off the thin film transistor of the liquid crystal cell and two bias voltages Vge1 and Vge2 as shown in FIG. 4. The first bias voltage Vge1 of the two bias voltages Vge1 and Vge2 is lowered in the negative direction from the gate low voltage Vgl, and the second bias voltage Vge2 is the gate low voltage at the negative voltage. Will rise to (Vgl) (Pixel2). Accordingly, after the liquid crystal cell is charged, the CC voltage is supplied to the liquid crystal cell through the storage capacitor with a feedthrough effect of two bias voltages Vge1 and Vge2. At this time, the voltage of the liquid crystal cell is as shown in Equation 1 below.

When the voltage of the liquid crystal cell is changed from Vp90 to Vp10 corresponding to the transmittance of 90% to 10% of the liquid crystal, the CC voltage supplied to the liquid crystal cell in the first frame is expressed by Equation 2 below.

In Equation 2, Clc (Vp90) is the liquid crystal capacitance at Vp90.

The CC voltage gradually changes to a steady state voltage as shown in Equation 3 during the hold period of the liquid crystal.

Accordingly, in the normal white display mode of the liquid crystal panel, since the CC voltage of Clc (Vp90) is smaller than Clc (Vp10), the CC voltage initially supplied to the liquid crystal cell becomes higher than the CC voltage in the subsequent hold period. . Accordingly, the voltage of the liquid crystal cell shows an overshoot. On the other hand, when the transmittance changes from 10% to 90%, the CC voltage supplied in the data signal supply period becomes lower than the voltage in the hold period. In this case, the voltage of the liquid crystal cell shows an undershoot. Therefore, the voltage applied to the liquid crystal cell by using the CC driving method is automatically overdrived whenever the voltage of the liquid crystal cell changes. Due to the automatic overdriving of the liquid crystal cell, the response time of the liquid crystal is improved.

As such, the LCD of the line inversion driving method using the CC driving can improve the image quality of the video only by the CC driving without additional cost. However, the driving method of the line inversion has a problem that the image quality is lower than that of the driving method of the one dot inversion in the case of a still image.

Accordingly, it is an object of the present invention to provide a driving apparatus and method for a liquid crystal display device which can improve image quality by changing a driving method of a liquid crystal panel according to an input signal.

1 is a plan view showing a conventional liquid crystal display device.

FIG. 2 is a diagram illustrating a data polarity inversion pattern of a one-dot inversion method displayed on the liquid crystal panel shown in FIG. 1.

FIG. 3 is a diagram illustrating a data polarity inversion pattern of a line inversion method displayed on the liquid crystal panel shown in FIG. 1.

4 is a waveform diagram illustrating gate pulses supplied to gate lines of the liquid crystal panel illustrated in FIG. 1.

5 is a plan view illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 6 is a waveform diagram illustrating a video mode signal shown in FIG. 5. FIG.

7A is a waveform diagram illustrating gate pulses having two voltage levels supplied to gate lines of the liquid crystal panel of FIG. 5.

7B is a waveform diagram illustrating gate pulses having four voltage levels supplied to gate lines of the liquid crystal panel of FIG. 5.

8 is a plan view of the data tape carrier package shown in FIG.

FIG. 9 is a circuit diagram illustrating a multiplexer part and a polarity converting part of the data D-IC shown in FIG. 5.

10 is a plan view of the gate tape carrier package shown in FIG.

<Description of Symbols for Main Parts of Drawings>

2, 102: liquid crystal panel 4, 104: gate PCB

6, 106: data PCB 8, 108: data D-IC

10, 110: data tape carrier package 20, 120: timing control unit

12, 112: gate tape carrier package 122: user connector

130: system 150, 160: input pad unit

154, 164: video mode signal input pad 152, 162: output pad unit

170: multiplexer 172: polarity converter

In order to achieve the above object, a driving device of a liquid crystal display according to an embodiment of the present invention is a liquid crystal panel in which liquid crystal cells are arranged in a matrix form, a system for supplying an image signal to the liquid crystal panel, and a video from the image signal. And a judgment unit for determining a still image, a data driver for supplying the image signal to the liquid crystal panel in a polarity inversion pattern according to the determination signal from the determination unit, and the liquid crystal panel in response to the determination signal from the determination unit. And a gate driver for supplying a scan signal to the gate driver.

The driving apparatus of the liquid crystal display device may further include a timing controller for supplying the determination signal to the data driver and the gate driver, and controlling each of the data driver and the gate driver.

In the driving apparatus of the liquid crystal display, the data driver converts the image signal into a positive and negative analog signal, and any one of the positive and negative analog signals in response to a polarity control signal from the timing controller. And a selection unit for selecting one to generate a main polarity inversion pattern and a conversion unit for converting the main polarity inversion pattern into the polarity inversion pattern in response to the determination signal.

The converting unit converts the still image into a first polarity inversion pattern and converts the video into a second polarity inversion pattern in the driving device of the liquid crystal display.

In the driving device of the liquid crystal display, the first polarity inversion pattern is inverted up and down and left and right, and the second polarity inversion pattern is inverted up and down.

In the driving device of the liquid crystal display, the selector may include a plurality of multiplexers for selecting any one of the positive and negative analog signals.

In the driving device of the liquid crystal display, the converter may include a sub-multiplexer connected to the even-numbered multiplexer of the multiplexers.

In the driving device of the liquid crystal display, the sub-multiplexer includes a control terminal to which the image mode signal is supplied, a first input terminal connected to an output terminal of the multiplexer, and a second terminal connected to an output terminal of the multiplexer through an inverter. Characterized in that it comprises an input terminal.

In the driving device of the liquid crystal display, the timing controller includes: a first gate start pulse having two voltage levels; And generating a second gate start pulse having at least four voltage levels.

In the driving apparatus of the liquid crystal display, the scan signal may be one of a first scan signal generated by the first gate start pulse and a second scan signal generated by the second gate start pulse.

In the driving device of the liquid crystal display, the gate driver supplies the second scan signal to the liquid crystal panel when the determination signal is the moving image, and supplies the first scan signal to the liquid crystal panel when the still image is a still image. It features.

A method of driving a liquid crystal display according to an exemplary embodiment of the present invention includes receiving an image signal; Detecting a moving image and a still image from the image signal; Supplying the still image to the liquid crystal panel in a first polarity inversion pattern in response to the detection signal; And supplying the moving image to the liquid crystal panel in a second polarity inversion pattern in response to the detection signal.

In the driving method of the liquid crystal display device, the first polarity inversion pattern is inverted up and down and left and right, and the second polarity inversion pattern is inverted up and down.

The driving method of the liquid crystal display includes converting the image signal into a positive and negative analog signal, and selecting one of the positive and negative analog signals in response to a polarity control signal to select a main polarity inversion pattern. And converting the main polarity inversion pattern into one polarity inversion pattern of the first and second polarity inversion patterns in response to the detection signal.

The method of driving the liquid crystal display may further include generating a first scan signal having two voltage levels and generating a second scan signal having at least four voltage levels.

In the driving method of the liquid crystal display, the second scan signal is supplied to the liquid crystal panel when the image signal is a moving picture, and the first scan signal is supplied to the liquid crystal panel when the image signal is a still image. It is done.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 10.

Referring to FIG. 5, a liquid crystal display according to an exemplary embodiment of the present invention includes a system 130, gate lines GL1 through GLn, and data lines DL1 through. The liquid crystal panel 102 in which the liquid crystal cell is formed at each intersection of the DLm, and the data D connected to each of the data lines DL1 to DLm of the liquid crystal panel 102 to drive the data lines DL1 to DLm. A plurality of data tape carrier packages 110 on which the IC 108 is mounted, a data PCB 106 connected to the plurality of data tape carrier packages 110, and gate lines GL1 to liquid crystal panels 102. A plurality of gate tape carrier packages 114 connected to each GLn and mounted with a gate D-IC 112 for driving the gate lines GL1 to GLn, and a plurality of gate tape carrier packages 114, respectively. A plurality of data D-ICs 108 arranged on the connected gate PCB 104 and the data PCB 106. ) And a timing controller 120 controlling the gate D-IC 112.

The system 130 supplies a data signal such as a moving picture signal (Ex: television or video image) or a personal computer (not shown) signal to the timing controller 120 through an interface unit (not shown). The interface unit receives the data (R, G, B) and control signals (input clock, horizontal synchronization signal, vertical synchronization signal, data enable signal) input from the system 130 and supplies them to the timing controller 120. Mainly, the interface unit uses a Low Voltage Differential Signal (LVDS) interface and a Transistor Transistor Logic (TTL) interface to transmit data and control signals from the system 130. In addition, the system 130 determines whether a signal supplied to the timing controller 120 is a video signal or a personal computer (not shown) signal to generate an image mode signal MS as shown in FIG. 6. And a detection unit. The image mode signal MS may be generated by a user's selection.

The liquid crystal panel 102 is formed at each intersection of the liquid crystal cells arranged in a matrix form and the gate lines GL1 to GLn and the data lines DL1 to DLm, and is connected to each of the liquid crystal cells TFT. ).

The thin film transistor TFT is turned on when the scan signal from the gate line GL, that is, the gate high voltage VGH is supplied, and supplies the pixel signal from the data line DL to the liquid crystal cell. The thin film transistor TFT is turned off when the gate low voltage VGL is supplied from the gate line GL to maintain the pixel signal charged in the liquid crystal cell.

The liquid crystal cell is equivalently represented by a liquid crystal capacitor Clc, and includes a common electrode facing the liquid crystal and a pixel electrode connected to the thin film transistor TFT. The liquid crystal cell further includes a storage capacitor Cst so that the charged pixel signal is stably maintained until the next pixel signal is charged. The storage capacitor Cst is formed between the pixel electrode and the previous gate line. In the liquid crystal cell, the arrangement state of the liquid crystal having dielectric anisotropy varies according to the pixel signal charged through the thin film transistor TFT, thereby adjusting grayscale.

The timing controller 120 generates gate control signals GSP, GSC, and GOE to control the plurality of gate D-ICs 112. At this time, the timing controller 120 generates a first gate start pulse GSP having two voltage levels for turning on and off the thin film transistor TFT as shown in FIG. 7A, and as shown in FIG. 7B. Likewise, the second gate start pulse GSP having two voltage levels Von and Voff and two bias voltage levels Vge1 and Vge2 for turning on and off the thin film transistor TFT is generated.

In addition, the timing controller 120 generates data control signals SSP, SSC, SOE, and POL to control the plurality of data D-ICs 108. In addition, the timing controller 120 aligns the pixel data R, G, and B to supply the plurality of data D-ICs 108. In addition, the timing controller 120 receives the image mode signal MS from the system 130 through the user connector 122 provided in the data PCB 106 and receives the supplied image mode signal MS from the data PCB 106. Is supplied to each of the data D-IC 108 and the gate D-IC 112 through the mode selection signal line MSL.

Each of the plurality of data D-ICs 108 is mounted in a data tape carrier package 110 as shown in FIG. 8. Each of the data tape carrier packages 110 includes an input pad part 150 connected to the data PCB 106 and an output pad part 152 connected to each of the data lines DL1 to DLm of the liquid crystal panel 102. Equipped. In this case, the input pad unit 150 includes a plurality of control signal input pads to which a control signal is supplied from the timing controller 120, and an image mode signal input pad to which the image mode signal MS is supplied from the timing controller 120. 154.

Each of the plurality of data D-ICs 108 is one line for each horizontal period H1, H2, ... in response to the data control signals SSP, SSC, SOE, and POL from the timing controller 120. The minute pixel signal is supplied to the data lines DL1 to DLm. In particular, each of the plurality of data D-ICs 108 uses an analog pixel signal using the gamma voltage from the gamma voltage generator (not shown) for the digital pixel data R, G, and B from the timing controller 120. To be supplied.

In detail, each of the plurality of data D-ICs 108 generates a sampling signal by shifting the source start pulse SSP according to the source shift clock SSC. Subsequently, each of the plurality of data D-ICs 8 sequentially receives and latches the pixel data signals R, G, and B in predetermined units in response to the sampling signal. Each of the plurality of data D-ICs 108 converts the latched one-line pixel data R, G, and B into analog pixel signals, and supplies them to the data lines DL1 through DLm. In this case, each of the plurality of data D-ICs 108 converts the pixel data R, G, and B into positive and negative pixel signals using a decoder (not shown). Each of the positive and negative pixel signals P and N converted as described above is selected and output by the multiplexer unit 170 as shown in FIG. 9. In this case, the multiplexer unit 170 selects one of the positive and negative pixel signals P and N in response to the polarity control signal POL from the timing controller 120. To this end, the multiplexer unit 170 includes a plurality of multiplexers MUX1 to MUXn to which the positive and negative pixel signals P and N are supplied. An inverter for inverting the polarity control signal POL is connected to the control terminal of the even-numbered multiplexers MUX2, MUX4, ..., MUXn among the multiplexers MUX1 to MUXn. Accordingly, the multiplexer unit 170 selects and outputs the positive and negative pixel signals P and N by the one-dot inversion driving method in response to the polarity control signal POL from the timing controller 120. .

The output side of the even-numbered multiplexers MUX2, MUX4, ..., MUXn among the multiplexers MUX1 to MUXn of the multiplexer unit 170 in response to the image mode signal MS as shown in FIG. A polarity converting unit 172 for converting the positive and negative pixel signals P and N into a single dot inversion driving method or a line inversion driving method is connected.

The polarity converting unit 172 includes a plurality of sub-multiplexers SMUX1 to SMUXn connected to output lines of even-numbered multiplexers MUX2 to MUXn among the multiplexers MUX1 to MUXn. The first input terminal of each of the sub-multiplexers SMUX1 to SMUXn is connected to the output line of each of the even-numbered multiplexers MUX2, MUX4, ..., MUXn, and the second input terminal is connected to the even-numbered multiplexer through the inverter IVT. (MUX2, MUX4, ..., MUXn) Connect to each output line. Also, the image mode signal MS from the timing controller 120 is supplied to the control terminals of the sub-multiplexers SMUX1 to SMUXn. On the other hand, an inverter for inverting the video mode signal MS is connected to the control terminals of the sub multiplexers SMUX1 to SMUXn. Meanwhile, each of the sub-multiplexers SMUX1 to SMUXn may be connected to an output line of each of the odd-numbered multiplexers MUX1, MUX3,..., MUXn-1.

When the image mode signal MS is in the low state, the polarity converting unit 172 outputs the output of each of the even-numbered multiplexers MUX2, MUX4, ..., MUXn. Accordingly, the positive and negative pixel signals P and N are output by the one dot inversion driving method. On the other hand, the polarity converting unit 172 inverts the output of each of the even-numbered multiplexers MUX2, MUX4, ..., MUXn when the image mode signal MS is in a high state. Accordingly, the positive and negative pixel signals P and N are output by the line inversion driving method.

Accordingly, each of the data D-ICs 108 converts the polarity of the pixel signals into the one dot inversion driving method or the line inversion driving method according to the image mode signal MS using the polarity converting unit 172. Feed the fields.

Each of the plurality of gate D-ICs 112 is mounted in a gate tape carrier package 114 as shown in FIG. Each of the gate tape carrier packages 114 includes an input pad part 160 connected to the gate PCB 1046 and an output pad part 162 connected to each of the gate lines GL1 to GLn of the liquid crystal panel 102. Equipped. At this time, the input pad unit 160 includes a plurality of control signal input pads to which a control signal is supplied from the timing controller 120, and an image mode signal input pad to which the image mode signal MS is supplied from the timing controller 120. 164 is provided.

Each of the plurality of gate D-ICs 112 sequentially gates the high voltage VGH to the gate lines GL1 to GLn in response to the gate control signals GSP, GSC, and GOE from the timing controller 120. ). Accordingly, each of the plurality of gate D-ICs 112 causes the thin film transistor TFT connected to the gate lines GL1 to GLn to be driven in units of the gate line GL.

Specifically, each of the plurality of gate D-ICs 112 has the first gate start pulse GSP shown in FIG. 7A when the image mode signal MS input through the image mode signal input pad 164 is low. Is shifted according to the gate shift pulse GSC to generate a shift pulse. Each of the plurality of gate D-ICs 112 supplies the gate high voltage VGH to the corresponding gate line GL for each horizontal period H1, H2,... In response to the shift pulse. In this case, each of the plurality of gate D-ICs 112 supplies the gate high voltage VGH only during the enable period in response to the gate output enable signal GOE. Each of the plurality of gate D-ICs 112 supplies the gate low voltage VGL in the remaining period in which the gate high voltage VGH is not supplied to the gate lines GL1 through GLn. In addition, each of the plurality of gate D-ICs 112 supplies a gate low voltage VGL to a gate line (not shown) formed at the uppermost side for the storage capacitor Cst of the first scan line. Here, the gate pulse generated by the first gate start pulse GSP is referred to as a first gate pulse hereinafter.

On the other hand, each of the plurality of gate D-ICs 112 has the second gate start pulse GSP shown in FIG. 7B when the image mode signal MS input through the image mode signal input pad 164 is high. Is shifted according to the gate shift pulse GSC to generate a shift pulse. Each of the plurality of gate D-ICs 112 supplies the gate high voltage VGH to the corresponding gate line GL for each horizontal period H1, H2,... In response to the shift pulse. In this case, each of the plurality of gate D-ICs 112 supplies the gate high voltage VGH only during the enable period in response to the gate output enable signal GOE. In addition, each of the plurality of gate D-ICs 112 may operate from the first bias voltage Vge1 to the gate low voltage VGL in the remaining period in which the gate high voltage VGH is not supplied to the gate lines GL1 through GLn. The falling gate pulse is supplied or the gate pulse rising from the second bias voltage Vge2 to the gate low voltage VGL is supplied. Each of the first and second bias voltages Vge1 and Vge2 is supplied to the storage capacitor Cst connected between the liquid crystal cell Clc and the front gate line. Here, the gate pulse generated by the second gate start pulse GSP is referred to as a second gate pulse hereinafter.

Accordingly, the liquid crystal cell is capacitively coupled (CC) driven by gate pulses supplied from the plurality of gate D-ICs 112 to the gate lines of the liquid crystal panel 102. Since the CC drive is the same as the description of the prior art described above, the following description will be omitted.

As described above, the LCD driving method according to the embodiment of the present invention provides a liquid crystal panel using line inversion driving when data signals are implemented in response to an image mode signal MS supplied from the system 130. To 102; Supplying the second gate pulse to the liquid crystal panel 102, and supplying data signals to the liquid crystal panel 102 in a dot inversion driving method when implementing a PC image (still image) such as a pulsed computer; The first gate pulse is supplied to the liquid crystal panel 102.

The driving method of the LCD according to the embodiment of the present invention is described in detail as follows. First, the system 130 determines whether the data signal supplied to the timing controller 120 is a moving picture (TV picture) or a still picture (PC picture) to generate a picture mode signal MS.

In the case where the image mode signal MS is in a high state, that is, the data signal is a signal representing a moving picture, each of the data D-ICs 108 is a polarity control signal from the timing controller 120 in response to the image mode signal MS. The analog positive and negative pixel signals generated according to the POL are output by the line inversion driving method and supplied to the data lines.

In synchronization with each other, each of the gate D-ICs 112 supplies a second gate pulse to the gate lines in response to the image mode signal MS.

Therefore, the LCD driving method according to an exemplary embodiment of the present invention drives the data D-IC 108 by the line inversion driving method and applies the CC to the liquid crystal cell by driving the gate D-IC 112. The losing voltage is automatically overdrived whenever the voltage of the liquid crystal cell changes. Due to the automatic overdriving of the liquid crystal cell, the response time of the liquid crystal is improved.

On the other hand, when the image mode signal MS is in a low state, that is, when the data signal is a signal representing a still image (PC image), each of the data D-ICs 108 may respond to the image mode signal MS. The analog positive and negative pixel signals generated according to the polarity control signal POL from 120 are outputted in a dot inversion driving method and supplied to the data lines.

In synchronization with each other, each of the gate D-ICs 112 supplies the first gate pulse to the gate lines in response to the image mode signal MS.

Therefore, when the still image is implemented, the LCD driving method according to the embodiment of the present invention drives the data D-IC 108 by the dot inversion driving method and outputs the gate D-IC 112 to the first gate pulse. By driving so as to improve the quality of still images.

As described above, the driving apparatus and method of the liquid crystal display according to the exemplary embodiment of the present invention include a polarity changing unit for changing the polarity of the data signals supplied to the liquid crystal panel according to the type of the input signal. Accordingly, the present invention improves the response speed of the liquid crystal by driving the liquid crystal panel by a line inversion driving method and overdriving the liquid crystal cell by using gate pulses having four voltage levels. Therefore, the present invention can improve the image quality when the video is implemented.

In addition, the present invention can improve the image quality of the still image by driving the liquid crystal panel in a dot inversion method when implementing a still image.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (16)

A liquid crystal panel in which liquid crystal cells are arranged in a matrix form; A system for supplying a video signal to the liquid crystal panel; A determination unit for discriminating a moving picture and a still picture from the video signal; A data driver for supplying the image signal to the liquid crystal panel in a polarity inversion pattern according to the determination signal from the determination unit; And a gate driver configured to supply a scan signal to the liquid crystal panel in response to the determination signal from the determination unit. The method of claim 1, And a timing controller configured to supply the determination signal to the data driver and the gate driver, and to control the data driver and the gate driver, respectively. The method of claim 2, The data driver, A decoder for converting the video signal into a positive and negative analog signal; A selector configured to select one of the positive and negative analog signals to generate a main polarity inversion pattern in response to the polarity control signal from the timing controller; And a converter which converts the main polarity inversion pattern into the polarity inversion pattern in response to the determination signal. The method of claim 3, wherein And the converting unit converts the still image into a first polarity inversion pattern, and converts the video into a second polarity inversion pattern. The method of claim 4, wherein The first polarity inversion pattern is inverted up and down and left and right, and And the second polarity inversion pattern is inverted up and down. The method of claim 3, wherein And the selector comprises a plurality of multiplexers for selecting any one of the positive and negative analog signals. The method of claim 6, And the converting unit includes a sub-multiplexer connected to the even-numbered multiplexer of the plurality of multiplexers. The method of claim 7, wherein The sub multiplexer, A control terminal to which the image mode signal is supplied; A first input terminal connected to an output terminal of the multiplexer, And a second input terminal connected to an output terminal of the multiplexer through an inverter. The method of claim 2, The timing controller, A first gate start pulse having two voltage levels; And a second gate start pulse having at least four voltage levels. The method of claim 4, wherein The scan signal, And a first scan signal generated by the first gate start pulse and a second scan signal generated by the second gate start pulse. The method of claim 10, The gate driver, And the second scan signal is supplied to the liquid crystal panel when the determination signal is the moving image, and the first scan signal is supplied to the liquid crystal panel when the still image is a still image. Receiving an image signal; Detecting a moving image and a still image from the image signal; Supplying the still image to the liquid crystal panel in a first polarity inversion pattern in response to the detection signal; And supplying the moving image to the liquid crystal panel in a second polarity inversion pattern in response to the detection signal. The method of claim 12, The first polarity inversion pattern is inverted up and down and left and right, and And the second polarity inversion pattern is inverted up and down. The method of claim 12, Converting the video signal into a positive and negative analog signal; Generating a main polarity inversion pattern by selecting any one of the positive and negative analog signals in response to the polarity control signal; And converting the main polarity inversion pattern into one polarity inversion pattern of the first and second polarity inversion patterns in response to the detection signal. The method of claim 12, Generating a first scan signal having two voltage levels; And generating a second scan signal having at least four voltage levels. The method of claim 15, The second scan signal is supplied to the liquid crystal panel when the video signal is a moving picture. And the first scan signal is supplied to the liquid crystal panel when the image signal is a still image.