KR20040074240A - 반도체 소자의 금속배선 형성 방법 - Google Patents
반도체 소자의 금속배선 형성 방법 Download PDFInfo
- Publication number
- KR20040074240A KR20040074240A KR1020030009748A KR20030009748A KR20040074240A KR 20040074240 A KR20040074240 A KR 20040074240A KR 1020030009748 A KR1020030009748 A KR 1020030009748A KR 20030009748 A KR20030009748 A KR 20030009748A KR 20040074240 A KR20040074240 A KR 20040074240A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- contact plug
- layer
- forming
- interlayer insulating
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 24
- 239000002184 metal Substances 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000010410 layer Substances 0.000 claims abstract description 50
- 239000011229 interlayer Substances 0.000 claims abstract description 37
- 230000004888 barrier function Effects 0.000 claims abstract description 21
- 239000010949 copper Substances 0.000 claims abstract description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052802 copper Inorganic materials 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 9
- 239000010937 tungsten Substances 0.000 claims abstract description 9
- 239000004020 conductor Substances 0.000 claims description 21
- 239000000126 substance Substances 0.000 claims description 11
- 238000005498 polishing Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 3
- 230000009977 dual effect Effects 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (6)
- 소정의 도전층이 형성된 반도체 기판 상에 제1 층간절연막을 형성하는 단계;상기 소정의 도전층과 연결되고 상기 제1 층간절연막의 상부 표면으로부터 소정 깊이로 리세스된 제1 콘택플러그를 형성하는 단계;상기 제1 콘택플러그가 형성된 결과물 상에 도전 물질을 증착한 후, 화학 기계적 연마하여 리세스된 부분을 매립하는 제2 콘택플러그를 형성하는 단계;상기 제2 콘택플러그가 형성된 결과물 상에 식각 정지층 및 제2 층간절연막을 순차적으로 형성한 후, 패터닝하여 금속배선을 형성하기 위한 트렌치를 형성하는 단계;상기 트렌치가 형성된 결과물 상에 배리어막을 형성하는 단계; 및상기 배리어막 상에 도전 물질을 증착한 후, 화학 기계적 연마하여 금속 배선을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
- 제1항에 있어서, 상기 제2 콘택플러그 및 상기 배리어막은 동일한 도전물질로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
- 제2항에 있어서, 상기 제2 콘택플러그 및 상기 배리어막은 Ta막 또는 TaN막으로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
- 제1항에 있어서, 상기 제1 콘택 플러그는 텅스텐(W)막으로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
- 제1항에 있어서, 상기 금속 배선은 구리(Cu)막으로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
- 제1항에 있어서, 상기 제1 콘택 플러그를 형성하는 단계는,상기 제1 층간절연막을 패터닝하여 상기 소정의 도전층을 개구하는 콘택홀을 형성하는 단계;상기 콘택홀이 형성된 결과물 상에 단차를 따라 제2 배리어막을 형성하는 단계; 및상기 제2 배리어막 상에 도전 물질을 증착한 후, 에치백하여 상기 콘택홀을 매립하면서 상기 제1 층간절연막의 상부 표면으로부터 소정 깊이로 리세스된 상기 제1 콘택플러그를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030009748A KR100954685B1 (ko) | 2003-02-17 | 2003-02-17 | 반도체 소자의 금속배선 형성 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030009748A KR100954685B1 (ko) | 2003-02-17 | 2003-02-17 | 반도체 소자의 금속배선 형성 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20040074240A true KR20040074240A (ko) | 2004-08-25 |
KR100954685B1 KR100954685B1 (ko) | 2010-04-27 |
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Application Number | Title | Priority Date | Filing Date |
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KR1020030009748A KR100954685B1 (ko) | 2003-02-17 | 2003-02-17 | 반도체 소자의 금속배선 형성 방법 |
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KR (1) | KR100954685B1 (ko) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR102211143B1 (ko) * | 2014-11-13 | 2021-02-02 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19843624C1 (de) * | 1998-09-23 | 2000-06-15 | Siemens Ag | Integrierte Schaltungsanordnung und Verfahren zu deren Herstellung |
KR100400037B1 (ko) * | 2001-02-22 | 2003-09-29 | 삼성전자주식회사 | 콘택 플러그를 구비하는 반도체 소자 및 그의 제조 방법 |
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- 2003-02-17 KR KR1020030009748A patent/KR100954685B1/ko active IP Right Grant
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Publication number | Publication date |
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KR100954685B1 (ko) | 2010-04-27 |
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