KR20040070739A - Method for forming metal line in semiconductor fabrication process - Google Patents
Method for forming metal line in semiconductor fabrication process Download PDFInfo
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- KR20040070739A KR20040070739A KR1020030006922A KR20030006922A KR20040070739A KR 20040070739 A KR20040070739 A KR 20040070739A KR 1020030006922 A KR1020030006922 A KR 1020030006922A KR 20030006922 A KR20030006922 A KR 20030006922A KR 20040070739 A KR20040070739 A KR 20040070739A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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Abstract
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 반도체 제조 공정 중 금속 라인 형성 시 EM 특성을 개선시키는 금속 라인 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a metal line forming method for improving EM characteristics during metal line formation during a semiconductor manufacturing process.
최근 들어 반도체 소자의 대용량 고집적화 추세에 따라 반도체 소자들은 점점 더 소형화가 요구되고 있으며, 반도체 소자의 크기가 작아 질수록 금속 라인의 수는 더 많아지고 있어 종래 금속라인 공정 방법으로는 금속 라인 형성에 곤란한 문제점이 있다.Recently, with the trend of high-capacity and high-density integration of semiconductor devices, semiconductor devices are increasingly required to be miniaturized. As the size of semiconductor devices becomes smaller, the number of metal lines becomes larger, which makes it difficult to form metal lines using conventional metal line processing methods. There is a problem.
도 1a 내지 도 1b는 종래 금속 라인 제조방법을 도시한 공정 수순도로, 이하 상기 도 1a 내지 도 1b를 참조하면, 먼저 도 1a에서와 같이 TiN/Al/TiN(102/104/108) 금속라인 구조, Ti/TiN/Al/TiN(100/102/104/108),Ti/TiN/Al/Ti/TiN(100/102/104/106/108) 등과 같은 금속라인 기본구조를 형성하게 되며, 이때 타이타늄(Ti) 또는 질화 타이타늄(TiN)은 경우에 따라 선택적으로 사용하게 된다. 이어 도 1b에서와 같이 제1 층간 절연막(IMD: InterMetal Dielectric Film)(110), SOG/USG/FSG막(112), 제2 IMD막(114)을 증착시키는 금속 라인 형성을 위한 후속 공정을 수행하게 된다.1A to 1B are process steps illustrating a conventional metal line manufacturing method. Referring to FIGS. 1A to 1B below, a TiN / Al / TiN (102/104/108) metal line structure as shown in FIG. 1A will be described. , Metal line basic structure such as Ti / TiN / Al / TiN (100/102/104/108), Ti / TiN / Al / Ti / TiN (100/102/104/106/108), etc. Titanium (Ti) or titanium nitride (TiN) is optionally used in some cases. Subsequently, as illustrated in FIG. 1B, a subsequent process for forming a metal line for depositing the first interlayer dielectric film (IMD) 110, the SOG / USG / FSG film 112, and the second IMD film 114 is performed. Done.
그러나 상기한 바와 같은 종래 금속 라인 형성에 있어서는 금속의 측면이 금속 식각 후 후 공정에 그대로 노출이 되어 EM(ElectroMigration: 높은 전류 및 온도로 금속의 품질을 특성화하기 위하여 사용되는 시험)/SM(StressMigration: 금속 라인에 일정한 스트레스를 가한 후 품질을 측정하는 방법)의 특성이 나빠지는 원인이되며, 후속 클리닝(Cln) 공정 등에서 화학적 공격을 받아 금속 라인의 특성이 변화게 되는 문제점이 있었다.However, in the conventional metal line formation as described above, the side surface of the metal is exposed to the post-etch process after the metal is intact, and thus, EM (ElectroMigration) is a test used to characterize the quality of the metal at high current and temperature. The method of measuring the quality after applying a certain stress to the metal line) is a cause of deterioration, there was a problem that the characteristics of the metal line is changed by a chemical attack in the subsequent cleaning (Cln) process.
따라서, 본 발명의 목적은 반도체 제조 공정 중 금속 라인 형성 시 EM 특성을 개선시키는 금속 라인 형성 방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a metal line forming method for improving EM characteristics during metal line formation during a semiconductor manufacturing process.
상술한 목적을 달성하기 위한 본 발명은 반도체 소자의 금속 라인 형성 방법에 있어서, (a)금속 식각 공정 후 미리 설정된 일정 두께의 질화 타이타늄막(TiN)을 증착시키는 단계와; (b)상기 질화 타이타늄막 상부에 미리 설정된 일정 두께의 옥사이드막(Oxide)을 증착시키는 단계와; (c)상기 질화 타이타늄막과 옥사이드막을 에치백(Etch back)하여 질화 타이타늄막이 금속 측면에 잔존하는 금속 라인 구조를 형성시키는 단계;를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a metal line of a semiconductor device, the method comprising: (a) depositing a titanium nitride film (TiN) having a predetermined thickness after a metal etching process; (b) depositing an oxide film having a predetermined thickness on the titanium nitride film; (c) etching back the titanium nitride film and the oxide film to form a metal line structure in which the titanium nitride film remains on the metal side.
도 1a 내지 도 1b는 종래 금속 라인 형성 방법을 도시한 공정 수순도,1a to 1b is a process flowchart showing a conventional metal line forming method,
도 2a 내지 도 2b는 본 발명의 실시 예에 따른 금속 라인 형성 방법을 도시한 공정 수순도.2A to 2B are process flowcharts illustrating a metal line forming method according to an exemplary embodiment of the present invention.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 실시 예의 동작을 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the operation of the preferred embodiment according to the present invention.
도 2a 내지 도 2e는 본 발명의 실시 예에 따른 금속 라인 제조 방법을 도시한 공정 수순도 이다. 이하 상기 도 2a 내지 도 2e를 본 발명의 금속 라인 제조 공정을 상세히 설명하기로 한다.2A to 2E are process flowcharts illustrating a metal line manufacturing method according to an exemplary embodiment of the present invention. 2A to 2E will be described in detail the metal line manufacturing process of the present invention.
먼저 도 2a의 금속 라인 구조 형성 공정에서는 기존 공정과 동일하게 Ti 또는 TiN을 선택적으로 사용하여 TiN/Al/TiN(102/104/108) 금속라인 구조, 또는 Ti/TiN/Al/TiN(100/102/104/108), Ti/TiN/Al/Ti/TiN(100/102/104/106/108) 등과 같은 금속라인 기본구조를 형성하게 된다.First, in the metal line structure forming process of FIG. 2A, TiN / Al / TiN (102/104/108) metal line structure, or Ti / TiN / Al / TiN (100 / 102/104/108), Ti / TiN / Al / Ti / TiN (100/102/104/106/108) and the like to form a metal line basic structure.
이어 도 2b에서와 같이 금속 라인 구조 형성 후 TiN막(200)을 700ű500Å 타겟(Target)으로 증착시키고, 도 2c에서와 같이 옥사이드막(Oxide)(202)을 일정 두께 700ű500Å타겟으로 증착시켜 가급적 얇게 형성시킨다.Subsequently, after forming the metal line structure as shown in FIG. 2B, the TiN film 200 is deposited with a 700Å ± 500Å target, and the oxide film 202 is deposited with a certain thickness of 700Å ± 500Å target as shown in FIG. 2C. To be as thin as possible.
그리고 도 2c에서와 같이 에치백(Etch back) 공정을 수행한 후, 도 2e에서와 같이 IMD/SOG/IMD/CMP 순서 또는 H에/IMD/CMP 공정 순으로 금속 라인 형성을 위한 후속 공정을 수행하여 금속 라인을 형성하게 된다.After performing an etch back process as shown in FIG. 2C, a subsequent process for forming a metal line is performed in the order of IMD / SOG / IMD / CMP or H / IMD / CMP as shown in FIG. 2E. To form a metal line.
따라서 상기한 발명의 금속 라인 형성 공정에서는 금속의 측면이 TiN에 의해 보호되어 EM/SM/금속측면의 손상을 근본적으로 제거하여 금속 라인의 특성이 변화되지 않도록 할 수 있게 된다.Accordingly, in the metal line forming process of the present invention, the side of the metal is protected by TiN to fundamentally eliminate the damage of the EM / SM / metal side so that the characteristics of the metal line can be changed.
한편 상술한 본 발명의 설명에서는 구체적인 실시 예에 관해 설명하였으나,여러 가지 변형이 본 발명의 범위에서 벗어나지 않고 실시될 수 있다. 따라서 발명의 범위는 설명된 실시 예에 의하여 정할 것이 아니고 특허청구범위에 의해 정하여져야 한다.Meanwhile, in the above description of the present invention, specific embodiments have been described. However, various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the invention should be determined by the claims rather than by the described embodiments.
이상에서 설명한 바와 같이, 본 발명은 반도체 소자 제조시 금속 라인 형성 공정에 있어서 금속의 측면이 TiN에 의해 보호되도록 하여 금속 라인에서 발생할 수 있는 EM/SM/금속 측면의 손상을 근본적으로 제거함으로서 금속 라인 특성이 변화되지 않도록 하는 이점이 있다.As described above, the present invention allows the metal side to be protected by TiN in the metal line forming process in semiconductor device fabrication, thereby essentially eliminating the EM / SM / metal side damage that may occur in the metal line. There is an advantage that the characteristic does not change.
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