KR20040065029A - Method for forming trench in semiconductor device - Google Patents
Method for forming trench in semiconductor device Download PDFInfo
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- KR20040065029A KR20040065029A KR1020030002148A KR20030002148A KR20040065029A KR 20040065029 A KR20040065029 A KR 20040065029A KR 1020030002148 A KR1020030002148 A KR 1020030002148A KR 20030002148 A KR20030002148 A KR 20030002148A KR 20040065029 A KR20040065029 A KR 20040065029A
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 150000004767 nitrides Chemical class 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 238000002955 isolation Methods 0.000 claims description 13
- 238000000137 annealing Methods 0.000 claims description 9
- 238000004140 cleaning Methods 0.000 claims description 5
- 238000011049 filling Methods 0.000 claims description 3
- 238000002156 mixing Methods 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 239000007788 liquid Substances 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 7
- 230000007547 defect Effects 0.000 abstract description 2
- 239000007789 gas Substances 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 description 9
- 238000007254 oxidation reaction Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체소자의 트렌치 형성방법에 관한 것으로, 보다 상세하게는 어닐링 공정을 이용하여 트렌치 상하부의 각진부분을 라운딩시킬 수 있는 반도체소자의 트렌치 형성방법에 관한 것이다.The present invention relates to a trench forming method of a semiconductor device, and more particularly to a trench forming method of a semiconductor device that can round the angular portion of the upper and lower trenches using an annealing process.
일반적으로 소자분리기술은 실리콘 집적회로를 제작하기 위해 각각의 단위소자들을 전기적으로 분리시킬 수 있는 기술인데, 이러한 소자분리기술은 소자가 점점 고집적화됨에 따라 단위소자는 물론 전체소자의 특성을 결정짓는데 기초가 되는 핵심기술중의 하나로 반도체소자 제조공정에서 출발점이 된다.In general, device isolation technology is capable of electrically separating each unit device to fabricate a silicon integrated circuit, and this device isolation technology is based on determining characteristics of the entire device as well as the device as the device is increasingly integrated. One of the key technologies to become a starting point in the semiconductor device manufacturing process.
또한, 후속의 소자 제조공정에 직간접적으로 영향을 미침과 동시에 소자특성에 많은 영향을 준다.In addition, it directly or indirectly affects subsequent device fabrication processes, and at the same time, greatly affects device characteristics.
종래의 64M 이상의 소자제작시 소자분리기술로서 STI (Shallow Trench Isolation)기술을 이용하고 있다. 이러한 종래의 STI 소자분리기술을 설명하면 다음과 같다.Shallow Trench Isolation (STI) technology is used as a device isolation technology when fabricating more than 64M of conventional devices. This conventional STI device isolation technology is as follows.
먼저, 실리콘기판상에 패드산화막과 패드질화막을 증착하고 포토레지스트 마스크를 이용하여 트렌치 식각할 영역을 패터닝한 후 상기 패드질화막을 배리어로 하여 소자분리영역을 실리콘 건식식각하여 트렌치를 형성한다.First, a pad oxide film and a pad nitride film are deposited on a silicon substrate, and a region to be trench-etched is patterned using a photoresist mask. Then, the device isolation region is silicon-etched using the pad nitride film as a barrier to form a trench.
그 다음, 상기 트렌치 건식식각으로 인해 발생한 손상을 제거하고, 식각후 남아있는 실리콘부분(액티브영역)의 상하부부분을 라운딩시키기 위해 열산화공정을 진행한다.Then, a thermal oxidation process is performed to remove the damage caused by the trench dry etching and to round the upper and lower portions of the silicon portion (active region) remaining after the etching.
이어서, 상기 건식식각된 트렌치영역(소자분리막 영역)에 절연막으로서 산화막을 증착하고, 식각후 남아있는 실리콘부분(액티브 영역)의 산화절연막을 제거한다.Subsequently, an oxide film is deposited as an insulating film in the dry etched trench region (device isolation region), and the oxide insulating film of the silicon portion (active region) remaining after etching is removed.
마지막으로, 인산(H3PO4)을 이용하여 상기 패드질화막을 습식식각함으로써 STI를 완성한다.Finally, the STI is completed by wet etching the pad nitride layer using phosphoric acid (H 3 PO 4).
이러한 종래의 STI 형성방법에서 열산화공정을 실시하여 트렌치 건식식각시 발생한 손상을 제거하고, 식각후 남아 있는 실리콘부분(액티브영역)의 상하부에서 각진부분을 라운딩한다. 이때, 상기 열산화공정은 트렌치 건식식각으로 인한 손상을 제거하는 효과가 있다.In the conventional STI forming method, a thermal oxidation process is performed to remove damage generated during trench dry etching, and rounded corners are formed at upper and lower portions of the silicon portion (active region) remaining after etching. At this time, the thermal oxidation process has the effect of removing the damage caused by the trench dry etching.
그러나, 이러한 종래의 열산화공정에서는 도 1에 도시된 바와 같이, 상기 트렌치 건식식각시 트렌치 프로파일이 그대로 트렌치의 상부 및 하부에 전사되기 때문에 라운딩 효과면에서는 취약하여 트렌치의 상하부 프로파일이 각이 지는 문제점이 있다.However, in the conventional thermal oxidation process, as illustrated in FIG. 1, since the trench profile is transferred to the upper and lower portions of the trench as it is, the upper and lower profiles of the trench are angled due to its weakening effect. There is this.
또한, 상기 트렌치의 각진 프로파일로 인해 반도체소자의 리프레쉬 및 전기적 특성의 열화를 가져와 수율을 저하시키는 문제점이 있다.In addition, due to the angular profile of the trench, there is a problem in that the yield of the semiconductor device is reduced due to the refreshing and electrical characteristics of the semiconductor device.
따라서, 본발명은 상기 종래기술의 제반문제점을 해결하기 위하여 안출한 것으로서, 트렌치 상하부의 각진 부분을 라운딩시키고 소자의 리프레시 및 전기적 특성을 향상시켜 수율을 개선할 수 있는 반도체소자의 트렌치 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems of the prior art, and provides a trench forming method of a semiconductor device that can improve the yield by rounding the angular portion of the upper and lower trenches, improve the refresh and electrical characteristics of the device Has its purpose.
도 1은 종래기술에 따른 반도체소자의 트렌치 형성방법에 의해 형성된 트렌치 상하부의 각진 프로파일을 도시한 사진.1 is a photograph showing an angular profile of upper and lower portions of a trench formed by a trench forming method of a semiconductor device according to the related art.
도 2a 내지 도 2k는 본 발명에 따른 반도체소자의 트렌치 형성방법을 도시한 공정별 단면도.2A to 2K are cross-sectional views illustrating a method of forming trenches in a semiconductor device according to the present invention.
(도면의 주요부분에 대한 부호설명)(Code description of main parts of drawing)
100 : 실리콘기판 110 : 패드산화막100: silicon substrate 110: pad oxide film
120 : 패드질화막 130 : 포토레지스트 마스크120: pad nitride film 130: photoresist mask
140 : 트렌치 150 : 라운딩부분140: trench 150: rounding part
160 : 제 1 열산화막 170 : 라이너산화막160: first thermal oxide film 170: liner oxide film
180 : 제 2 열산화막 190 : HDP절연막180: second thermal oxide film 190: HDP insulating film
200 : 소자분리영역 300 : 액티브영역200: device isolation region 300: active region
상기 목적을 달성하기 위한 본 발명은, 반도체기판상에 패드산화막과 패드질화막을 차례로 형성하는 단계; 상기 패드질화막과 패드산화막 및 반도체기판을 순차적으로 제거하여 상기 반도체기판내에 트렌치를 형성하는 단계; 상기 트렌치를 포함한 결과물의 상부를 세정하는 단계; 상기 트렌치를 포함한 결과물의 상부를 어닐링하는 단계; 상기 반도체기판내 트렌치 표면상에 제 1 열산화막을 형성하는 단계; 상기 제 1 열산화막의 상부와 상기 패드질화막의 상부 및 측벽에 라이너산화막을 형성하는 단계; 상기 라이너산화막의 상부에 제 2 열산화막을 형성하는 단계; 상기 트렌치를 포함한 결과물의 상부를 평탄화용 절연막으로 매립하는 단계; 상기 패드질화막이 노출될때 까지 상기 평탄화용 절연막을 평탄화시키는 단계; 및 상기 패드질화막을 제거하여 소자분리막을 형성하는 단계를 포함하여 구성됨을 특징으로 한다.The present invention for achieving the above object, the step of sequentially forming a pad oxide film and a pad nitride film on a semiconductor substrate; Sequentially removing the pad nitride film, the pad oxide film, and the semiconductor substrate to form a trench in the semiconductor substrate; Cleaning the top of the resultant product including the trench; Annealing the top of the resultant product including the trench; Forming a first thermal oxide film on the trench surface in the semiconductor substrate; Forming a liner oxide film on the top of the first thermal oxide film and on the top and sidewalls of the pad nitride film; Forming a second thermal oxide film on the liner oxide film; Filling the upper portion of the resultant including the trench with a planarization insulating film; Planarizing the planarization insulating layer until the pad nitride layer is exposed; And removing the pad nitride layer to form an isolation layer.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2k는 본 발명에 따른 반도체소자의 트렌치 형성방법을 도시한 공정별 단면도이다.2A to 2K are cross-sectional views illustrating processes of forming trenches in the semiconductor device according to the present invention.
먼저, 도 2a에 도시된 바와 같이, 실리콘기판(100)상에 패드산화막(110)과 패드질화막(120)을 차례로 증착한다.First, as shown in FIG. 2A, the pad oxide film 110 and the pad nitride film 120 are sequentially deposited on the silicon substrate 100.
여기서, 상기 패드산화막(110)은 패드질화막의 스트레스를 완화시키고, 상기 패드질화막(120)은 트렌치형성을 위한 식각시 배리어로 사용한다.Here, the pad oxide layer 110 may relieve stress of the pad nitride layer, and the pad nitride layer 120 may be used as a barrier during etching for forming trenches.
이때, 상기 패드산화막(110)은 800∼1100℃의 온도범위에서 수행하여50∼150Å두께로 형성하며, 상기 패드질화막(120)은 LP-CVD로 600∼800℃의 온도범위에서 500∼1500Å두께로 형성한다.In this case, the pad oxide film 110 is formed in a temperature range of 800 to 1100 ° C. to form a thickness of 50 to 150 ° C., and the pad nitride film 120 is 500 to 1500 ° C. in a temperature range of 600 to 800 ° C. by LP-CVD. To form.
그 다음, 도 2b에 도시된 바와 같이, 상기 패드질화막(120)상에 형성된 포토레지스트 마스크(130)를 이용하여 트렌치 형성영역을 패터닝한다.Next, as shown in FIG. 2B, the trench formation region is patterned using the photoresist mask 130 formed on the pad nitride layer 120.
이어서, 도 2c에 도시된 바와 같이, 상기 결과물의 상부에 트렌치 건식식각공정을 수행하여 상기 반도체기판(100)내에 트렌치(140)를 형성한다.Subsequently, as shown in FIG. 2C, a trench dry etching process is performed on the resultant to form the trench 140 in the semiconductor substrate 100.
그 다음, 도 2d에 도시된 바와 같이, 상기 트렌치(140)를 포함한 결과물의 상부에 BFN 세정공정을 수행하여 그 표면의 일부를 식각제거함으로써 상기 트렌치식각으로 인해 발생한 손상과 결함을 제거한다.Next, as shown in FIG. 2D, the BFN cleaning process is performed on the upper part of the resultant including the trench 140 to etch away part of the surface to remove damage and defects caused by the trench etching.
이어서, 도 2e에 도시된 바와 같이, 종래의 열산화공정 대신에 H2/N2혼합가스를 이용한 어닐링공정을 수행한다.Subsequently, as shown in FIG. 2E, an annealing process using H 2 / N 2 mixed gas is performed instead of the conventional thermal oxidation process.
여기서, 상기 H2가스만을 이용하여 어닐링공정을 수행하면 실리콘 이주현상이 과도하게 발생하여 STI 프로파일 자체가 왜곡될 수 있기 때문에, H2가스와 함께 N2가스를 혼합하여 어닐링공정을 수행하면 과도한 실리콘 이주현상을 감소시킬 수 있다.Here, since this could cause the STI profile itself distorted by excessive generation of silicon two weeks developing performing an annealing process using only the H 2 gas, if a mixture of N 2 gas with H 2 gas to perform the annealing step excessive silicon It can reduce migration.
이러한 H2/N2혼합가스를 이용한 실리콘 이주현상에 의해 실리콘부분(액티브영역)의 상하부에 트렌치 건식식각후의 각진 프로파일이 그대로 전사되던 종래의 열산화공정의 문제를 해결할 수 있다.The problem of the conventional thermal oxidation process in which the angular profile after the trench dry etching is transferred to the upper and lower portions of the silicon portion (active region) by the silicon migration phenomenon using the H 2 / N 2 mixed gas can be solved.
이로써, 트렌치식각으로 인한 손상이 제거되고 액티브영역 상하부의 각진 프로파일(즉, 트렌치 상하부의 각진 프로파일)을 라운딩하여 라운딩부분(150)을 형성한다.As a result, damage due to the trench etching is removed and the angular profile of the upper and lower portions of the active region (that is, the angular profile of the upper and lower portions of the trench) is rounded to form the rounded portion 150.
이때, 상기 어닐링공정은 400∼800℃의 온도범위에서 수행하며, 상기 H2/N2혼합가스는 1:1∼1:4의 혼합비율을 갖는다.At this time, the annealing process is carried out in a temperature range of 400 ~ 800 ℃, the H 2 / N 2 mixed gas has a mixing ratio of 1: 1 to 1: 4.
그 다음, 도 2f에 도시된 바와 같이, 상기 결과물의 상부에 열산화공정을 수행하여 상기 트렌치(140)의 표면상에 제 1 열산화막(160)을 형성한다.Next, as illustrated in FIG. 2F, a thermal oxidation process is performed on the resultant to form a first thermal oxide layer 160 on the surface of the trench 140.
여기서, 제 1 열산화막(160)은 후속공정에서 트렌치영역(소자분리막영역)을 매립하기 위한 HDP(High Density Plasma)절연막과 실리콘기판사이에 계면전하포획 중심영역이 형성되는 것을 억제하며, 또한 소자분리막 상하부의 각진 프로파일이 라운딩 프로파일로 변화되도록 소자분리막의 상하부 모서리부분을 라운딩시켜 후속의 열산화공정에 기인한 스트레스를 완화시킨다.Here, the first thermal oxide film 160 suppresses the formation of the interface charge trapping center region between the HDP (High Density Plasma) insulating film and the silicon substrate for filling the trench region (device isolation region) in a subsequent process, and also The upper and lower corners of the device separator are rounded so that the angular profile of the upper and lower parts of the separator is changed to a rounding profile, thereby alleviating stress due to subsequent thermal oxidation.
이어서, 도 2g에 도시된 바와 같이, 상기 결과물의 전체상부에 라이너산화막(170)을 증착한다.Subsequently, as shown in FIG. 2G, a liner oxide film 170 is deposited over the entire resultant product.
이때, 상기 라이너산화막 증착시 실리콘 소스가스로서 DCS(DichloroSilane)가스 또는 MS(MonoSilane)가스를 이용하며, 이러한 라이너산화막(170)은 후속의 HDP절연막 증착시 측벽에 보이드가 형성되는 것을 억제한다.At this time, when the liner oxide film is deposited, DCS (DichloroSilane) gas or MS (MonoSilane) gas is used as the silicon source gas, and the liner oxide film 170 suppresses the formation of voids on the sidewalls during the subsequent HDP insulation film deposition.
그 다음, 도 2h에 도시된 바와 같이, 고온의 열산화공정을 수행하여 제 2 열산화막(180)을 형성한다.Next, as shown in FIG. 2H, a high temperature thermal oxidation process is performed to form a second thermal oxide film 180.
여기서, 상기 제 2 열산화막(180)은 상기 패드질화막(120)과 상기 실리콘기판(100)간 계면의 모트 크기를 줄이고 반도체소자의 리프레시 특성을 향상시킨다.Here, the second thermal oxide film 180 reduces the mote size of the interface between the pad nitride film 120 and the silicon substrate 100 and improves the refresh characteristics of the semiconductor device.
이어서, 도 2i에 도시된 바와 같이, 상기 트렌치(140)를 포함한 결과물의 상부에 HDP(High Density Plasma)절연막(190)을 증착하여 상기 트렌치(140)를 포함한 결과물의 상부까지 매립한다.Subsequently, as shown in FIG. 2I, a high density plasma (HDP) insulating layer 190 is deposited on the resultant including the trench 140 and filled up to the upper part of the resultant including the trench 140.
여기서, 상기 HDP절연막(190)은 PE-CVD(Plasma Enhanced-Chemical Vapor Deposition)방식을 이용하여 형성한다.The HDP insulating layer 190 is formed using a plasma enhanced-chemical vapor deposition (PE-CVD) method.
그 다음, 도 2j에 도시된 바와 같이, 상기 패드질화막(120)이 노출될 때 까지상기 결과물의 상부에 CMP(Chemical Mechanical Polishing)공정을 수행하여 액티브영역상의 상기 HDP절연막(190)을 제거하고 평탄화시킨다.Next, as illustrated in FIG. 2J, a chemical mechanical polishing (CMP) process is performed on the resultant product until the pad nitride layer 120 is exposed to remove and planarize the HDP insulating layer 190 on the active region. Let's do it.
마지막으로, 도 2k에 도시된 바와 같이, 상기 결과물의 상부에 H3PO4식각액을 이용한 습식식각공정을 수행하여 상기 실리콘기판(100)상의 패드질화막(120)을 제거함으로써 소자분리막(190)을 완성하여 소자분리영역(200)과 액티브영역(300)을 형성한다.Finally, as shown in FIG. 2K, the device isolation layer 190 is removed by performing a wet etching process using an H 3 PO 4 etchant on the top of the resultant to remove the pad nitride layer 120 on the silicon substrate 100. The device isolation region 200 and the active region 300 are formed.
상술한 바와 같이, 본 발명은 트렌치 상하부의 각진 부분을 라운딩시킬 수 있으며, 또한 소자의 리프레시 및 전기적 특성을 향상시켜 수율을 개선할 수 있다는 효과가 있다.As described above, the present invention can round the angular portions of the upper and lower trenches, and also improve the yield by improving the refresh and electrical characteristics of the device.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
Claims (7)
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