KR20040063331A - Method of manufacturing a flash memory cell - Google Patents

Abstract

PURPOSE: A method for fabricating a flash memory cell is provided to facilitate an isolation process by eliminating the necessity of a deep trench process, to reduce a junction leakage current by decreasing stress of silicon, and to reduce a cell size by decreasing an active width as compared with a deep trench process. CONSTITUTION: An isolation layer(302) of an STI(shallow trench isolation) structure is formed on a semiconductor substrate(301) in a direction vertical to a wordline direction so as to define an active region for forming a channel region and a drain. After a trench(304) is formed in the region having the isolation layer, the trench is filled with a polysilicon layer to form a control gate(305). An insulation layer is formed on the resultant structure including the upper portion of the control gate and the active region. One end of a floating gate(307) of a predetermined pattern overlaps the control gate, the other end of the floating gate overlaps the active region, and the center portion of the floating gate overlaps the isolation layer. The drain is formed in the active region in the periphery of the floating gate by an ion implantation process.

Description

Method of manufacturing a flash memory cell

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory cell, and more particularly, to a method of manufacturing a flash memory cell capable of preventing excessive erasing from occurring, thereby improving erase characteristics and facilitating circuit design.

Flash memory cells are electrically programmable / eraseable devices in which electrons are trapped by a floating gate or formed from a floating gate through a tunnel oxide film consisting of a thin oxide film of approximately 100 kV by a strong electric field generated by a voltage applied to the gate line. Data is stored by changing the threshold voltage of the cell through the emitted program / erase operation.

1 is a conceptual diagram illustrating a structure of a general flash memory cell.

Referring to FIG. 1, a general flash memory cell includes a tunnel oxide film 102, a floating gate 103, a dielectric film 104, and a control gate 105 formed in a stacked structure, and a semiconductor substrate at both edges of the floating gate 103. And source / drain 106a and 106b formed in 101.

A program operation of a flash memory cell having the above configuration will be described below.

When the p well (not shown) where the flash memory cell is formed and the source 106a are grounded and a high voltage of about 9V is applied to the control gate 105, a pulse 5us of about 5V is applied to the drain 106b. Channel hot electrons (CHEs) are generated as channels are formed on the surface of the semiconductor substrate 101 under the floating gate 103. The channel hot electrons are trapped by the electric field through the tunnel oxide film 102 and into the floating gate 103. As a result, the threshold voltage of the flash memory cell is increased, the threshold voltage reaches the target voltage, and the program operation is completed.

The erase operation of the flash memory cell having the above configuration will be described below.

When a high voltage of about 8V is applied to the semiconductor substrate 101 while a high voltage of about -8V is applied to the control gate 105, electrons trapped at the floating gate 103 by FN (Fowler Nerdheim) tunneling are tunnel oxide films ( Passed through 102 and exits from floating gate 103. As a result, the threshold voltage of the flash memory cell is lowered, the threshold voltage reaches the target voltage, and the erase operation is completed.

At this time, the rate of extracting electrons during the erasing operation depends mainly on the thickness of the gate coupling and the tunnel oxide layer. Since the tunneling is not self-controlled, the threshold voltage distribution of the cell is determined by the distribution of the speed at which the flash memory cell is erased. do.

2 is a circuit diagram illustrating a general flash memory cell array.

Referring to FIG. 2, a flash memory cell array is composed of a plurality of flash memory cells (only six are shown in the drawings; C201 to C206). At this time, the control gates of the flash memory cells are commonly connected to each row by word lines, and the drains are commonly connected to each column by bit lines.

According to the above configuration, when a bias is applied to the first word line W / L _n-1 , a bias is applied to the control gates of the first and second flash memory cells C201 and C202, and the second word line ( When applying a bias to the W / L _n) the third and the fourth flash memory cells (is applied to the bias on the control gate of the C203 and C204), the when applying a bias to the third word line (W / L _{n + 1)} the A bias is applied to the control gates of the fifth and sixth flash memory cells C205 and C206.

In addition, when a bias is applied to the first bit line B / L _n , a bias is applied to the drains of the first, third and fifth flash memory cells C201, C203, and C205, and the second bit line B / L _n is applied. Applying a bias to L _{n + 1} applies a bias to the drains of the second, fourth and sixth flash memory cells C202, C204, and C206.

In the above, if the erase speed of the flash memory cell is not uniform, a cell that is over erased is generated, so that a leakage current always flows in the bit line where the cell is over erased.

For example, if the first flash memory cell C201 is over erased, the first bit line B / L _n may be selected regardless of whether the third and fifth flash memory cells C203 and C205 are selected or stored data. Current always flows through the first flash memory cell C201. Therefore, data cannot be read normally.

In order to solve such a problem, the process of forming the device isolation film, the critical dimension of the floating gate, the dielectric film, the tunnel oxide film, and the like, which are important factors for determining the gate coupling, must be very finely controlled. . After the flash memory cell is manufactured, another algorithm is required in order to prevent a malfunction caused by a cell that is excessively erased during a test or operation.

For example, in order to prevent a cell from being excessively erased in the course of performing an erase operation, a pre-program is initially performed to match the threshold voltage of the cell to some extent, and after the erase operation is completed, Performs a post-program to raise the threshold voltage of the over erased cell to the target threshold voltage. However, in addition to the algorithm of erasing and erasing verification, this method continuously performs preprogramming and verifying until the program state before the erasing operation is verified, and post-programming and verification until the threshold voltage of the over erased cell increases after the erasing operation. Since the verification is performed continuously, the time efficiency of erasing the cell is reduced.

In the FN tunneling used during the erase operation of the cell, power consumption is not large because almost no current flows. However, in the program operation, approximately 200 mA or more current flows per cell, and in the post program, 200 mA or more current flows per bit line. As a result, much more power is consumed in the algorithm to prevent over erase than in an actual erase operation. Moreover, since the erase algorithm must include a peripheral circuit for the post program and drive the positive charge pump circuit as well as the negative charge pump circuit during the erase operation, additional power consumption in the peripheral circuit block driven by the internal clock is required. Is generated and has drawbacks in terms of power consumption. In addition, many hot carriers are generated during post programming, and hot holes trapped to the floating gate through the tunnel oxide film deteriorate the electrical characteristics of the tunnel oxide film more than the electrons. This reduces the electrical characteristics of the cell.

Therefore, in order to solve the above problem, in the state in which the control gate is formed in the trench form in the region where the device isolation layer is formed so as to be electrically isolated from the channel region, an insulating film is formed on the entire upper portion and one end portion of the control gate is formed. A floating gate is formed on the substrate so that the other end overlaps with the channel region, and then a drain is formed on the semiconductor substrate around the channel region by an ion implantation process, so that the drain and the floating gate and between the control gate and the floating gate are formed. When the electric field is the same, the erase operation no longer proceeds, thereby preventing excessive erase from occurring, improving the reliability of the device and eliminating the need for peripheral circuitry to perform post program operation, thereby simplifying the design of the flash memory cell. To provide a method of manufacture for that purpose There is this.

1 is a conceptual diagram illustrating a configuration of a general flash memory cell.

2 is a circuit diagram illustrating a general flash memory cell array.

3 is a layout diagram illustrating a method of manufacturing a flash memory cell according to the present invention.

4A to 4D are cross-sectional views illustrating a method of manufacturing a flash memory cell according to the present invention with the layout diagram of FIG. 3 taken along line A-A '.

5 is a characteristic graph for illustrating a change in the control gate current and the bulk current according to the floating gate voltage.

<Explanation of symbols for the main parts of the drawings>

101, 301: semiconductor substrate 102, 306: tunnel oxide film

103, 307: floating gate 104: dielectric film

105: control gate 106a: source

106b, 308: Drain 302: Device isolation film

303 photoresist pattern 304 trench

305: polysilicon, control gate 306: tunnel oxide film

A method of manufacturing a flash memory cell according to an embodiment of the present invention includes the steps of defining an active region in which a channel region or a drain is to be formed by forming a device isolation layer having an STI structure provided on a semiconductor substrate in a direction perpendicular to a word line direction. Forming a trench in a region in which a separator is formed, and then filling a trench with a polysilicon layer to form a control gate, forming an insulating film over the entire area including the control gate and the upper portion of the active region, and one end of the control gate. And forming a floating gate in a predetermined pattern and overlapping the other end portion with the active region and the center portion overlapping the device isolation layer, and forming a drain in the active region around the floating gate by an ion implantation process. do.

In the above, the width of the device isolation layer may be set to 2 to 4 times the width of the active region.

Meanwhile, the device isolation layer between the control gate and the active region may adjust the position of the control gate formed in the device isolation layer so that the width of the device isolation layer may be stably operated even when a breakdown voltage of 20V to 25V is applied. At this time, it is preferable to adjust the width of the device isolation layer between the control gate and the active region to 500 to 1000 mW.

The ratio of overlapping the floating gate and the control gate and overlapping the floating gate and the active region may be determined according to the target threshold voltage in the erase state. In this case, it is preferable that the ratio of the overlapping level of the floating gate and the control gate and the overlapping level of the floating gate and the active region is set to 1: 1.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various different forms, and only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information. In the drawings, like reference numerals refer to like elements.

3 is a layout for explaining a method of manufacturing a flash memory cell according to the present invention, Figures 4a to 4d is a view of the layout of Figure 3 taken along the line A-A 'according to the present invention Sectional drawing for explaining the manufacturing method of a flash memory cell.

Referring to FIG. 4A, a device isolation layer 302 having a shallow trench isolation (STI) structure is formed in a direction parallel to a word line direction in a semiconductor substrate 301 of an element isolation region including a region where a control gate line is to be formed. This defines an active region in which a channel region or a drain is to be formed. In this case, the device isolation layer 302 is formed to a depth of 2000 to 4000Å, and the width of the device isolation layer 302 is 2 to 4 times the width of the active region.

Referring to FIG. 4B, after forming the photoresist pattern 303 in which the control gate line region is defined, the device isolation layer 302 of the control gate line region is defined by an etching process using the photoresist pattern 303 as an etching mask. Etch to depth. As a result, a trench 304 having a depth lower than that of the device isolation layer 302 is formed in the device isolation layer 302 in the region where the control gate line is to be formed. In this case, the trench 304 is formed to be biased to one edge portion of the device isolation layer 302, and breakdown of 20V to 25V or more is applied to the narrow device isolation layer 302 between the trench 304 and the active region 301a. The width between the trench 304 and the active region 301a is adjusted to 500 to 1000 kW so that the device can operate stably even when a voltage (Breakdown voltage) is applied.

Referring to FIG. 4C, the photoresist pattern 303 of FIG. 4B is removed, a polysilicon layer is formed on the entire upper portion, and the polysilicon layer formed on the semiconductor substrate 301 is removed by a chemical mechanical polishing process. The polysilicon layer 305 remains only at 304 in FIG. 4B. The polysilicon layer 305 remaining in the trench (304 in FIG. 4B) serves as a control gate. In the above, the photoresist pattern (303 of FIG. 4B) may be removed together during the chemical mechanical polishing process after forming the polysilicon layer first.

3 and 4D, an insulating film 306 is formed over the entire surface. The insulating film 306 serves as a tunnel oxide film. Subsequently, after the polysilicon layer is formed on the whole, the polysilicon layer is patterned by an etching process using a floating gate mask, and one end thereof overlaps with the polysilicon layer 305 remaining in the trench (304 in FIG. 4B). A floating gate 307 overlapping with the active region (301a of FIG. 4C) and the center portion overlaps with the device isolation layer 302 having a narrow width is formed in a predetermined pattern.

Thereafter, the floating gate 307 is not formed so that impurities are implanted into the exposed active region (301a of FIG. 4C) by an ion implantation process to form a drain 309. As a result, the flash memory cell C300 is manufactured.

The flash memory cell of the present invention formed through the above process does not have a source line, and the drain of an adjacent cell connected to the ground terminal serves as a source during the read and program operations of the cell. The control gate 305 is completely isolated from the bulk by the device isolation layer 302, and the floating gate 307 and the control gate 305 have the same thickness as the insulating layer 306 between the floating gate 307 and the bulk. Are isolated.

5 is a characteristic graph for illustrating a change in the control gate current and the bulk current according to the floating gate voltage. The reason why the erase operation is stopped when the threshold voltage of the flash memory cell having the above structure reaches a specific voltage during the erase operation will be described with reference to FIGS. 4D and 5. On the other hand, for convenience of explanation, the width of the control gate 305 and the active region 301a on the channel side is the same and overlaps with the floating gate 307 at 1: 1 (gate coupling = 0.5). In the state where the threshold voltage of the ultraviolet ray erasing state is assumed to be 2V, the case of performing the erase operation by applying 7.5V to the channel region and -7.5V to the control gate 305 will be described.

Since the oxide film (the narrow portion of the device isolation film) between the control gate 305 and the semiconductor substrate 301 has a breakdown voltage of at least 20V, no leakage current is generated.

If the threshold voltage of the flash memory cell is raised to about 6V by the program operation, the floating gate 307 is equal to the case where a voltage of about -4V is applied, so that a voltage of 11.5V is applied to the semiconductor substrate. A voltage of about 3.5V is applied to the control gate. Therefore, electron movement from the control gate 305 to the floating gate 307 is hardly generated, and electrons are emitted only from the floating gate 307 toward the semiconductor substrate to perform an erase operation.

As described above, if the voltage of the floating gate 307 approaches 0V, the voltage between the floating gate 307 and the semiconductor substrate and the voltage between the floating gate 307 and the control gate 305 become the same. . Then, at the point where the electrons emitted toward the semiconductor substrate and the electrons injected from the control gate 305 are equal (the gate current characteristic graph and the bulk current characteristic graph in FIG. 5 coincide), the voltage of the floating gate 307 is no longer present. Does not change and the erase operation is stopped.

As in the example here, when the gate coupling is 0.5, the erase operation is stopped when the threshold voltage becomes 2V, which is the threshold voltage of the ultraviolet erasing state. On the other hand, when the gate coupling is greater than 0.5, the erase operation is stopped at a position lower than the ultraviolet erasure threshold voltage, and when the gate coupling is smaller than 0.5, the erase operation is stopped at a position higher than the ultraviolet erasure threshold voltage.

As described above, in the flash memory cell of the present invention, when the threshold voltage reaches a specific voltage, the erase operation is stopped, and the timing at which the erase operation is stopped may be adjusted by gate coupling. However, in order to eliminate the change in the threshold voltage at which erasing stops due to the erase bias, it is preferable to set the gate coupling to 0.5.

By manufacturing a flash memory cell by the above-described method, the present invention can obtain the following effects.

First, the device does not use a deep trench process, which facilitates device isolation, and reduces stress on silicon, reducing the risk of leakage current between junctions. In addition, compared to the deep trench process, it is easier to reduce the active width, thereby further reducing the cell size.

Secondly, since the polysilicon layer is formed only once, the process step is simplified.

Third, since the ONO dielectric film is not used, electrons are not emitted through the ONO, thereby improving electron retention.

Fourth, since the etching process of the ONO film or the control gate is omitted, the process step is simplified, and the gate coupling can be easily controlled.

Fifth, since no over erase occurs, peripheral circuitry for performing an algorithm such as a post program is unnecessary, which simplifies the design.

Sixth, it is possible to prevent the lifespan and electrical characteristics of the device from being degraded by the post program.

Claims (6)

Defining an active region in which a channel region or a drain is to be formed by forming a device isolation layer having an STI structure in a semiconductor substrate in a direction perpendicular to a word line direction; Forming a trench in an area in which the device isolation layer is formed, and then filling the trench with a polysilicon layer to form a control gate; Forming an insulating film over the entire region including the control gate and the active region; Forming a floating gate in a predetermined pattern on one end of which overlaps the control gate, the other end of which overlaps the active region, and a central portion of which overlaps the device isolation layer; And Forming a drain in the active region around the floating gate by an ion implantation process. The method of claim 1, And the width of the device isolation layer is two to four times the width of the active region. The method of claim 1, The device isolation layer between the control gate and the active region controls the position of the control gate formed on the device isolation layer so that the width of the device isolation layer is maintained to be stable even when a breakdown voltage of 20V to 25V is applied. The manufacturing method of the flash memory cell. The method of claim 3, wherein And a width of the device isolation layer between the control gate and the active region is 500 to 1000 mW. The method of claim 1, And a ratio between the level of overlapping the floating gate and the control gate and the level of overlapping the floating gate and the active region is determined according to a target threshold voltage in an erased state. The method of claim 1, And a ratio between the level of overlapping the floating gate and the control gate and the level of overlapping the floating gate and the active region is 1: 1.