KR20040061601A - Array substrate for LCD and method for fabricating of the same - Google Patents

Abstract

PURPOSE: An array substrate of an LCD(liquid crystal display) and a method for manufacturing the array substrate are provided to repair gate lines and data lines using a metal black matrix. CONSTITUTION: An array substrate of an LCD includes an insulating substrate(200), a black matrix pattern(203a,203b) including a repair line, a color filter pattern layer formed on the black matrix pattern, a planarization layer formed on the color filter pattern layer, and a gate line(207) that is located on the planarization layer and includes a gate pad formed at one end of the gate line. The array substrate further includes a gate insulating layer formed on the gate pad and gate line, a data line(209a) that intersects the gate line to define a pixel region and includes a data pad(235a) formed at one end of the data line, and a thin film transistor that is formed at the intersection of the gate line and data line and includes a gate electrode(215), a semiconductor layer, source and drain electrodes(220,225). The array substrate also has a passivation layer that is formed on the overall surface of the substrate and exposes the gate pad and data pad, and a pixel electrode(227) formed at the pixel region and connected to the drain electrode.

Description

Array substrate for LCD and manufacturing method thereof {Array substrate for LCD and method for fabricating of the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a TFT array on color filter (TOC) structure liquid crystal display device including a repair wiring using BM and a method of manufacturing the same.

In general, a liquid crystal display device displays an image by using optical anisotropy and birefringence characteristics of liquid crystal molecules. When an electric field is applied, the alignment of liquid crystals is changed, and the characteristics of light transmission vary according to the arrangement direction of the changed liquid crystals.

In general, a liquid crystal display device is formed by arranging two substrates on which electric field generating electrodes are formed so that the surfaces on which the two electrodes are formed face each other, injecting a liquid crystal material between the two substrates, and then applying a voltage to the two electrodes. By moving the liquid crystal molecules by the electric field is a device that represents the image by the transmittance of light that varies accordingly.

1 is a view schematically showing a general liquid crystal display device.

As shown, a general color liquid crystal display 11 includes a color filter 7 and a color filter 7 including a black matrix 6 formed between a sub color filter 8 and each sub color filter 8. The upper substrate 5 having the common electrode 18 deposited thereon, the pixel region P, and the pixel electrode 17 and the switching element T formed in the pixel region, and the pixel region P The liquid crystal 14 is filled between the lower substrate 22 and the upper substrate 5 and the lower substrate 22 on which array wiring is formed.

The lower substrate 22 is also referred to as an array substrate, and the thin film transistor T, which is a switching element, is positioned in a matrix type, and the gate wiring 13 crosses the plurality of thin film transistors TFT. ) And data wirings 15 are formed.

In this case, the pixel area P is an area defined by the gate wiring 13 and the data wiring 15 intersecting. A transparent pixel electrode 17 is formed on the pixel area P as described above.

The pixel electrode 17 uses a transparent conductive metal having a relatively high transmittance of light, such as indium-tin-oxide (ITO).

A storage capacitor C connected in parallel with the pixel electrode 17 is formed on the gate wiring 13, and a part of the gate wiring 13 is used as the first electrode of the storage capacitor C, and a second As an electrode, an island-shaped source and drain metal layer 30 formed of the same material as the source and drain electrodes is used.

In this case, the source and drain metal layers 30 may be in contact with the pixel electrode 17 to receive a signal of the pixel electrode.

As described above, when the upper color filter substrate 5 and the lower array substrate 22 are bonded to each other to produce a liquid crystal panel, light leakage defects due to the bonding error between the color filter substrate 5 and the array substrate 22 may be reduced. It is very likely to occur.

In order to solve the above problems, the color filter and the thin film transistor are configured on one substrate to solve the problem of occurrence of adhesion error and light leakage defect.

Hereinafter, an array substrate of the TOC structure liquid crystal display device will be described.

As shown, the gate wiring 53 is formed in the first direction, the data wiring 57 is formed in the second direction crossing the first direction, and the gate wiring 53 and the data wiring 57 are formed. The intersection defines the pixel region P. FIG.

Gate pads 60 and data pads 63 are formed at one end of the gate line 53 and the data line 57, respectively.

A thin film transistor is formed at the point where the gate line 53 and the data line 57 cross each other, and the pixel electrode 70 is formed by being connected to the thin film transistor.

The thin film transistor includes a gate electrode 55 branched from the gate line 53, a source electrode 65 branched from the data line 57, and a drain electrode spaced apart from the source electrode 65 at a predetermined interval. It consists of (67).

The pixel electrode 70 partially overlaps the front gate line 53, and a region of the gate line 53 overlapping the pixel electrode 70 forms a capacitor electrode. In addition, the hatched region corresponds to the black matrix 45 forming portion, and the black matrix 45 includes a gate wiring 53, a data wiring 55, and a region covering the thin film transistor T and the pixel electrode. 70 is positioned in an area covering the edge portion, and the main area of the pixel area P is exposed.

3 to 6 are cross-sectional views taken along the lines II ′, II-II ′, and III-III ′ of FIG. 2.

As shown in the figure, a BM pattern 45 is formed on the transparent insulating substrate 40 to prevent light leakage, and red, green, and blue (B) bordering on the BM pattern 45 are formed. The planarization film 49 of the transparent organic insulator is formed on the color filter pattern 47 and the color filter pattern 47. The gate electrode 55a is formed of a conductive material such as a metal on the planarization layer 49, and the gate insulating layer 56 covers the gate electrode 55a. The semiconductor layer 59 forming the active layer 59a is formed on the gate insulating layer 56 on the gate electrode 55a, and the source and drain electrodes 65 and 67 are formed on the semiconductor layer 59. The source and drain electrodes 65 and 67 together with the gate electrode 55a form a thin film transistor. Subsequently, a passivation layer 69 having a drain electrode contact hole 68 exposing the drain electrode 67 is formed on the source and drain electrodes 65 and 67, and a transparent conductive material is formed on the passivation layer 69. The pixel electrode 70 is formed, and the pixel electrode 70 is connected to the drain electrode 67 through the drain electrode contact hole 68.

Referring to the gate pad 60 and the data pad 63, color filters and planarization layers are not formed on the gate and the data pads 60 and 63. In the gate pad, a gate pad electrode 55b is formed of a material of the gate electrode 55a on the substrate 45, and a gate insulating layer 56 is formed on the gate pad electrode 55b. A protective layer 69 is formed on the gate insulating layer 56, and the protective layer 69 and the gate insulating layer 56 are etched to expose the gate pad electrode 55b, and the metal pattern 55a is disposed thereon. It is formed in contact with a portion of the protective layer 69 and the exposed gate pad electrode 55b.

In the data pad 63, a gate insulating film 56 is formed on the substrate 45, and a passivation layer 69 is disposed on the data pad electrode 66 and the data pad electrode 66 on the gate insulating film 56. Is formed, and the protective layer 69 is etched to expose the data pad electrode 66, and to contact the exposed gate electrode 66 and a portion of the protective layer 69 to form a metal pattern 71b. Is formed.

According to the present invention, in the conventional TOC structure, the BM is extended to the gate pad region by using the metal BM formed at the bottom of the substrate without additional masks, and at the same time, the BM is separated and configured to be electrically separated by each gate wiring. As a result, a structure capable of repairing the gate wiring and the data wiring is formed.

1 is a view schematically showing a configuration of a general liquid crystal display device.

2 to 5 are cross-sectional views of an array substrate of a general TOC structure liquid crystal display device.

6 is a plan view schematically showing a part of an array substrate for a TOC structure liquid crystal display device according to a first embodiment of the present invention;

7 is a plan view of a BM pattern formed on an array substrate for a TOC structure liquid crystal display device according to a first embodiment of the present invention;

8A to 8D, 9A to 9D, and 10A to 10D are cut along AA ′, BB ′, and CC ′ of 6, and are shown in a process sequence according to a process sequence according to the first embodiment of the present invention. .

FIG. 11 is a plan view schematically showing a part of an array substrate for a TOC structure liquid crystal display device according to a second embodiment of the present invention; FIG.

12 is a plan view of a BM pattern formed on an array substrate for a TOC structure liquid crystal display device according to a second embodiment of the present invention;

13A to 13D, 14A to 14D, and 15A to 15D are cut along the lines DD ′, EE ′, and FF ′ of FIG. 11, and are shown in a process sequence according to a process sequence according to the first embodiment of the present invention. .

<Brief description of the main parts of the drawing>

200: substrate 203a, 203b: BM pattern

207: gate wiring 209a, 209b: data wiring data pad

215: gate electrode 220: source electrode

225: drain electrode 120: data pad

122: island-shaped metal layer 128: black matrix

134a, b, c: color filter 138, 140: pixel electrode

142: gate pad contact hole 144: data pad contact hole

An array substrate for a liquid crystal display device according to the present invention for achieving the above object is an insulating substrate; A black matrix (BM) pattern including a repair wiring; A color filter pattern layer on the BM pattern; A planarization layer on the color filter pattern layer; A gate wiring disposed on the planarization layer and including a gate pad at one end thereof; A gate insulating film positioned over the gate pad and the gate wiring; A data line intersecting the gate line and the gate insulating layer vertically to define a pixel area and including a data pad at one end thereof; A thin film transistor positioned at an intersection point of the gate line and the data line, the thin film transistor including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode; A protective layer disposed on a front surface of the substrate on which the thin film transistor is formed and exposing the gate pad and the data pad; And a pixel electrode independently contacting the drain electrode and patterned for each pixel region.

In the method of manufacturing an array substrate for a liquid crystal display device according to the present invention, an intermediate BM pattern is formed in a first direction without a break on an insulating substrate, and the middle thereof is cut at a predetermined interval connecting one end, one end, and the other end of the BM pattern. One end extends to the gate pad part at regular intervals between the edge BM pattern formed in the second direction and the edge BM pattern formed in the first direction, and the other end is formed to meet the other edge BM pattern in the second direction. Forming a plurality of gate repair BM patterns in a first direction; Forming a color filter pattern on the BM pattern including the repair pattern; Forming a planarization layer over the color filter pattern layer; Removing the planarization layer of the pad part, and etching the planarization layer at a predetermined interval in the other surface BM pattern to expose the BM pattern; Forming a gate wiring including a gate electrode on the planarization layer, overlapping the gate repair BM pattern, and including a gate pad at one end thereof; Forming a gate insulating film on an entire surface of the substrate on which the gate wiring and the gate pad are formed; Forming a data line on the gate insulating layer, the data line including a data pad at one end thereof while crossing the gate line; Forming a thin film transistor including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode at an intersection point of the gate wiring and the data wiring; Forming a protective layer on an entire surface of the substrate on which the thin film transistor is formed; Patterning the protective layer to expose a portion of the drain electrode and the pad; And forming a metal pattern in contact with the pad electrode in the pixel electrode and the pad portion in contact with the exposed drain electrode, and connecting the gate line and the gate repair BM pattern overlapping the lower portion of the gate line.

In this case, the gate wiring in the first direction has the other end overlapping the other edge BM pattern and a part thereof is extended in the second direction, and is connected to the BM pattern through a contact hole, and the end of the gate wiring in the vicinity It is characterized by not being connected with.

According to another aspect of the present invention, there is provided a method of fabricating an array substrate for a liquid crystal display device, wherein a plurality of BM patterns are formed on the insulating substrate at regular intervals in the first direction, and one end of the data pad is seamless in the second direction. Forming a plurality of BM patterns including a data repair line extending to a portion; Forming a color filter pattern on the BM pattern including the repair pattern; Forming a planarization layer over the color filter pattern layer; Removing the planarization film of the pad part, and etching the planarization film at a predetermined interval in the lower teburi BM pattern to expose the BM pattern; Forming a gate wiring including a gate electrode on the planarization layer and overlapping the gate repair BM pattern, and including a gate pad at one end thereof; Forming a gate insulating film on an entire surface of the substrate on which the gate wiring and the gate pad are formed; Forming a data line on the gate insulating layer, the data line including first and second data pads at one end thereof and crossing the gate line; Forming a thin film transistor including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode at an intersection point of the gate wiring and the data wiring; Forming a protective layer on an entire surface of the substrate on which the thin film transistor is formed; Patterning the protective layer to expose a portion of the drain electrode and the pad; Forming a metal pattern in contact with the pad electrode and a pixel electrode in contact with the exposed drain electrode, and connecting the data repair BM pattern overlapping the data line.

In this case, a plurality of metal patterns may be formed on the lowermost BM pattern in the first direction to contact the BM and to be spaced apart from each other by a smaller distance than the pixel width.

In addition, the data line has the other end of the pad portion overlapping the lowermost BM pattern in the second direction, and a part thereof extends in the second direction, and is not connected to the adjacent data line, and contacts the metal pattern on the BM pattern. It is characterized by being formed.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

<First Embodiment>

The first embodiment has a TOC structure capable of repairing gate wirings.

FIG. 6 is a plan view of an array substrate including a gate pad, a data pad, and a BM for repairing a gate wiring, and FIG. 7 illustrates a BM repair pattern when only a BM process is performed.

When the BM pattern was formed on the substrate 100, the BM patterns 103a and 103b were formed to extend to the gate pad 160. In the longitudinal BM pattern 103b of the edge for electrical separation, the pixel unit It is formed by cutting off. That is, the BM pattern 103b in the longitudinal direction of the edge is formed so as to be independent of each pixel forming part, and the horizontal BM pattern 103a under the gate wiring 107a is formed to be connected seamlessly. That is, the BM pattern 103a in the lateral direction is formed to overlap the gate wiring 107a and the pixel electrode 127 on the pixel region P defined by the gate wiring 107a and the data wiring 109 intersecting with each other. ) Overlaps with the data lines 109 positioned on both sides thereof. This is to secure a high opening rate. The pixel electrode 127 also partially overlaps the gate wiring 107a, is in contact with the storage electrode on the gate wiring 107a, and is also formed to contact the drain electrode 125 through a contact hole.

The most distinctive feature of the TOC structure lower substrate according to the first embodiment of the present invention is that the edge BM pattern 103b on the other side of the gate pad and a portion thereof extend vertically and overlap the edge BM pattern 103b in the longitudinal direction. do. In this case, the longitudinal gate line 107b overlapping with the BM pattern 103b is not connected to the gate line extension around the gate line 107b.

8A to 8A, 9A to 9F, and 10A to 10F are cross-sectional views taken along the cutting lines A-A ', B-B', and C-C 'of FIG. 6. A manufacturing method will be described with reference to the above drawings.

First, as illustrated in FIGS. 8A, 9A, and 10A, conductive chromium (Cr) is deposited on the insulating substrate 100, and a mask process is performed to form the BM patterns 103a and 103b. The BM patterns 103a and 103b include functions of light leakage prevention and repair wiring of the gate wiring according to the present invention. Thereafter, the red, green, and blue color filter patterns 110 are formed on the BM patterns 103a and 103b, and the planarization film 112 of the transparent organic insulator is formed on the color filter patterns 110. In this case, the planarization film 112 may be removed when the printed circuit board (PCB), which is an external driving circuit, may be a problem after the panel is manufactured in the pad part. The flattening film 112 may be removed. A portion of the planarization film 112 is removed to expose the pattern 103b.

Next, as illustrated in FIGS. 8B, 9B, and 10B, a metal material is deposited on the entire surface of the substrate 100 on which the planarization film 112 is formed, and a gate electrode 115a is formed by performing a mask process. In this case, the metal material forming the gate electrode 115a is patterned on the exposed BM pattern 103b to form the gate pad electrode 115b, and in the edge longitudinal BM pattern 103b, A portion of the planarization layer 112 is removed to contact the exposed BM pattern 103b and the gate wiring 107b extends. Thereafter, an inorganic material such as silicon nitride is deposited on the gate lines 107a and 107b and the gate pad electrode 115b including the gate electrode 115a to form a gate insulating layer 116.

Next, as shown in FIGS. 8C, 9C, and 10C, the semiconductor layer 117 of the active layer 117a of amorphous silicon and the ohmic contact layer 117b of amorphous silicon containing impurities are disposed on the gate insulating layer 116. Form. Here, the active layer 117a is formed by depositing and patterning a silicon layer, and the ohmic contact layer 117b is formed by ion doping phosphorous (Phosphorus) or boron (Boron) as impurities in the active layer 117a.

Next, a source electrode 120 and a drain electrode 125 are formed on the ohmic contact layer 117b. Here, one selected from the group of conductive metals including chromium (Cr), molybdenum (Mo), tungsten (W), titanium (Ti), and copper (Cu) is deposited and patterned through a mask process to form the source and drain electrodes 120. , 125). Meanwhile, the active layer 117a and the ohmic contact layer 117b are formed, and source and drain electrodes 120 and 125 are formed thereon, and then exposed in a region spaced between the source and drain electrodes 120 and 125. The ohmic contact layer is removed to expose the active layer 117a at the bottom to form a channel region. Thereafter, an organic material such as benzocyclobutene (BCB) is coated on the source and drain electrodes 120 and 125 to form a protective layer 140. In this case, the protective layer 140 is also formed on the BM pattern 103a of the pad part and the edge.

8D, 9D, and 10D, the drain contact hole 150 and the gate pad electrode 115b exposing the drain electrode 125 by performing a mask process on the protective layer 140 may be formed. A gate pad contact hole 153 is formed to be exposed. Subsequently, ITO, which is a transparent conductive material, is deposited on the entire surface of the substrate 100 on which the contact holes 150 and 153 are formed, and patterned to contact the drain electrode 125 through the drain contact hole 150. ), And at the same time, a gate pad electrode pattern is formed in contact with and connected to the gate pad electrode 115b.

In the lower substrate of the TOC structure liquid crystal display device having the gate repair wiring formed as BM according to the first embodiment of the present invention manufactured as described above, the gate wiring and the BM pattern under the gate wiring are electrically connected to each other. It is possible to prevent the gate line defect caused when the wiring is disconnected or short-circuited. That is, when the gate wiring is disconnected, since the pixels after the disconnected pixel are not supplied with electricity, a line off defect occurs in which the pixel dies, but electricity is supplied through the repair wiring of the BM to prevent the line open defect. Can be.

Second Embodiment

The second embodiment has a TOC structure capable of repairing data wirings.

FIG. 11 is a plan view of a lower substrate including a gate pad and a data pad and a BM for repairing a gate wiring, and FIG. 12 is a view illustrating a BM repair wiring when only a BM process is performed.

When the BM patterns 203a and 203b are formed on the substrate 200, the BM patterns 203a and 203b are formed to extend to the data pad part 260, and are positioned below the gate wiring 207 for electrical separation. In the lateral BM pattern 203a, the BM pattern 203a is formed in pixel units by pixel. In other words, the longitudinal BM pattern 203b under the data line 209a is formed by connecting without interruption in the middle so as to be electrically connected, and the transverse BM pattern 203a under the gate line 207 is electrically connected. It is formed so as not to be connected to each other by forming a pixel to prevent only light leakage.

In addition, the pixel electrode 227 on the pixel region P defined by the intersection of the gate wiring 207 and the data wiring 209a is formed to overlap the data wiring 209a positioned at both sides to secure a high opening ratio. . The pixel electrode 227 also partially overlaps the gate wiring 207, contacts the storage electrode on the gate wiring 207, and contacts the drain electrode 225 through the drain contact hole. In addition, the data line 209a is connected to the end of the data pad 235a and is formed to the end of the active region, and the end thereof is partially extended by being vertically bent to the transverse BM edge. The extended data line 209b is connected to the horizontal edge BM pattern 203a through a contact hole.

In the lower substrate of the TOC structure liquid crystal display, a characteristic portion includes a first data pad 235a and a second data pad 235b, and the other side of the data pad portion 265, that is, the transverse direction under the active region. The data line 209b and the BM pattern are formed at the edge of the BM through a contact hole.

13A to 13D, FIGS. 14A to 14D, and FIGS. 15A to 15F are cross-sectional views taken along the cutting lines D-D ', E-E', and F-F 'of FIG. A manufacturing method will be described with reference to the above drawings.

First, as shown in FIGS. 13A, 14A, and 15A, metal materials such as chromium (Cr) are deposited on the insulating substrate 200 and a mask process is performed to form BM patterns 203a and 203b. The BM patterns 203a and 203b include functions of light leakage prevention and repair wiring of the data wiring according to the present invention. Thereafter, red, green, and blue color filter patterns 210 are formed on the BM patterns 203a and 203b, and the planarization film 212 of the transparent organic insulator is formed on the color filter patterns 210. In this case, the planarization film 212 may be removed after the panel is manufactured in the pad parts 260 and 265, and may be a problem when the PCB is attached. The BM pattern 103b may also be removed in the lower edge of the BM pattern 103b. A portion of the planarization film 212 is patterned and removed to expose it.

Next, as illustrated in FIGS. 13B, 14B, and 15B, a metal material is deposited on the entire surface of the substrate 200 on which the planarization film 212 is formed, and a gate electrode 215a is formed by performing a mask process. In this case, a metal material of the gate electrode 215a is patterned on the exposed BM pattern 203b in the first data pad 235a, and pad portions are connected between the active regions of the first data pad 235a. Part of the planarization film 212 is also removed at the portion. The removed portion is later formed with a contact hole in contact with the BM pattern 203b. A portion of the planarization film 212 is removed from the lower edge BM pattern 203a to contact the exposed BM pattern 203a and a metal pattern is formed at the same time as the gate electrode 215a is formed. Thereafter, an inorganic material such as silicon nitride is deposited on the entire surface of the substrate 200 including the gate electrode 215a to form a gate insulating layer 216.

Next, as shown in FIGS. 13C, 14C, and 15C, the semiconductor layer 217 of the active layer 217a, which is amorphous silicon, and the ohmic contact layer 217b, which is amorphous silicon containing impurities, are disposed on the gate insulating layer 216. Form. Here, an active layer 217a is formed by depositing and patterning a silicon layer, and an ohmic contact layer 217b is formed by ion doping phosphorous or boron as impurities in the active layer 217a.

Next, a source electrode 220 and a drain electrode 225 are formed on the ohmic contact layer 217b. Here, the metal material is deposited and patterned through a mask process to form the source and drain electrodes 220 and 225. Meanwhile, the active layer 217a and the ohmic contact layer 217b are formed, the source and drain electrodes 220 and 225 are formed thereon, and then exposed in a region spaced between the source and drain electrodes 220 and 225. The ohmic contact layer 217b is removed to expose the active layer 217a to form a channel region. In the data pad part 265, a data line 209a including a source electrode 220 is formed on the gate insulating layer 216. In addition, in the data line 209b connected to the teburi BM pattern 203a at the end of the data line 209a, the metal pattern portion and the gate insulating film formed while the data line 209b is in contact with the lower edge BM pattern 103a. 116 is formed with some overlap in between. Thereafter, an organic material such as benzocyclobutene (BCB) is coated on the source and drain electrodes 220 and 225 to form a protective layer 240.

Next, as illustrated in FIGS. 13D, 14D, and 15D, a drain process hole 250 and first and second data pads exposing the drain electrode 225 by performing a mask process on the protective layer 240 are performed. Data pad contact holes 204b and 204c exposing the electrodes 215b and 209a are formed. Subsequently, ITO, which is a transparent conductive material, is deposited on the entire surface of the substrate 200 on which the contact holes 204b and 204c are formed, and patterned to contact the drain electrode 225 through the drain contact hole 250. ) And a data pad metal pattern 228 for contacting and connecting the first and second data pad electrodes 215b and 209a at the same time. The data pad metal pattern 228 is connected to the first data pad electrode 215b formed in the data pad part 265 and the second data pad electrode 209a formed in the data pad connection part.

In the array substrate of the TOC structure liquid crystal display device having the data repair wiring formed as the BM pattern according to the second embodiment of the present invention manufactured as described above, the data wiring and the BM pattern under the data wiring are the first and second data pads. A lower end of the data line is connected to a transparent metal through a contact hole formed on the data metal pattern formed in contact with the data wiring contact hole and the lateral transverse BM pattern formed at the lower end thereof, A BM repair wiring is formed. Therefore, it is possible to prevent data wiring defects caused when the data wiring is disconnected or short-circuited. That is, when the data line is disconnected, the pixels after the disconnected pixel are not supplied with electricity, thereby causing a pixel line off failure. However, electricity is supplied and electrically connected through the BM repair wiring under the data line. It can prevent the line off failure.

The array substrate for a liquid crystal display device having a TOC structure according to the present invention has an effect of preventing a wiring open defect caused when the gate wiring or the data wiring is disconnected by using the black matrix as the gate repair wiring or the data repair wiring.

Claims (6)

An insulating substrate; A black matrix (BM) pattern including a repair wiring; A color filter pattern layer on the BM pattern; A planarization layer on the color filter pattern layer; A gate wiring disposed on the planarization layer and including a gate pad at one end thereof; A gate insulating film positioned over the gate pad and the gate wiring; A data line intersecting the gate line and the gate insulating layer vertically to define a pixel area and including a data pad at one end thereof; A thin film transistor positioned at an intersection point of the gate line and the data line, the thin film transistor including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode; A protective layer disposed on a front surface of the substrate on which the thin film transistor is formed and exposing the gate pad and the data pad; A pixel electrode which is independently patterned for each pixel area while in contact with the drain electrode Array substrate for a liquid crystal display device comprising a. A border BM pattern formed in the first direction without a break on the insulating substrate, a border BM pattern in the second direction formed at a predetermined interval connecting one end and one end, the other end and the other end of the BM pattern, and the first Forming a plurality of gate repair BM patterns in a first direction in which one end thereof extends to the gate pad part at regular intervals between the edge BM patterns in a direction, and the other end thereof meets the other edge BM pattern in the second direction; Wow; Forming a color filter pattern on the BM pattern including the repair pattern; Forming a planarization layer over the color filter pattern layer; Removing the planarization layer of the pad part, and etching the planarization layer at a predetermined interval in the other surface BM pattern to expose the BM pattern; Forming a gate wiring including a gate electrode on the planarization layer, overlapping the gate repair BM pattern, and including a gate pad at one end thereof; Forming a gate insulating film on an entire surface of the substrate on which the gate wiring and the gate pad are formed; Forming a data line on the gate insulating layer, the data line including a data pad at one end thereof while crossing the gate line; Forming a thin film transistor including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode at an intersection point of the gate wiring and the data wiring; Forming a protective layer on an entire surface of the substrate on which the thin film transistor is formed; Patterning the protective layer to expose a portion of the drain electrode and the pad; Forming a metal pattern in contact with the pad electrode and a pixel electrode in contact with the exposed drain electrode and connecting the gate repair BM pattern overlapping the gate line; Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 2, The other end of the gate wiring in the first direction overlaps the other edge BM pattern, and a part thereof is extended in the second direction, and is connected to the BM pattern through a contact hole, and an end thereof is adjacent to the adjacent gate wiring. Array substrate for a liquid crystal display device characterized in that not connected. A plurality of BM patterns are formed on the insulating substrate, the plurality of BM patterns including a plurality of BM patterns formed at regular intervals apart from each other in the first direction, and data repair wires having one end extending to the data pad portion without interruption in the second direction. Making a step; Forming a color filter pattern on the BM pattern including the repair pattern; Forming a planarization layer over the color filter pattern layer; Removing the planarization film of the pad part, and etching the planarization film at a predetermined interval in the lower Teburi BM pattern to expose the BM pattern; Forming a gate wiring including a gate electrode on the planarization layer, overlapping the gate repair BM pattern, and including a gate pad at one end thereof; Forming a gate insulating film on an entire surface of the substrate on which the gate wiring and the gate pad are formed; Forming a data line on the gate insulating layer, the data line including first and second data pads at one end thereof while crossing the gate line; Forming a thin film transistor including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode at an intersection point of the gate wiring and the data wiring; Forming a protective layer on an entire surface of the substrate on which the thin film transistor is formed; Patterning the protective layer to expose a portion of the drain electrode and the pad; Forming a metal pattern in contact with the pad electrode and a pixel electrode in contact with the exposed drain electrode, and connecting the data repair BM pattern overlapping the data line; Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 4, wherein And a plurality of metal patterns are formed on the lowermost BM pattern in the first direction and in contact with the BM and spaced at a predetermined interval smaller than the pixel width. The method of claim 4, wherein The other end of the pad portion of the pad portion overlaps the lowermost BM pattern in the second direction and extends a part of the pad portion in the second direction, is not connected to the adjacent data wiring, and is formed in contact with the metal pattern on the BM pattern. An array substrate for liquid crystal display devices.