KR20040060551A - source resistance improvement structure of flash memory and its manufacturing method - Google Patents

Abstract

PURPOSE: A structure of a flash memory and a manufacturing method thereof are provided to improve considerably source resistance by forming a common source line having a low resistance in the second trench alone using ion-implantation. CONSTITUTION: An active region(1) and a trench region are alternately formed along the bit line direction. The trench region includes the first trench region and the second trench region(8b). The first trench region is formed at both sides of the active region along the bit line direction. The second trench is formed between the first trenches at the periphery of the active region. A common source line(12) is formed in the second trench region by using ion-implantation.

Description

Source resistance improvement structure of flash memory and its manufacturing method

The present invention relates to a source resistance improving structure of a flash memory and a method of manufacturing the same. Specifically, a shallow trench isolation (STI) technology and a self aligned floating gate (SAS) technology applied to reduce a cell size of a flash memory are described. The present invention relates to a source resistance improving structure of a flash memory and a method of manufacturing the same, which can significantly improve the source resistance when applied simultaneously.

In general, NOR flash memory uses a common source method. In other words, one contact is formed in each of the 16 cells, and source lines of the 16 cells are connected to a diffusion layer (N +). Most semiconductors use Shallow Trench Isolation (STI) technology as the isolation technology at 0.25μm or 0.18μm or less, while flash memory uses the Self Aligned Floating Gate (SAS) at 0.35 or below. The cell size is significantly reduced, and the flow of these technologies is described below.

First, referring to FIG. 1A, a plan view of a flash memory cell when the SAS (Self Aligned Floating Gate) technology is not applied is illustrated. Referring to FIG. 1B, a plan view of the flash memory cell when the SAS technology is applied is illustrated. Is shown.

Here, reference numeral 2 denotes a common source line, 6 denotes a gate, 8 denotes a device isolation region, that is, shallow trench isolation (STI), 10 denotes a drain contact, 9 denotes a bit line, and 4 denotes a common at the gate 6. It is a predetermined gap facing the source line 2. In addition, the lengths corresponding to 0.1 占 퐉 are also displayed on the X and Y axes, so that the flash memory cell sizes in FIGS. 1A and 1B can be known.

As shown, SAS technology is a technique for shrinking a cell in the direction of a bit line (9), a predetermined gap (4) from the gate 6 shown in Figure 1a toward the common source line (2). Can be removed, which is an essential process in 0.25 μm technology. With the introduction of SAS technology, we can reduce cell size by approximately 20%.

Next, referring to FIG. 2, an array state of a plurality of flash memory cells is shown in a plan view when SAS technology is not used as in FIG. 1A. As shown, a plurality of flash memory cells each have a drain contact 10, and each cell is commonly connected through a series of common source lines 2 having a vertical direction with a bit line 9.

Next, referring to FIG. 3A, an array state of a plurality of flash memory cells is shown in a plan view when using SAS technology, and referring to FIG. 3B, a cross-sectional view taken along the line a-a of FIG.

As shown, in the case of using the SAS technique, a plurality of trench regions 8a formed in parallel with the bit lines 9 (filled with oxide films by high density plasma in the trench regions become the device isolation regions 8) and Ion implantation into the active region 1 forms a series of common source lines 2. Therefore, the shape of the common source line 2 is substantially square in cross section.

However, since the junction, that is, the common source line 2 is formed in a substantially square wave shape along the surface of the trench region 8a and the surface of the active region 1, as shown in FIG. 3B, the actual resistance per cell tends to increase rapidly. There is this. The reason why the resistance of the common source line 2 is increased in this way is that since the junction resistance is formed along the surface shape of the trench region 8a as shown in FIG. 3B, the actual sheet resistance length is long, and the trench region 8a is This is because the sidewall resistivity itself becomes large. In other words, a relatively small amount of ions are implanted into the sidewall of the trench region 8a during diffusion or ion implantation, so that the resistance is very high.

Referring to FIG. 4, a flash memory circuit including a source resistor when the common source line is used as shown in FIG. 3A is illustrated.

As shown in the figure, when the resistance per cell increases, the source contact is formed every 16, so the degree of back bias is different due to the IR voltage drop between the first and eighth cells. Therefore, an error may occur when reading the flash memory. In particular, since the flash memory uses an internal high voltage, as the cell size is reduced, the trench region is deepened, which is increasingly detrimental to the source resistance.

Meanwhile, Table 1 below calculates the IR voltage drop when the source resistance is 600 mA per cell. The voltage difference between the first and eighth cells is about 0.06V, indicating that the current difference occurs due to the VDS difference. Here, the resistance display indicates the source resistance of one cell.

1st cell 2nd cell Third cell 4th cell 5th cell 6th cell 7th cell 8th cell 9th cell One 2 3 4 5 6 7 8 9 Left resistance 600 1200 1800 2400 3000 3600 4200 4800 5400 Right resistance 9600 9000 8400 7800 7200 6600 6000 5400 4800 Total resistance 564.7 1058.8 1482.4 1835.3 2117.6 2329.4 2470.6 2541.2 2541.2 IR drop 0.017 0.032 0.044 0.055 0.064 0.070 0.074 0.076 0.076

Next, referring to FIG. 5A, a plan view of a flash memory cell to which the conventional SAS technology is applied is shown, and referring to FIGS. 5B and 5C, cross-sectional views of a-a and b-b lines of FIG. 5A are shown.

First, as shown in FIG. 5B, the cross section aa of FIG. 5A has a silicon substrate 14 protruding toward the bit line 9 to form an active region 1, and both sides of the active region 1 are actually formed. The trench region 8a in which the element isolation region 8 is formed is formed. Here, as described above, it can be seen that the common source line 2 having a substantially square wave shape in cross section is formed on the sidewall of the trench region 8a and the surface of the active region 1.

In addition, as shown in FIG. 5C, the bb line cross-section of FIG. 5A has a contact 10 formed on the silicon substrate 14, and a floating gate 16 and a control gate are formed on the right side of the contact 10. 6) is formed, and no trench region is formed on the right side of the gates 16 and 6. 5B and 5C are shown as simplified as possible so as not to obscure the subject matter of the present invention, and in FIG. 5B and 5C, the device isolation regions (eg, oxide films) filled in the trench regions 8a ( 8) Also not shown for convenience of understanding.

As described above, the STI technology and the SAS technology are essential technologies for reducing the X-axis and the Y-axis of the cell. When the two technologies are applied at the same time, the source resistance increases several times.

In other words, when SAS technology is applied in a typical LOCOS (Local Oxidation of Silicon) isolation technology, the resistance per cell is 300kW, but when STI is applied, it is about 1000kW / cell. As a result, a high source resistance during programming and reading of the flash memory causes an IR voltage drop. Therefore, the voltage of the source terminal becomes high, resulting in a low VDS value, resulting in a malfunction of the device due to poor read and programming efficiency. .

SUMMARY OF THE INVENTION The present invention is to overcome the above-described problems, and an object of the present invention is to provide a source when a shallow trench isolation (STI) technique and a self-aligned floating gate (SAS) technique are simultaneously applied to reduce a flash memory cell size. The present invention provides a source resistance improving structure of a flash memory and a method of manufacturing the same that can significantly improve resistance.

FIG. 1A is a plan view showing a flash memory cell when the SAS (Self Aligned Floating Gate) technology is not applied, and FIG. 1B is a plan view showing a flash memory cell when the SAS Technology is applied.

Fig. 2 is a plan view showing the array state of flash memory cells when SAS technology is not used.

FIG. 3A is a plan view showing an array state of a flash memory cell in the case of using the SAS technology, and FIG.

FIG. 4 is a circuit diagram illustrating a flash memory circuit including a source resistor when using a common source line as shown in FIG. 3A.

Fig. 5A is a plan view showing a flash memory cell to which the conventional SAS technology is applied, and Figs. 5B and 5C are cross sectional views taken along lines a-a and b-b of Fig. 5A.

6A is a plan view showing a flash memory cell to which the SAS technology according to the present invention is applied, and FIGS. 6B and 6C are cross-sectional views taken along lines a-a and b-b of FIG. 6A.

FIG. 7A is a plan view showing the layout of the trench mask, and FIG. 7B is a plan view showing the trench region implemented in the actual wafer.

FIG. 8A is a plan view showing a layout of a trench mask to which optical proximity correction (OPC) is applied, and FIG. 8B is a plan view showing trench regions implemented in an actual wafer.

9A to 9C are a plan view and a sectional view showing one example of a method of manufacturing a flash memory according to the present invention.

Description of the main symbols in the drawings

One; Active region 2; Common Source Line

4; Gap 6 from the gate towards the source; Control gate

8; Device isolation region 8a; First trench region

8b; Second trench region 9; Bit line

10; Contact 14; Silicon substrate

16; Floating gate 18; Trench mask

19; Optical proximity correction area 20; Oxide film

22; Nitride film 24; High density oxide film

In order to achieve the above object, the present invention provides a common source line in a direction perpendicular to the conductive well, floating gate, control gate, contact, and bit line directions in the active region of the silicon substrate, and in the outer periphery of the active region. In the region where the region is formed, the active region and the trench region are alternately formed in parallel with the bit line direction, and the common source line is formed by ion implanting a portion of the common source line in the trench region.

The trench region may be parallel to the bit line direction, and may be formed in a first trench region formed at left and right sides of each active region, and perpendicular to the first trench region, and may be parallel to the common source line. And a second trench region formed to include a portion of the common source line.

In addition, all sidewalls of the second trench region where the common source line is formed are formed to have a minimum source resistance.

In order to achieve the above object, according to the present invention, an active region is provided in a silicon substrate, and a trench region is divided into a first trench region and a second trench region at an outer periphery of the active region, and the first trench region is formed. The semiconductor device of claim 1, wherein the second trench region is formed on the left and right sides of the active region in parallel with the bit line, and the second trench region is formed perpendicular to the first trench region. Sequentially forming a nitride film, etching the nitride film and the oxide film to remain only in the bit line direction using a mask, and etching and removing the nitride film and the oxide film remaining in the common source line region using a mask. And the silicon substress using the remaining nitride film as a hard mask. It characterized in that: etching the set has the step of forming the first and second trench region.

Here, after the trench manufacturing step, forming an oxide film having a predetermined thickness in the silicon substrate by a diffusion process, forming an oxide film in the trench by a high density plasma process, and chemically mechanical planarization of the oxide film by the high density plasma. Removing the remaining nitride film by a process, forming a well, a gate oxide film, a floating gate and a control gate in an active region of the silicon substrate, and opening a region where a common source line is to be formed; And removing the high density plasma oxide layer using a source mask, and forming a common source line by ion implantation using the source mask.

In this case, the trench region may further include an optical proximity correction region protruding from an edge of the trench mask so that an edge portion may be formed at substantially right angles, and the optical proximity correction region is a trench region.

As described above, according to the source resistance improving structure and manufacturing method of the flash memory according to the present invention, the problem of source resistance, which has been an obstacle when reducing the existing cell size in flash memory development, is solved, thereby improving the read and programming efficiency of the flash memory. There is an advantage to improve.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. Here, the same components as in the prior art will use the same reference numerals.

Referring to Fig. 6A, a plan view of a flash memory cell to which the SAS technology according to the present invention is applied is shown, and Figs. 6B and 6C are cross sectional views taken along lines a-a and b-b of Fig. 6A.

In the active region 1 of the silicon substrate 14, a common source perpendicular to the conductive wells (not shown), the floating gate 16, the control gate 6, the contact 10, and the bit line 9 directions. Lines 2 are formed, and trench regions 8a and 8b are formed on the outer periphery of the active region 1.

According to the present invention, the active region 1 and the trench regions 8a and 8b are alternately formed in parallel with the bit line 9 direction, and the common source line 2 is ion implanted into the trench region 8b. The main feature is that formed.

Here, the trench regions 8a and 8b are parallel to the bit line 9 direction, the first trench regions 8a formed on the left and right sides of the active regions 1, and the first trench regions. The second trench region 8b is formed in a direction perpendicular to 8a and is parallel to the common source line 2 and includes a portion of the common source line 2.

That is, the present invention is characterized in that the second trench region 8b in which the common source line 2 is formed is formed separately, and all sidewalls of the second trench region 8b are flat so that the source resistance thereof is minimized. It is formed.

In FIG. 6A, reference numeral 8 denotes an isolation region formed by filling an oxide film or the like into the first and second trench regions 8a and 8b, which are not shown in FIGS. 6B and 6C.

Referring to FIG. 7A, a planar layout of the trench mask 18 is shown, and referring to FIG. 7B, trench regions 8a and 8b, which are implemented in the actual silicon substrate 14, are shown.

As illustrated, when the corners of the trench mask 18 are formed at right angles, the corners of the trench regions 8a and 8b that are actually implemented are formed in a round shape, which is not preferable.

Meanwhile, referring to FIG. 8A, a planar layout of the trench mask 18 to which optical proximity correction (OPC) is applied is illustrated. Referring to FIG. 8B, the trench regions 8a, which are implemented in the actual silicon substrate 14, are illustrated. 8b) is shown.

As shown, the first and second trench regions 8a and 8b further form an optical proximity correction region 19 protruding from the corner of the trench mask 18 so that the corner portions may be formed at substantially right angles. Preferably, the optical proximity correction region 19 is a trench region 8a, 8b. In this manner, the corners of the first and second trench regions 8a and 8b which are actually formed in the silicon substrate 14 are formed at approximately right angles.

Next, referring to Figs. 9A to 9C, an example of a method of manufacturing a flash memory according to the present invention is shown.

First, the pad oxide film 20 and the pad nitride film 22 are sequentially formed on the silicon substrate 14.

Subsequently, by using the trench mask 18, the nitride film 22 and the oxide film 20 are etched and removed so as to remain only in the direction of the bit line 9 (see FIG. 6A). (See FIG. 9A)

Next, the nitride film 22 and the oxide film 20 remaining in the region to be the common source line 2 are etched and removed using a trench mask (see Fig. 9B).

Finally, the silicon substrate 14 is etched using the remaining nitride film 22 as a hard mask to form first and second trench regions 8a and 8b (see FIG. 8B) (see FIG. 9C).

Of course, after this process, a normal flash memory manufacturing process is performed as it is.

In other words, an oxide film having a predetermined thickness is formed on the silicon substrate 14 by a diffusion process.

Next, an oxide film 24 is formed in the first and second trench regions 8a and 8b by a high density plasma process.

Subsequently, the oxide film 24 by the high density plasma is removed by a chemical mechanical planarization process, and the remaining nitride film 22 is also removed.

Subsequently, a well, a gate oxide layer, a floating gate 16, and a control gate 6 are formed in the active region 1 of the silicon substrate 14, and a source mask is formed so that the region where the common source line 2 is formed is opened. To form.

Next, the high density plasma oxide film 24 is removed using a source mask.

Finally, the ion source is implanted using the source mask so that the common source line 2 is formed flat in the second trench region 8b with low resistance, thereby producing a flash memory according to the present invention.

As described above, according to the source resistance improving structure and manufacturing method of the flash memory according to the present invention, the problem of source resistance, which has been an obstacle when reducing the existing cell size in flash memory development, is solved, and the read and programming efficiency of the flash memory is solved. Has the effect of improving.

What has been described above is only one embodiment for implementing the source resistance improving structure and manufacturing method of the flash memory according to the present invention, the present invention is not limited to the above-described embodiment, it is claimed in the claims As will be apparent to those skilled in the art without departing from the gist of the present invention, the technical spirit of the present invention to the extent that various changes can be made.

Claims (6)

In a flash memory in which a conductive source, a floating gate, a control gate, a contact, and a common source line perpendicular to the bit line direction are formed in an active region of a silicon substrate, and a trench region is formed at an outer periphery of the active region. Wherein the active region and the trench region are alternately formed in parallel with the bit line direction, and the common source line is formed by ion implantation into the trench region. The common trench of claim 1, wherein the trench region is parallel to the bit line direction, and is formed in a first trench region formed at left and right sides of each active region, and is perpendicular to the first trench region. And a second trench region which is parallel to the line and formed to include a portion of the common source line. 3. The source resistance improvement structure of a flash memory according to claim 1 or 2, wherein all sidewalls of the second trench region where the common source line is formed are formed to have a minimum source resistance. An active region is provided in the silicon substrate, and a trench region is formed on the outer periphery of the active region by dividing the first trench region and the second trench region, and the first trench region is parallel to a bit line. In the left and right of the, and the second trench region is a flash memory manufacturing method which is formed perpendicular to the first trench region, Sequentially forming a pad oxide film and a pad nitride film on the silicon substrate; Etching by using a mask so that the nitride film and the oxide film remain only in the bit line direction; Etching away the nitride film and the oxide film remaining in the common source line region using a mask; And, And etching the silicon substrate to form the first and second trench regions by using the remaining nitride layer as a hard mask. The method of claim 4, wherein after the trench manufacturing step Forming an oxide film having a predetermined thickness on the silicon substrate by a diffusion process; Forming an oxide film on the trench by a high density plasma process; Removing the oxide film by the high density plasma by a chemical mechanical planarization process and removing the remaining nitride film; A source mask step of forming a well, a gate oxide layer, a floating gate, and a control gate in an active region of the silicon substrate, and opening a region where a common source line is to be formed; Removing the high density plasma oxide film using a source mask; And, Forming a common source line by ion implantation using the source mask. The method of claim 4, wherein the trench region further includes an optical proximity correction region protruding from an edge of the trench mask so that the corner portion is formed at a right angle, and the optical proximity correction region is a trench region. The manufacturing method of the flash memory.