KR20080114183A - Method for fabricating semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to reduce a contact resistance by increasing a contact area between a plug and an active region. An element isolation layer(22A) is formed on a substrate. A plurality of active regions(21) with a long axis and a short axis are defined by the isolation layer. An insulating layer(23A) is formed on the substrate including the element isolation layer. A contact hole to expose a part of a lateral side of an active region is formed by etching an insulating layer and a part of the element isolation layer. A plug embedded in the contact hole is formed.

Description

Semiconductor device manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

1 is a cross-sectional view illustrating a method for increasing the contact area between a plug and a junction region formed in an active region in the prior art;

2 is a plan view for explaining a method for forming a 'landing plug according to a first embodiment of the present invention.

3A and 3B are cross-sectional views of a process for forming a landing plug using the mask pattern manufactured in FIG. 2.

Figure 4 is a plan view for explaining a method for forming a 'landing plug according to a second embodiment of the present invention.

5A and 5B are cross-sectional views of a process for forming a landing plug using the active region and the mask pattern manufactured in FIG. 4.

Explanation of symbols on the main parts of the drawings

21: active area 22A: device isolation film

23A: insulating film 26: landing plug

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly to a method for increasing the contact area between a landing plug and an active region during a semiconductor device manufacturing process.

As the degree of integration of a semiconductor device increases, the size of the contact hole connecting the device and the device or the layer and the layer to the conductive film decreases, while the thickness of the interlayer insulating film increases. Therefore, the aspect ratio of the contact hole increases, so that the alignment margin of the contact hole decreases, thereby making it difficult to form a contact hole of fine size. Therefore, in the DRAM device, a landing plug is used to reduce the aspect ratio of the contact hole. The landing plug serves to connect the board and the storage node, and the board and the bit line.

However, the formation area of the landing plug is reduced due to the increasing degree of integration, and the contact area between the landing plug and the substrate is reduced. As the contact area between the substrate and the landing plug decreases, the contact resistance increases, and when the contact resistance increases, the driving of the device is adversely affected.

Recently, in order to solve this problem, as shown in FIG. 1, the active region 11 of the region where the landing plug is to be formed is partially recessed, and the landing plug 15 is formed in the recess region to form a junction region. The contact area with (13) was increased. In this case, the junction region 13 may be formed by an ion implantation process before the landing plug 15 is formed, or may be formed by diffusing impurities of the landing plug 15 into the active region 11.

However, such a method also causes a problem in that the junction region 13 is formed to the lower portion of the gate lines G1 to G4 by the recess of the active region 11, resulting in a shortening of the channel 14, and thus the junction region 13. There is a problem that it is difficult to control the width of the formation.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device which reduces contact resistance by increasing the contact area between the plug and the substrate without reducing the channel length. .

According to an aspect of the present invention for achieving the above object, forming a device isolation film on the substrate, thereby defining a plurality of active regions having a long axis and a short axis, forming an insulating film on the substrate including the device isolation film Forming a contact hole to etch the insulating layer and to etch a portion of the device isolation layer to expose a portion of the sidewall surface of the active region, and to form a plug embedded in the contact hole. It provides a manufacturing method.

In addition, according to another aspect of the present invention, forming a device isolation film on the substrate, through which is defined in a zigzag form a plurality of active regions having a short axis and a long axis, a plurality of crossing in the short axis direction of the active region Forming a gate line, forming an insulating film on a substrate including the gate line, and a region overlapping a portion of the device isolation layer formed on at least the active region adjacent to each other in a short axis direction of the active region on the insulating film Forming an open etching mask, etching the insulating layer using the etching mask, and etching a portion of the device isolation layer to form a contact hole exposing a portion of the sidewall surface of the active region; and in the contact hole It provides a method for manufacturing a semiconductor device comprising the step of forming a plug to be embedded.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

FIG. 2 is a plan view illustrating a method for forming a landing plug according to a first embodiment of the present invention, and particularly a mask pattern for forming a landing plug contact hole.

As shown in FIG. 2, the device isolation layer 22 is formed on the substrate, and a plurality of active regions 21 are arranged in a zigzag form and have a short axis and a long axis.

The device isolation layer 22 is formed by a shallow trench isolation (STI) process having excellent insulating properties between devices. In addition, the active region 21 has an island shape.

Subsequently, a plurality of gate lines 23 intersecting in the short axis direction of the active region 21 are formed on the resultant device on which the device isolation layer 22 is formed.

The gate line 23 may have a structure in which a gate insulating film, a gate conductive film, and a gate metal film are sequentially stacked. The gate line 23 may further include a gate hard mask film as a protective film on the gate metal film.

Subsequently, impurities are injected into both active regions 21 of the gate line 23 to form a junction region. Alternatively, it may be formed by diffusing impurities of the landing plug formed in a subsequent process.

Subsequently, an insulating film 34 is formed on the resultant product on which the gate line 23 is formed.

The insulating film 24 is a thin film formed for insulating between layers, and may be an oxide-based thin film, for example, an HDP (High Density Plasma) oxide film or a BPSG (Boron Phosphorus Silicate Glass) film.

Subsequently, a mask pattern 25 in which a region overlapping with a portion of the device isolation layer 22 formed between at least the active regions adjacent to each other in the short direction of the active region 21 is formed is formed. Thus, in order for the mask pattern 25 to have an open area, the mask pattern 25 must have a half moon shape. For example, the open area is referred to as '27'. The mask pattern 25 may be formed of photoresist.

A portion of the insulating film 24 and the device isolation film 22 are etched using the mask pattern 25 formed as described above. Hereinafter, the process pattern is changed to a cross-sectional view for convenience of description.

3A and 3B are cross-sectional views of a process for forming a landing plug using the mask pattern 25 manufactured in FIG. 2. In the following description, reference numerals of FIG. 2 are cited.

As shown in FIG. 3A, the insulating layer 24 is etched using the mask pattern 25, but a portion of one side wall surface of the active region 21 is exposed by etching the insulating layer 24. 25).

In this case, the substrate 21 may be excessively etched to increase the contact area between the landing plug and the active region 21 formed in a subsequent process. The transient etching of the substrate 21 preferably has a range in which the channel length is not reduced, for example, 200 to 500 kPa.

Next, the mask pattern 24 is removed.

As shown in FIG. 3B, a landing plug 26 embedded in the contact hole 25 is formed.

The landing plug 26 thus formed is in contact with a portion of the one side wall surface of the active region 21 and the upper surface. The landing plug 26 is formed of a conductive material, for example, a polysilicon film.

As a result, a landing plug 26 having an increased contact area with the active region 21 is manufactured.

The landing plug 26 according to the first embodiment as described above is formed to contact not only the upper surface of the active region 21 but also one side of the active region 21 to increase the contact area between the active regions 21.

This is not a method of increasing the contact area by etching the active region 21 as in the related art, and the channel length does not decrease even if the channel length is not shortened even when the active region 21 is etched.

Therefore, if the contact area between the LAN plug 26 and the active region 21 is increased without reducing the channel length, the contact resistance can be reduced, thereby increasing the efficiency of signal transmission between the devices.

FIG. 4 is a plan view illustrating a method for forming a landing plug according to a second embodiment of the present invention. In particular, FIG. 4 illustrates a plane relationship between an active region and a mask pattern for forming a landing plug contact hole. to be.

As shown in FIG. 4, an isolation layer 32 is formed on a substrate, and a plurality of active regions 31 are defined in a zigzag form and have a short axis and a long axis.

The device isolation layer 32 is formed by an STI (Shallow Trench Isolation) process having excellent inter-device insulating properties, and is formed of an oxide-based thin film, for example, an HDP (High Density Plasma) oxide film or a BPSG (Boron Phosphorus Silicate Glass) film.

In the active region 31, both ends of the major axis in the plane are thinner than the central portion. In detail, the critical dimension of both ends of the long axis direction of the active region 31 is shorter than that of the central portion.

Subsequently, a plurality of gate lines 33 intersecting in the short direction of the active region 31 are formed on the resultant device on which the device isolation layer 32 is formed.

The gate line 33 may have a structure in which a gate insulating layer, a gate conductive layer, and a gate metal layer are sequentially stacked, and may further include a gate hard mask layer as a protective layer on the gate metal layer.

Subsequently, an insulating film 34 is formed on the resultant formed gate line 33.

The insulating film 34 is a thin film formed for insulating between layers and is formed of an oxide-based thin film, for example, an HDP (High Density Plasma) oxide film or a BPSG (Boron Phosphorus Silicate Glass) film.

Subsequently, a mask pattern 35 in which a region overlapping with a portion of the device isolation layer 32 formed between at least the active regions adjacent to each other in the short direction of the active region 31 is formed. An example of an open area is denoted by '37'. The open area 37 may be opened by the active area 31 having a shorter short axis width at both ends than the center. In this case, the mask pattern 35 may have a bar shape and may be formed of a photoresist.

A portion of the insulating film 35 and the device isolation film 22 are etched using the mask pattern 35 formed as described above. Hereinafter, the process pattern is changed to a cross-sectional view for convenience of description.

5A and 5B are cross-sectional views of a process for forming a landing plug using the active region 31 and the mask pattern 35 fabricated in FIG. 4. In the following description, reference numerals of FIG. 4 are cited.

As shown in FIG. 5A, the insulating layer 34 is etched using the mask pattern 35, but the portion of the sidewalls of the active region 31 is exposed by etching to the part of the isolation layer 32. ).

In this case, the substrate 31 may be excessively etched to increase the contact area between the landing plug and the active region 31 formed in a subsequent process. The transient etching of the substrate 31 has a range in which the channel length is not reduced, for example, in the range of 200 to 500 kPa.

Subsequently, the mask pattern 34 is removed.

As shown in FIG. 5B, a landing plug 36 embedded in the contact hole 35 is formed.

The landing plug 36 may be referred to as a storage node landing plug or a bit line landing plug, and contacts a portion and an upper surface of both sidewalls of the active region 31. The landing plug 36 is formed of a conductive material, such as a polysilicon film.

As a result, a landing plug 36 having an increased contact area with the active region 31 is manufactured.

The landing plug 36 according to the second embodiment as described above is formed not only on the upper surface of the active region 31 but also on both sides of the active region 31 to increase the contact area between the active regions 31.

This is not a method of increasing the contact area by etching the active region 31 as in the related art, and the channel length does not decrease even if the channel length is not shortened even when the active region 31 is etched.

Therefore, when the contact area between the LAN plug 36 and the active region 31 is increased without reducing the channel length, the contact resistance can be reduced, thereby increasing the efficiency of signal transmission between devices.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

As described above, the present invention reduces the contact resistance by increasing the contact area between the plug and the junction region formed in the active region.

Therefore, the signal transmission characteristic of a semiconductor element can be improved.

Claims (9)

Forming an isolation layer on the substrate, and defining a plurality of active regions having a long axis and a short axis through the device isolation film; Forming an insulating film on the substrate including the device isolation film; Etching the insulating layer to form a contact hole exposing a part of the sidewall surface of the active region by etching a portion of the device isolation layer; And Forming a plug embedded in the contact hole Semiconductor device manufacturing method comprising a. The method of claim 1, The sidewall surface of the exposed active region is one side wall surface or both side wall surface. The method of claim 1, And the plug is in contact with a portion of the sidewall and the top of the active region. The method of claim 1, The active region has a shortened line width at both ends of the long axis direction is shorter than the shortened line width at the center portion. The method of claim 1, The device isolation film and the insulating film is a semiconductor device manufacturing method of forming an oxide film series. Forming a device isolation film on the substrate, and defining a plurality of active regions disposed in a zigzag form and having a short axis and a long axis; Forming a plurality of gate lines crossing in the axial direction of the active region; Forming an insulating film on the substrate including the gate line; Forming an etch mask on the insulating layer, the region of which overlaps with a portion of the device isolation layer formed between at least the active regions adjacent to each other in the minor direction of the active region; Etching the insulating layer using the etching mask, and etching a portion of the device isolation layer to form a contact hole exposing a portion of the sidewall surface of the active region; And Forming a plug embedded in the contact hole Semiconductor device manufacturing method comprising a. The method of claim 6, And forming a portion of the one side wall surface or both side wall surfaces of the active region in the forming of the contact hole. The method of claim 6, And wherein the active region has a shorter line width at both ends of the long axis direction than a shorter line width at the center portion. The method of claim 6, The device isolation film and the insulating film is a semiconductor device manufacturing method of forming an oxide film based.

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