KR20040060410A - A method for designing a layout of a semiconductor device - Google Patents

Abstract

PURPOSE: A layout method of a semiconductor device is provided to improve cell write margin by improving the contact area of a bit line contact without increasing contact resistance. CONSTITUTION: An isolation region(33) is defined for defining the first active region(31a) of I-type and the second active region(31b). A word line region(35) is defined for dividing the active region to a storage node contact part(39), a bit line contact part(37) and a word line contact part. At this time, the word line region is designed to the size of 1F, the distance of the word line region on the storage node contact part is 1F+α (0<α<F), and the distance of the word line region on the bit line contact part is 1F-α, thereby increasing the area of the storage node contact part. The second active region has cross shape to compensate the reduced area of the bit line contact part. The F presents minimum line-width of line/space pattern.

Description

A method for designing a layout of a semiconductor device

The present invention relates to a layout method of a semiconductor device, and more particularly, to a method of designing a cell layout to improve a cell write margin (tWR) characteristic of a DRAM.

Currently, DRAM devices are becoming highly integrated, and high integration of the cell array area, which occupies the largest area ratio of DRAM devices, is a key task of DRAM integration.

The most difficult problem in the yield securing step of the development stage of the highly integrated DRAM is to secure the tWR characteristic, which is closely related to the current drivability of the cell transistor.

As semiconductor devices are highly integrated, the area of the cell transistors is becoming smaller and smaller.The source / drain junction area contact area of the highly integrated cell transistors is reduced, the resistance is increased to several KΩ or more, so that the cell current flow characteristics are weak. It is difficult to secure the characteristics.

1 shows a layout of a semiconductor device according to the prior art.

First, an isolation region 13 defining an I-type active region 11,

A plurality of word line regions 15 are designed to divide the active region 11 into three parts and intersect the I type. At this time, the distance between the word line region 15 is formed to a size of 1F. Here, 1F denotes a minimum line width of a line / spacer pattern that can be defined in a semiconductor device manufacturing process.

Here, an external source junction region, that is, a storage electrode contact portion 19, which is divided into the word line region 15, is illustrated, and a bit line contact portion, which is a drain junction region, is divided into a center portion of the active region 11. 17) is shown. The storage electrode contact portion 19 and the bit line contact portion 17 are designed to have a line width of 1F.

Then, in order to prevent a phenomenon in which both ends of the active region 11 are in contact with the word line region 15, the word line regions 15 positioned at both ends of the active region 11 are bent by shaving. The active region 11 and the word line region 15 may be maintained at a predetermined interval.

However, the resistance of the storage electrode contact portion 19 is more important than the resistance of the bit line contact hole 17 in terms of controlling the current flow of the cell transistor in relation to the tWR characteristic of the actual cell transistor.

In other words, a method of securing a storage electrode contact area that serves as a source of a transistor is required in terms of securing current flow of a cell transistor in terms of the tWR characteristic.

Therefore, as the semiconductor device is highly integrated, a problem arises in that the tWR characteristic of the device is degraded.

In order to solve the above problems of the prior art, the storage electrode contact portion of the active region provided as the word line region is exposed to have a line width of 1F + α (0 <α <F), and the bit line contact portion is 1F. To expose the line width of -α, but to design a bit line contact portion in the cross shape to increase the area of the bit line and the storage electrode contact portion to provide a semiconductor device layout method to ensure the tWR characteristics of the semiconductor device The purpose is.

1 is a layout diagram of a semiconductor device according to the prior art.

2A and 2B are layout views of a semiconductor device according to the present invention.

<Explanation of symbols for main parts of drawing>

11,31a, 31b: active region 13,33: device isolation region

15,35: word line region 17,37: bit line contact portion

19,39: storage electrode contact portion

Method of forming a semiconductor device according to the present invention for achieving the above object,

A word isolation region defining a first active region of type I and a second active region crossing the same, and partitioning the active region into three portions of a storage electrode contact portion, a bit line contact portion, and a word line contact portion; Define a line region, wherein the word line region is designed to have a size of 1F, the word line region spacing on the storage electrode contact portion is designed to have a size of 1F + α (0 <α <F), and the bit line contact portion The word line area spacing of the yarn is designed to be 1F-α (0 <α <F) to increase the area of the storage electrode contact portion.

The second active region is disposed in the bit line contact portion to form a cross shape (+) with the I-type to compensate for the decrease in the area of the bit line contact portion reduced when the area of the storage electrode contact portion is increased.

The word line region overlapping the outer side of the storage electrode contact portion is cut out so that the first active region and the word line region of the storage electrode contact portion are spaced apart by a predetermined distance, provided that F is the minimum line width of the line / space pattern. Shows)

The bit line contact portion is a drain junction region of a first active region, and the storage electrode contact portion is a source junction region of a first active region;

The bit line contact portion may be designed to have a size in which a center portion of the first active region divided into the word line region and a second active region are added together.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A and 2B show a layout method of a semiconductor device according to the present invention.

Referring to FIG. 2A, a plurality of device isolation regions 33 defining the first active region 31a of type I and the first active region 31a are divided into three portions and intersected with the type I. Is designed a word line region 35 of. In this case, the word line region 35 divides a source junction region, that is, a storage electrode contact portion 39, to the outside, and is a bit line contact portion 37, which is a drain junction region partitioned at a central portion of the first active region 31. ), Wherein the spacing of the word line region 35 on the storage electrode contact portion 39 is 1F + α (0 <α <F), and the word line region 35 on the bit line contact portion 37 is formed. The interval is 1F-α (0 <α <F) and the word line region 35 is 1F.

The bit line contact portion 37 crosswise crosses the first active region 31a of the bit line contact portion 37 so as to secure a contact area narrowed to a size of 1F-α (0 <α <F). By designing the second active region 31b, the size of the bit line contact portion 37 is the sum of the center portion of the first active region 31a and the second active region 31b divided into the word line region 35. It is formed in size.

It is possible to reduce the contact resistance of the bit line contact process formed in a subsequent process.

Referring to FIG. 2B, after the process of FIG. 2A, the word line region 35 is formed by cutting the word line region 35 at regular intervals so that the active region 31a and the word line region 35 are not connected to each other in the dotted line of FIG. 2A. do.

Here, the dotted line shows the minimum designed wordline region 35.

As described above, in the semiconductor device layout method, the contact area of the storage electrode contact portion is secured to secure a large contact area during the storage electrode contact process, thereby reducing the contact resistance of the storage electrode contact. It is possible to improve the tWR characteristics of the semiconductor device, thereby improving the characteristics and reliability of the semiconductor device and thereby enabling the high integration of the semiconductor device.

Claims (3)

A word isolation region defining a first active region of type I and a second active region crossing the same, and partitioning the active region into three portions of a storage electrode contact portion, a bit line contact portion, and a word line contact portion; Define a line region, wherein the word line region is designed to have a size of 1F, the word line region spacing on the storage electrode contact portion is designed to have a size of 1F + α (0 <α <F), and the bit line contact portion The word line area spacing of the yarn is designed to be 1F-α (0 <α <F) to increase the area of the storage electrode contact portion. The second active region is disposed in the bit line contact portion to form a cross shape (+) with the I-type to compensate for the decrease in the area of the bit line contact portion reduced when the area of the storage electrode contact portion is increased. And a word line region overlapping an outer portion of the storage electrode contact portion by designating the first active region and the word line region of the storage electrode contact portion spaced apart from each other by a predetermined distance. (Where F represents the minimum line width of the line / space pattern) The method of claim 1, And the bit line contact portion is a drain junction region of the first active region, and the storage electrode contact portion is a source junction region of the first active region. The method of claim 1, And the bit line contact portion is designed to have a size in which a center portion of the first active region divided into the word line region and a second active region are combined.