KR20040060331A - A method for forming a metal line of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a metal interconnection of a semiconductor device is provided to prevent damage of a hard mask by damascene processing using the third etch barrier layer. CONSTITUTION: The first interlayer dielectric(43) is formed to expose a lower metal line(41). The first etch stop layer(45), the second interlayer dielectric(47), the second etch stop layer(49), the third interlayer dielectric(51), and a hard mask(53) are sequentially stacked on the resultant structure. A via contact hole is formed to expose the lower metal line by etching the stacked structure. The third etch barrier layer(57) is formed on the via contact hole. An organic anti-reflective coating layer is filled in the via contact hole. The second etch barrier layer is exposed by etching the organic anti-reflective coating layer, the third etch barrier layer, the hard mask, and the third interlayer dielectric. The organic anti-reflective coating layer is removed. By selectively etching the third etch barrier layer, an upper metal line region(63) is formed to expose the lower metal line and to remain the third etch barrier layer at the sidewall of the via contact hole and on the hard mask.

Description

A method for forming a metal line of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring in a semiconductor device, and more particularly, to a technique for forming a multi-layered metal wiring using a damascene method.

When the structure of the semiconductor device is analyzed, a plurality of electrical wiring layers are basically stacked in the vertical direction, and the upper and lower wiring layers are connected to each other.

As an example of a logic device, a gate, a metal layer, and the like correspond to electrical wiring layers, and a contact hole layer connecting the gate layer and the metal layer or a via contact hole layer connecting the upper and lower metal layers correspond to the connection layer.

In general, the metal wiring method of the semiconductor device has proceeded to a process of forming an interlayer insulating film for patterning and planarizing the metal wiring on the planarized surface, but the patterning of the metal wiring with the fine line width due to the high integration of the semiconductor device has not been easy.

In order to solve this problem, a damascene method of forming an interlayer insulating film having an area where a metal wiring is to be formed is etched on a planarized surface and embedding the interlayer insulating film is used.

1A to 1E are cross-sectional views illustrating a metal wiring forming method of a semiconductor device according to the prior art.

Referring to FIG. 1A, an isolation layer (not shown), a word line (not shown), a bit line (not shown), and a capacitor (not shown) defining an active region are formed on a semiconductor substrate (not shown) and formed thereon. A lower insulating layer (not shown) is formed to planarize.

A lower metal wiring 11 connected to the lower structure of the lower insulating layer is formed. In this case, the lower metal wiring 11 is formed using copper.

The planarized first interlayer insulating film 13 exposing the lower metal wiring 11 is formed on the entire surface.

A stacked structure of the first etch stop film 15, the second interlayer insulating film 17, the second etch stop film 19, the third interlayer insulating film 21, and the hard mask layer 23 is formed on the entire surface.

The first etch stop layer 15 is exposed by etching the stacked structure from the top by a photolithography process using a metal wiring contact mask (not shown), that is, a via contact mask (not shown).

Referring to FIG. 1B, an organic antireflection film 27 is coated on the entire surface.

The photoresist pattern 29 is formed on the organic antireflection film 27. In this case, the photoresist pattern 29 is formed by an exposure and development process using a metal wiring mask (not shown).

Referring to FIG. 1C, the organic anti-reflection film 27, the hard mask layer 23, and the third interlayer insulating film 21 are etched using the photoresist pattern 29 as a mask to form the second etch stop layer 19. Expose At this time, the organic antireflection film 27 remains between the second interlayer insulating film 17 and the first antireflection film 15.

Referring to FIG. 1D, the photoresist pattern 29 is removed and the organic antireflection film 15 is removed.

Referring to FIG. 1E, an upper metal wiring region 31 contacting the lower metal wiring 11 is formed by removing the first etch stop layer 15 on the lower metal wiring 11 by an etching process.

In this case, the etching process is performed without a mask, and the second anti-reflection film 19 and the hard mask layer 23 having a predetermined thickness are etched and corners of the hard mask layer 23 and the second interlayer insulating film 17 are etched. The part is etched like the ⓐ part.

The corner portion of the hard mask layer 23 of the ⓐ portion has a problem of deteriorating the electrical characteristics of the metal wiring by shortening the distance between the upper metal wiring formed in a subsequent process than the designed distance.

FIG. 2 is a schematic image of a metal wiring formed according to the prior art, and it can be seen that the space CD (critical dimension) between Cu wirings, which are metal wirings, is reduced.

The present invention is to solve the problems of the prior art, to form a metal wiring of the semiconductor device to prevent the deterioration of the electrical characteristics of the device to ensure the distance between the metal wiring during the forming process of the multi-layer metal wiring using the damascene method The purpose is to provide a method.

1A to 1E are cross-sectional views illustrating a metal wiring forming method of a semiconductor device according to the prior art.

Figure 2 is a schematic image showing a metal wiring of the semiconductor device according to the prior art.

3A to 3F are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

11,41 lower metal wiring 13,43 first interlayer insulating film

15,45: 1st etching prevention film 17,47: 2nd interlayer insulating film

19,49: Second etching prevention film 21,51: Third interlayer insulating film

23,53: Hard mask layer 25,55: Via contact hole

27,59: organic antireflection film 29,61: photoresist pattern

31,63: upper metallization region 57: third etch stop layer

In order to achieve the above object, a metal wiring forming method of a semiconductor device according to the present invention,

Forming a first interlayer insulating film forming a lower metal interconnection formed on the semiconductor substrate and exposing the lower metal interconnection;

Forming a stacked structure of a first etch stop layer, a second interlayer insulating layer, a second etch stop layer, a third interlayer insulating layer, and a hard mask layer on the entire surface thereof;

Forming a via contact hole exposing the lower metal wiring by etching the stacked structure by a photolithography process using a via contact mask;

Forming a third etch stop layer on the entire surface including the via contact hole;

Forming an organic anti-reflective coating on the entire surface of the via contact hole;

Etching the organic antireflection film, the third etch stop film, the hard mask layer, and the third interlayer insulating film by a photolithography process using an upper metal wiring mask to expose the second etch stop film;

By removing the organic anti-reflection film and etching the third etching prevention layer on the lower metal wiring to expose the lower metal wiring, leaving a third etching prevention layer on the sidewall of the via contact hole and the hard mask layer, the upper metal wiring Including a step of forming an area,

The second interlayer insulating film and the third interlayer insulating film may include an oxide film, an organic low-k layer (organic low-k, k is a dielectric constant), a porous organic low-k layer (k is a dielectric constant), and these To form any one selected from the group consisting of

The third etch stop layer is formed of a silicon nitride film (SiN) or a silicon carbon film (SiC),

The third etch barrier layer is formed in the bottom of the via contact hole 50 ~ 100 Å, the side wall 30 to 60 Å thickness and the top of the hard mask layer 50 to 200 두께 thickness, and

The etching process of the third etch stop layer may be performed by an RF sputtering process using an Ar plasma.

In addition, the metal wiring forming method of the semiconductor device according to the present invention in order to achieve the above object,

Forming a first interlayer insulating film forming a lower metal interconnection formed on the semiconductor substrate and exposing the lower metal interconnection;

Forming a stacked structure of an oxide film which is a first etch stop film, a second interlayer insulating film, a second etch stop film, and a third interlayer insulating film on the entire surface thereof;

Forming a via contact hole exposing the lower metal wiring by etching the stacked structure by a photolithography process using a via contact mask;

Forming a third etch stop layer on the entire surface including the via contact hole;

Forming an organic anti-reflective coating on the entire surface of the via contact hole;

Etching the organic anti-reflection film, the third etch stop film, and the third interlayer insulating film by a photolithography process using an upper metal wiring mask to expose the second etch stop film;

By removing the organic anti-reflection film and etching the third etching prevention layer on the lower metal wiring to expose the lower metal wiring, leaving a third etching prevention layer on the sidewall of the via contact hole and the hard mask layer, the upper metal wiring The second feature includes a step of forming a region.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3A to 3F are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.

Referring to FIG. 3A, an isolation layer (not shown), a word line (not shown), a bit line (not shown), and a capacitor (not shown) defining an active region are formed on a semiconductor substrate (not shown) and formed thereon. A lower insulating layer (not shown) is formed to planarize.

A lower metal wiring 41 is formed to be connected to the lower structure of the lower insulating layer. In this case, the lower metal wiring 41 is formed using copper.

The planarized first interlayer insulating film 43 exposing the lower metal wiring 41 is formed on the entire surface.

The first etch stop layer 45 is formed on the entire surface. In this case, the first etch stop layer 45 is used as a copper capping layer.

A second interlayer insulating layer 47 is formed on the first etch stop layer 45. In this case, the second interlayer insulating film 47 may include an oxide film, an organic low-k layer (organic low-k, k is a dielectric constant), an organic porous low-k layer (k is a dielectric constant), and these It is formed of any one selected from the group consisting of.

A second etch stop layer 49 is formed on the second interlayer insulating layer 47, and a third interlayer insulating layer 51 is formed on the second interlayer insulating layer 47. In this case, the third interlayer insulating layer 51 may include an oxide film, an organic low-k layer (organic low-k, k is a dielectric constant), an organic porous low-k layer (k is a dielectric constant), and these It is formed of any one selected from the group consisting of.

A hard mask layer 53 is formed on the third interlayer insulating layer 51. In this case, the third interlayer insulating film 51 may not be formed when the oxide film is formed.

The photolithography process using the metallization contact mask (not shown), that is, the via contact mask (not shown), is used to form the hard mask layer 23, the third interlayer insulating film 21, the second etching preventing film 19, and the second interlayer insulating film. (17) and the first etch stop layer 15 are etched to form a via contact hole 55 exposing the lower metal wiring 41.

Referring to FIG. 3B, a third etch stop layer 57 is formed on the entire surface including the via contact hole 55, and 50 to 100 mm thick is deposited on the bottom of the via contact hole 55. In this case, the third etch stop layer 57 is formed on the sidewalls of the via contact hole 55 to have a thickness of 30 to 60 mm 3, and is formed on the hard mask layer 53 to a thickness of 50 to 200 mm 3.

The third etch stop layer 57 is formed of a silicon nitride film (SiN) or a silicon carbon film (SiC).

Referring to FIG. 3C, an organic antireflection film 59 filling the via contact hole 55 is formed on the entire surface.

The photoresist layer pattern 61 is formed on the organic antireflection layer 59. In this case, the photoresist pattern 61 is formed by an exposure and development process using a metal wiring mask (not shown).

Referring to FIG. 3D, the organic anti-reflection film 59, the third etch stop layer 57, the hard mask layer 53, and the third interlayer insulating layer 51 are etched using the photoresist pattern 61 as a mask. A predetermined region is formed by a metal wiring that exposes the second etch stop layer 49. In this case, the organic antireflection film 59 and the third etch stop layer 57 remain between the second interlayer insulating layer 47 and the first etch stop layer 45.

Referring to FIG. 3E, the photoresist layer pattern 61 is removed and the organic antireflective layer 59 is removed.

Referring to FIG. 3F, the third etch stop layer 57 on the lower metal interconnection 41 is etched to expose the lower metal interconnection 41, and the sidewalls of the via contact hole 55 and the hard mask layer ( 53) the upper metal wiring region 63 is formed by leaving the third etch stop layer 57 thereon. At this time, the third etch barrier layer 57 on the hard mask layer 53 is reduced in thickness and the sidewalls are cut off to have a shape such as ⓑ, but the edge of the hard mask layer 53 is prevented from being etched. . Therefore, it is possible to maintain the distance between the upper metal wiring formed in a subsequent process, it is possible to prevent the deterioration of electrical characteristics as in the prior art.

The etching process of the third etch stop layer is performed by an RF sputtering process using an Ar plasma.

The third etch stop layer 57 on the sidewalls of the via contact holes 55 suppresses the phenomenon that impurities in the interlayer insulating layer are out-diffused into the copper wiring formed in a subsequent process.

In a subsequent process, a copper layer filling the upper metal wiring region 63 is formed on the entire surface and planarized to form an upper metal wiring (not shown).

The hard mask layer 53 is exposed by the planarization etch process, and the planarization etch process of the third etch stop layer 57 is performed in a CMP process using a slurry having a difference in etching selectivity from the hard mask layer 53. Conduct.

According to another embodiment of the present invention, when the third interlayer dielectric layer 51 is formed of an oxide layer, a separate hard mask layer 53 is not formed.

As described above, in the method of forming the metal wiring of the semiconductor device according to the present invention, the metal wiring is formed by the damascene method using the third etching prevention film to prevent the damage of the hard mask layer and to increase the distance between the upper metal wirings as much as the predetermined amount. It can be secured to prevent the deterioration of the electrical characteristics of the device, thereby providing an effect to improve the characteristics and reliability of the semiconductor device.

Claims (6)

Forming a first interlayer insulating film forming a lower metal interconnection formed on the semiconductor substrate and exposing the lower metal interconnection; Forming a stacked structure of a first etch stop layer, a second interlayer insulating layer, a second etch stop layer, a third interlayer insulating layer, and a hard mask layer on the entire surface thereof; Forming a via contact hole exposing the lower metal wiring by etching the stacked structure by a photolithography process using a via contact mask; Forming a third etch stop layer on the entire surface including the via contact hole; Forming an organic anti-reflective coating on the entire surface of the via contact hole; Etching the organic antireflection film, the third etch stop film, the hard mask layer, and the third interlayer insulating film by a photolithography process using an upper metal wiring mask to expose the second etch stop film; By removing the organic anti-reflection film and etching the third etching prevention layer on the lower metal wiring to expose the lower metal wiring, leaving a third etching prevention layer on the sidewall of the via contact hole and the hard mask layer, the upper metal wiring A metal wiring formation method for a semiconductor device comprising the step of forming a region. The method of claim 1, The second interlayer insulating film and the third interlayer insulating film include an oxide film, an organic low-k layer (organic low-k, k is a dielectric constant), an organic porous low-k layer (k is a dielectric constant), and these Forming a metal wiring of the semiconductor device, characterized in that formed in any one selected from the group consisting of. The method of claim 1, The third etch stop layer is formed of a silicon nitride film (SiN) or a silicon carbon film (SiC) characterized in that the metal wiring forming method. The method of claim 1, The third etch barrier layer is formed in the bottom of the via contact hole 50 ~ 100 Å, the side wall 30 ~ 60 Å thickness and the top of the hard mask layer 50 to 200 두께 thickness of the semiconductor device, characterized in that Metal wiring formation method. The method of claim 1, The etching process of the third etch stop layer is a metal wiring formation method of a semiconductor device, characterized in that performed by the RF sputtering process using an Ar plasma. Forming a flattened first interlayer insulating film for forming a lower metal wiring formed on the semiconductor substrate and exposing the lower metal wiring; Forming a stacked structure of an oxide film which is a first etch stop film, a second interlayer insulating film, a second etch stop film, and a third interlayer insulating film on the entire surface thereof; Forming a via contact hole exposing the lower metal wiring by etching the stacked structure by a photolithography process using a via contact mask; Forming a third etch stop layer on the entire surface including the via contact hole; Forming an organic anti-reflective coating on the entire surface of the via contact hole; Etching the organic anti-reflection film, the third etch stop film, and the third interlayer insulating film by a photolithography process using an upper metal wiring mask to expose the second etch stop film; By removing the organic anti-reflection film and etching the third etching prevention layer on the lower metal wiring to expose the lower metal wiring, leaving a third etching prevention layer on the sidewall of the via contact hole and the hard mask layer, the upper metal wiring A metal wiring formation method for a semiconductor device comprising the step of forming a region.