KR20040060115A - Method for forming interconnection between metal lines in semiconductor device fabrication process - Google Patents

Method for forming interconnection between metal lines in semiconductor device fabrication process Download PDF

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KR20040060115A
KR20040060115A KR1020020086644A KR20020086644A KR20040060115A KR 20040060115 A KR20040060115 A KR 20040060115A KR 1020020086644 A KR1020020086644 A KR 1020020086644A KR 20020086644 A KR20020086644 A KR 20020086644A KR 20040060115 A KR20040060115 A KR 20040060115A
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interconnection
metal wiring
forming
interconnect
wiring
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KR1020020086644A
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Korean (ko)
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KR100620159B1 (en
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박철수
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동부전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

PURPOSE: A method for forming an interconnection between a lower and upper metal line in a semiconductor device is provided to minimize the misalignment of the interconnection by firstly forming the lower and upper metal line and secondly forming the interconnection. CONSTITUTION: Lower metal lines(1) are formed on a semiconductor substrate. An insulating layer(2) for planarization is deposited on the resultant structure. The insulating layer is firstly etched by using the first photoresist pattern as an etching mask. Then, the insulating layer is secondly etched by using the second photoresist pattern as an etching mask. Upper metal lines(4) are formed in the second etched portions of the insulating layer. Plugs(6) for interconnection are formed between the lower and upper metal lines.

Description

반도체 소자 제조시 금속간 인터커넥션 형성방법{METHOD FOR FORMING INTERCONNECTION BETWEEN METAL LINES IN SEMICONDUCTOR DEVICE FABRICATION PROCESS}METHOD FOR FORMING INTERCONNECTION BETWEEN METAL LINES IN SEMICONDUCTOR DEVICE FABRICATION PROCESS}

본 발명은 반도체 소자 금속 배선 방법에 관한 것으로, 특히 반도체 소자 제조시 금속간 인터커넥션(Interconnection) 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device metallization method, and more particularly, to a method of forming interconnections between metals in the manufacture of semiconductor devices.

반도체 소자 제조시의 금속 배선은 하부 배선을 완료하고 상부 배선과 연결하기 위한 인터커넥션용 콘텍 플러그(Contact plug)를 형성한 다음 상부 배선을 완성하는 것이 지금까지의 일반적인 방법이었으며, 콘텍과 하부 배선 혹은 콘텍 플러그와 상부 배선의 오버랩(Overlap)에 대한 디자인 룰(Design rule)은 제로(zero) 이상이었다.In the manufacture of semiconductor devices, the conventional method has been to form a contact plug for interconnection for completing the lower wiring and connecting the upper wiring, and then completing the upper wiring. The design rule for overlap of the contact plug and the upper wiring was more than zero.

그러나 상기한 바와 같은 종래 하부 금속 배선과 상부 금속 배선간 인터커넥션 형성 디자인 룰 하에서의 콘텍 플러그와 하부 배선 혹은 콘텍 플러그와 상부 배선의 금속 배선 형성방법은 나노기술(Nano-technology) 실현에 있어 많은 제약을 일으키게 되는 문제점이 있었다.However, as described above, the method of forming the contact plug and the lower wiring or the contact wiring and the upper wiring through the interconnection forming design rule between the lower metal wiring and the upper metal wiring has many restrictions in realizing nano-technology. There was a problem.

따라서, 본 발명의 목적은 반도체 소자 제조시 하부 금속 배선과 상부 금속 배선간 인터커넥션의 불정렬을 최소화시키는 금속간 인터커넥션 형성 방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method for forming an intermetallic interconnect, which minimizes the misalignment of the interconnection between the lower metal wiring and the upper metal wiring in manufacturing a semiconductor device.

상술한 목적을 달성하기 위한 본 발명은 반도체 소자 제조시 금속간 인터커넥션 형성 방법에 있어서, (a)반도체 소자 기판에 하부 금속 배선을 형성하는 단계와; (b)상기 하부 금속 배선위에 평탄화 절연막을 적층시킨 후 평탄화 시키는 단계와; (c)상기 평탄화 절연막을 패터닝한 후 상부 배선 두께만큼 소정의 깊이까지 건식 식각시키는 단계와; (d)상기 식각된 위치에 상부 금속 배선을 형성시키는 단계와; (e)상기 하부 금속 배선과 상부 금속 배선을 인터커넥션 시키는 인터커넥션용 콘텍 플러그가 형성될 위치의 상기 평탄화 절연막을 상기 하부 금속 배선이 노출될 때까지 건식식각시키는 단계와; (f)상기 식각된 위치에 인터커넥션용 콘텍 물질을 충진(Gap fill)하여 상기 하부 금속 배선과 상부 금속 배선을 인터커넥션시키는 단계;를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method for forming an intermetallic interconnection in manufacturing a semiconductor device, the method comprising: (a) forming a lower metal wiring on a semiconductor device substrate; (b) stacking and planarizing a planarization insulating film on the lower metal wiring; (c) dry etching the patterned planarization insulating film to a predetermined depth by an upper wiring thickness; (d) forming an upper metal wiring at the etched position; (e) dry etching the planarization insulating layer at a position where an interconnect contact plug for interconnecting the lower metal wiring and the upper metal wiring is to be formed until the lower metal wiring is exposed; and (f) gap filling the contact material for interconnection at the etched position to interconnect the lower metal wiring and the upper metal wiring.

도 1a 내지 도 1c는 본 발명의 실시 예에 따른 반도체 소자 제조시 금속간 인터커넥션 형성 방법을 도시한 공정 수순도.1A to 1C are process flowcharts illustrating a method for forming an intermetallic interconnection in manufacturing a semiconductor device according to an embodiment of the present invention.

이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 실시 예의 동작을 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the operation of the preferred embodiment according to the present invention.

도 1a 내지 도 1c는 본 발명의 실시 예에 따른 금속 인터커넥션 형성 방법을도시한 공정 수순도이다. 이하 상기 도 1a 내지 도 1c를 참조하여 본 발명의 금속 인터커넥션 형성 방법을 상세히 설명한다.1A through 1C are process flowcharts illustrating a metal interconnection formation method according to an exemplary embodiment of the present invention. Hereinafter, a method of forming a metal interconnection of the present invention will be described in detail with reference to FIGS. 1A to 1C.

먼저 도 1a에서와 같이 하부 금속 배선(1)을 형성하고 평탄화 절연막(2)을 두껍게 적층시킨다. 이어 CMP(Chemical Mechanical Polishing)를 수행하여 평탄화를 수행하고, 상부 금속 배선용 감광막(Photoresist)을 패터닝(Patterning)시킨 후, 노출된 평탄화 절연막을 상부 배선 두께만큼 소정의 깊이까지 건식 식각으로 제거시킨다.First, as shown in FIG. 1A, the lower metal wiring 1 is formed and the planarization insulating film 2 is thickly stacked. Subsequently, planarization is performed by performing chemical mechanical polishing (CMP), and after patterning the photoresist for the upper metal wiring, the exposed planarization insulating layer is removed by dry etching to a predetermined depth by the thickness of the upper wiring.

이어 도 1b에서와 같이 종래 일반적인 방식과는 달리 하부 금속배선(1)과 상부 금속 배선(4)을 먼저 형성하고 그 이후에 인터커넥션을 하기 위하여 인터커넥션용 감광막 패터닝(5)을 수행한 후, 하부 금속 배선이 노출될 때까지 건식식각시킨다.Subsequently, unlike the conventional method, as shown in FIG. 1B, the lower metal wiring 1 and the upper metal wiring 4 are first formed, and then the photoresist patterning 5 for interconnection is performed thereafter for interconnection. Dry etch until the bottom metal wiring is exposed.

그런 후, 도 1c에서와 같이 인터커넥션용 감광막 패턴(5)을 제거시킨다. 그리고 그 상부에 CVD(Chemical Vapor Deposition) 타이타늄(TiN) 또는 탄탈륨(TaN)을 콘텍 홀내에 매립하고 에치백(Etch-back) 혹은 CMP하여 인터커넥션용 플러그(Plug)(6)를 완성하여 하부 금속 배선(1)과 상부 금속 배선(2)을 인터커넥션시키게 된다.Thereafter, as shown in FIG. 1C, the interconnection photoresist pattern 5 is removed. In addition, the CVD (Chemical Vapor Deposition) titanium (TiN) or tantalum (TaN) is embedded in the contact hole, and etch-back or CMP is used to complete the interconnection plug (6). The wiring 1 and the upper metal wiring 2 are interconnected.

즉, 상술한 바와 같이 본 발명은 하부 금속 배선과 상부 금속 배선을 먼저 형성하고 인터커넥션을 그 이후에 형성하여 인터커넥션과 하부 오버랩이 "0"이하여도 가능하며, 인터커넥션용 콘텍 플러그와 상부 금속 배선과 오버랩이 불정렬 마진만큼만 되어도 된다.That is, as described above, the present invention may form the lower metal wiring and the upper metal wiring first, and then form the interconnection thereafter, so that the interconnection and the lower overlap may be less than or equal to "0", and the interconnect plug and the upper metal may be used. Wiring and overlap may be as long as misalignment margin.

한편 상술한 본 발명의 설명에서는 구체적인 실시 예에 관해 설명하였으나, 여러 가지 변형이 본 발명의 범위에서 벗어나지 않고 실시될 수 있다. 따라서 발명의 범위는 설명된 실시 예에 의하여 정할 것이 아니고 특허청구범위에 의해 정하여져야 한다.Meanwhile, in the above description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the invention should be determined by the claims rather than by the described embodiments.

이상에서 설명한 바와 같이, 본 발명은 반도체 소자 제조공정 중 금속 인터커넥션 형성방법에 있어서, 하부 금속 배선과 상부 금속 배선을 먼저 형성하고 인터커넥션을 그 이후에 형성함으로써, 인터커넥션과 하부 오버랩이 "0"이하여도 가능하며, 인터커넥션용 콘텍 플러그와 상부 금속 배선과 오버랩이 불정렬 마진만큼만 되어도 되는 이점이 있다.As described above, in the method of forming a metal interconnect during the semiconductor device manufacturing process, the interconnection and the bottom overlap are formed by forming the lower metal wiring and the upper metal wiring first and then forming the interconnect thereafter. "It is possible, and there is an advantage that the overlap of the contact plug for the interconnect and the top metal wiring can only be as much as the misalignment margin.

Claims (4)

반도체 소자 제조시 금속간 인터커넥션 형성 방법에 있어서,In the method of forming an intermetallic interconnect in manufacturing a semiconductor device, (a)반도체 소자 기판에 하부 금속 배선을 형성하는 단계와;(a) forming a lower metal wiring on the semiconductor element substrate; (b)상기 하부 금속 배선위에 평탄화 절연막을 적층시킨 후 평탄화 시키는 단계와;(b) stacking and planarizing a planarization insulating film on the lower metal wiring; (c)상기 평탄화 절연막을 패터닝한 후 상부 배선 두께만큼 소정의 깊이까지 건식 식각시키는 단계와;(c) dry etching the patterned planarization insulating film to a predetermined depth by an upper wiring thickness; (d)상기 식각된 위치에 상부 금속 배선을 형성시키는 단계와;(d) forming an upper metal wiring at the etched position; (e)상기 하부 금속 배선과 상부 금속 배선을 인터커넥션 시키는 인터커넥션용 콘텍 플러그가 형성될 위치의 상기 평탄화 절연막을 상기 하부 금속 배선이 노출될 때까지 건식식각시키는 단계와;(e) dry etching the planarization insulating layer at a position where an interconnect contact plug for interconnecting the lower metal wiring and the upper metal wiring is to be formed until the lower metal wiring is exposed; (f)상기 식각된 위치에 인터커넥션용 콘텍 물질을 충진(Gap fill)하여 상기 하부 금속 배선과 상부 금속 배선을 인터커넥션시키는 단계;를 포함하는 것을 특징으로 하는 금속간 인터커넥션 형성 방법.and (f) gap filling the contact material for interconnection at the etched position to interconnect the lower metal interconnection and the upper metal interconnection. 제1항에 있어서,The method of claim 1, 상기 (f)단계는, (f1)상기 인터커넥션용 식각홀내 인터커넥션용 물질을 매립시키는 단계와;Step (f) may include: (f1) embedding the interconnection material in the interconnection etching hole; (f2)상기 매립된 인터커넥션용 물질을 에치백 또는 CMP수행하여 상기 하부금속 배선과 상부 금속 배선간 인터커넥션용 플러그를 형성시키는 단계;를 포함하는 것을 특징으로 하는 금속간 인터커넥션 형성방법.and forming a plug for interconnection between the lower metal wiring and the upper metal wiring by etching back or CMPing the buried interconnect material. 제2항에 있어서,The method of claim 2, 상기 인터커넥션용 물질은, CVD TiN 또는 TaN 중 어느 하나의 금속 물질이 사용되는 것을 특징으로 하는 금속간 인터커넥션 형성방법.The interconnection material is a metal-to-metal interconnect formation method, characterized in that any one of CVD TiN or TaN metal material is used. 제3항에 있어서,The method of claim 3, 상기 인터커넥션용 물질은, 블랭킷 텅스텐이나 구리를 합성하여 사용하는 것을 특징으로 하는 금속간 인터커넥션 형성 방법.The interconnection material is a method for forming intermetallic interconnect, characterized in that the synthesis of the blanket tungsten or copper.
KR1020020086644A 2002-12-30 2002-12-30 Method for forming interconnection between metal lines in semiconductor device fabrication process KR100620159B1 (en)

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