KR20040057964A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- KR20040057964A KR20040057964A KR1020030095121A KR20030095121A KR20040057964A KR 20040057964 A KR20040057964 A KR 20040057964A KR 1020030095121 A KR1020030095121 A KR 1020030095121A KR 20030095121 A KR20030095121 A KR 20030095121A KR 20040057964 A KR20040057964 A KR 20040057964A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 집적 회로에 있어서의 Cu 배선에 관한 것으로, 특히 빈 구멍을 갖는 저유전율막(다공성 Low - k막)을 층간 절연막으로서 이용한 반도체 집적회로에 있어서의 Cu 배선의 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to Cu wiring in a semiconductor integrated circuit, and more particularly, to a method of forming Cu wiring in a semiconductor integrated circuit using a low dielectric constant film (porous Low-k film) having an empty hole as an interlayer insulating film.
반도체 집적 회로의 미세화에 수반하여, 메탈 배선 사이의 피치가 축소되어 메탈 배선의 신호 지연이 심각한 문제가 되고 있다.With the miniaturization of semiconductor integrated circuits, the pitch between the metal wirings is reduced, and the signal delay of the metal wirings becomes a serious problem.
이 문제를 해결하기 위해, 배선 재료에 Cu를 이용하여 배선 저항을 저감하고, 층간 절연막에 저유전율막을 이용하여 정전 용량을 저감하는 것이 필요 불가결하게 되어 있다.In order to solve this problem, it is necessary to reduce the wiring resistance by using Cu as the wiring material and to reduce the capacitance by using the low dielectric constant film as the interlayer insulating film.
특히, 차세대의 반도체 집적 회로에서는 보다 한층 층간 용량 저감을 위해, 절연막 중에 복수의 빈 구멍을 갖는 소위 다공성 저유전율막(이하 「다공성 Low - k막」이라 함)의 사용이 검토되어 있다(예를 들어, 특허 문헌 1 참조).In particular, in the next generation of semiconductor integrated circuits, the use of a so-called porous low dielectric constant film (hereinafter referred to as a "porous Low-k film") having a plurality of void holes in the insulating film has been considered to further reduce interlayer capacitance (example See, for example, Patent Document 1).
[특허 문헌 1][Patent Document 1]
일본 특허 공개 평9-298241호 공보(제2, 제3 페이지, 도10, 도11)Japanese Patent Laid-Open No. 9-298241 (2nd, 3rd page, Fig. 10, Fig. 11)
그러나, 다공성 Low - k막은 빈 구멍을 갖고 있으므로, 다공성 Low - k막에 형성된 배선 홈의 측면에 요철이 형성되어 버린다. 이 상태에서, 배리어 메탈막 및 시드층을 형성해도 이들을 커버리지 좋게 형성할 수 없다고 하는 문제가 있었다.However, since the porous Low-k film has an empty hole, irregularities are formed on the side surface of the wiring groove formed in the porous Low-k film. In this state, even when the barrier metal film and the seed layer were formed, there was a problem that they could not be formed in a good coverage.
또한, 배리어 메탈막 및 시드층이 배선 홈의 측면으로부터 박리되어 버린다고 하는 문제가 있었다. 즉, 배선 홈의 측면과 배리어 메탈막 및 시드층과의 밀착성이 낮다고 하는 문제가 있었다.Moreover, there existed a problem that a barrier metal film and a seed layer peeled off from the side surface of a wiring groove. That is, there exists a problem that the adhesiveness of the side surface of a wiring groove, a barrier metal film, and a seed layer is low.
본 발명은 상기 종래의 과제를 해결하기 위해 이루어진 것으로, 다공성 저유전율막에 형성된 배선 홈 내에 커버리지 좋게 또한 높은 밀착성으로 도전체막을 형성하는 것을 목적으로 한다.This invention is made | formed in order to solve the said conventional subject, and an object of this invention is to form a conductor film | membrane with good coverage and high adhesiveness in the wiring groove formed in the porous low dielectric constant film.
도1은 본 발명의 제1 실시 형태에 의한 반도체 장치의 제조 방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1 : 기판(실리콘 기판)1: substrate (silicon substrate)
2 : 다공성 저유전율막(다공성 MSQ)2: porous low dielectric constant membrane (porous MSQ)
3 : 하드 마스크(SiC 마스크)3: hard mask (SiC mask)
4, 6 : 플라즈마4, 6: plasma
5 : 배선 홈5: wiring groove
7 : 퇴적막(CxFy막)7: deposition film (CxFy film)
8 : 플라즈마(Ar 플라즈마)8 plasma (Ar plasma)
21 : 빈 구멍21: empty hole
본 발명에 관한 반도체 장치의 제조 방법은, 기판 상에 다공성 저유전율막을 형성하는 공정과,The manufacturing method of the semiconductor device which concerns on this invention is a process of forming a porous low dielectric constant film on a board | substrate,
플라즈마 에칭에 의해 상기 저유전율막 내에 배선 홈을 형성하는 공정과,Forming a wiring groove in the low dielectric constant film by plasma etching;
플라즈마 에칭 장치에 있어서 퇴적성을 갖는 가스의 플라즈마를 이용하여 상기 배선 홈의 측면을 포함하는 상기 기판의 전체면에 퇴적막을 형성하는 공정과,Forming a deposition film on the entire surface of the substrate including the side surface of the wiring groove by using a plasma of a gas having deposition property in the plasma etching apparatus;
스퍼터 에칭에 의해 상기 배선 홈의 측면 이외에 형성된 불필요한 상기 퇴적막을 제거하는 공정과,Removing the unnecessary deposited film formed on the side surface of the wiring groove by sputter etching;
상기 배선 홈 내에 도전체막을 형성하는 공정을 포함하는 것을 특징으로 하는 것이다.And forming a conductor film in the wiring groove.
본 발명에 관한 반도체 장치의 제조 방법에 있어서, 상기 배선 홈을 형성하는 공정과 상기 퇴적막을 형성하는 공정을 동시에 행할 수 있다.In the manufacturing method of the semiconductor device which concerns on this invention, the process of forming the said wiring groove and the process of forming the said deposited film can be performed simultaneously.
본 발명에 관한 반도체 장치의 제조 방법에 있어서, 상기 배선 홈을 형성하는 공정, 상기 퇴적막을 형성하는 공정 및 상기 퇴적막을 제거하는 공정을 동일한 처리실 내에서 행할 수 있다.In the method of manufacturing a semiconductor device according to the present invention, the step of forming the wiring groove, the step of forming the deposited film, and the step of removing the deposited film can be performed in the same process chamber.
본 발명에 관한 반도체 장치의 제조 방법에 있어서, 상기 저유전율막은 다공성 MSQ, 다공성 HSQ, 메틸기와 수소기의 양 쪽을 함유하는 하이브리드막 및 카본을 주성분으로 하는 다공성 유기막 중 어느 하나이다.In the method of manufacturing a semiconductor device according to the present invention, the low dielectric constant film is any one of a porous MSQ, a porous HSQ, a hybrid film containing both methyl and hydrogen groups, and a porous organic film containing carbon as a main component.
이하, 도면을 참조하여 본 발명의 실시 형태에 대해 설명한다. 도면 중, 동일 또는 상당하는 부분에는 동일 부호를 붙여 그 설명을 간략화하거나 생략하는 경우가 있다.EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described with reference to drawings. In the drawings, the same or corresponding parts may be denoted by the same reference numerals to simplify or omit the description thereof.
<제1 실시 형태><First Embodiment>
도1을 참조하여 본 발명의 제1 실시 형태에 의한 반도체 장치의 제조 방법에 대해 설명한다.With reference to FIG. 1, the manufacturing method of the semiconductor device by 1st Embodiment of this invention is demonstrated.
도1은 본 발명의 제1 실시 형태에 의한 반도체 장치의 제조 방법을 설명하기 위한 도면이다. 상세하게는, 도1의 (a)는 다공성 MSQ 상에 SiC 마스크를 형성한 후의 상태를 도시하는 도면이고, 도1의 (b)는 다공성 MSQ 내에 배선 홈을 형성한 후의 상태를 도시하는 도면이고, 도1의 (c)는 기판 전체면에 퇴적막을 형성한 상태를 도시하는 도면이고, 도1의 (d)는 불필요한 퇴적막을 스퍼터 에칭한 후의 상태를 도시하는 도면이다.1 is a diagram for explaining a method for manufacturing a semiconductor device according to the first embodiment of the present invention. In detail, FIG. 1A is a view showing a state after forming a SiC mask on a porous MSQ, and FIG. 1B is a view showing a state after forming a wiring groove in the porous MSQ. 1C is a view showing a state in which a deposited film is formed on the entire surface of the substrate, and FIG. 1D is a view showing a state after sputter etching an unnecessary deposition film.
우선, 도1의 (a)에 도시한 바와 같이 실리콘 기판 등의 기판(1) 상에, 복수의 빈 구멍(21)을 갖는 다공성 저유전율막(이하 「다공성 Low - k막」이라 함)(2)으로서 다공성 MSQ를 형성한다. 다공성 MSQ(2)의 빈 구멍(21)의 크기는, 수Å 내지 수백Å 정도이다. 다음에, 다공성 MSQ(2) 상에 하드 마스크(3)로서 SiC 마스크를 형성한다.First, as shown in Fig. 1A, a porous low dielectric constant film (hereinafter referred to as a "porous Low-k film") having a plurality of hollow holes 21 on a substrate 1 such as a silicon substrate ( 2) form porous MSQ. The size of the hollow hole 21 of the porous MSQ 2 is about several hundreds to several hundreds of micrometers. Next, a SiC mask is formed as a hard mask 3 on the porous MSQ 2.
다음에, 도1의 (b)에 도시한 바와 같이 SiC 마스크(3)를 마스크로서 다공성 MSQ(2)를 플라즈마 에칭한다. 여기서, 플라즈마 에칭 장치로서 처리실(챔버) 내에 기판을 적재하는 하부 전극과 그에 대향하는 상부 전극을 구비한 2주파 여기 평행평판형 RIE(reactive ion etching) 장치를 이용하였다(도시 생략).Next, as shown in Fig. 1B, the porous MSQ 2 is plasma etched using the SiC mask 3 as a mask. Here, a two-frequency excitation parallel plate type reactive ion etching (RIE) apparatus having a lower electrode for mounting a substrate in a processing chamber (chamber) and an upper electrode opposite thereto was used as a plasma etching apparatus (not shown).
다공성 MSQ(2)의 플라즈마 에칭에 대해 상세하게 서술하면, 우선 상부 전극에 대향하는 하부 전극 상에 실리콘 기판(1)을 배치한다. 실리콘 기판(1)의 온도는, 열교환기 등을 이용하여 약 25 ℃로 유지해 둔다. 다음에, 챔버 내에 프로세스 가스로서 C4F8/N2/Ar을 각각 10/225/1400 sccm의 유량으로 도입하고, 배기 기구를 이용하여 챔버 내의 압력을 150 mTorr로 유지한다. 그리고, 상부 전극에 주파수 60 ㎒, 출력 1000 W의 RF 전력(고주파 전력)을 인가하고, 하부 전극에 주파수 13.56 ㎒, 출력 1400 W의 RF 전력을 인가하면 챔버 내에 플라즈마(4)가 발생한다. 이 플라즈마(4)로 다공성 MSQ(2)를 이방성 에칭함으로써, 다공성 MSQ(2) 내에 배선 홈(5)이 형성된다. 에칭 종료 후는, 배선 홈(5)의 측면이 다공성 MSQ(2)의 빈 구멍(21)에 의해 요철 형상이 된다.The plasma etching of the porous MSQ 2 will be described in detail. First, the silicon substrate 1 is disposed on the lower electrode opposite to the upper electrode. The temperature of the silicon substrate 1 is kept at about 25 degreeC using a heat exchanger etc. Next, C 4 F 8 / N 2 / Ar is introduced into the chamber at a flow rate of 10/225/1400 sccm, respectively, and the pressure in the chamber is maintained at 150 mTorr using an exhaust mechanism. When the RF power (high frequency power) with a frequency of 60 MHz and an output of 1000 W is applied to the upper electrode, and the RF power with a frequency of 13.56 MHz and an output of 1400 W is applied to the lower electrode, plasma 4 is generated in the chamber. By anisotropically etching the porous MSQ 2 with the plasma 4, the wiring groove 5 is formed in the porous MSQ 2. After the end of etching, the side surface of the wiring groove 5 is formed into an uneven shape by the hollow hole 21 of the porous MSQ 2.
또, 본 발명에 있어서 배선 홈은 도전체막을 매립하기 위한 홈 또는 구멍을 의미한다.In addition, in this invention, a wiring groove | channel means a groove | channel or a hole for embedding a conductor film.
다음에, 도1의 (c)에 도시한 바와 같이 동일 챔버 내에서 하부 전극으로의 RF 전력 인가만을 중지하고, 그 밖의 조건은 바꾸지 않고 플라즈마(6)를 계속하여 생성한다. 이 결과, C4F8로부터 해리한 CxFy(x ＝ 1 내지 4, y ＝ 1 내지 8) 분자가 배선 홈(5)의 측면을 포함하는 실리콘 기판(1) 전체면에 퇴적된다. 즉, 배선 홈(5)의 측면을 포함하는 실리콘 기판(1) 전체면에 퇴적막(7)으로서 CxFy막을 형성한다. 이에 의해, 배선 홈(5)의 측면에 노출되는 빈 구멍(21)이 막혀 상기 요철형상이 완화된다.Next, as shown in Fig. 1C, only the application of RF power to the lower electrode in the same chamber is stopped, and the plasma 6 is continuously generated without changing other conditions. As a result, the deposition on the entire surface C 4 F 8 haeri from a CxFy (x = 1 to 4, y = 1 to 8), the silicon substrate 1, which molecule comprises a side surface of the wiring groove 5. That is, a CxFy film is formed as the deposition film 7 on the entire surface of the silicon substrate 1 including the side surface of the wiring groove 5. As a result, the hollow hole 21 exposed to the side surface of the wiring groove 5 is blocked, thereby alleviating the irregularities.
또, 상기 퇴적막(7)의 조성, 막 두께 및 커버리지는 상부 전극에 인가하는 RF 전력, 혼합 가스 C4F8/N2/Ar의 유량비, 프로세스 압력, 기판 온도 등의 변수를 적절하게 조정함으로써 최적화가 가능하다.In addition, the composition, film thickness, and coverage of the deposited film 7 appropriately adjust parameters such as RF power applied to the upper electrode, flow rate ratio of the mixed gas C 4 F 8 / N 2 / Ar, process pressure, substrate temperature, and the like. This can be optimized.
다음에, 도1의 (d)에 도시한 바와 같이 동일 챔버 내에서 하부 전극에 RF 전력을 다시 인가하여 C4F8및 N2가스의 도입을 중지하고, 그 밖의 조건은 바꾸지 않고 Ar 플라즈마(8)를 계속하여 생성한다. 이 Ar 플라즈마(8)에 의한 스퍼터 에칭에 의해, 배선 홈(5)의 측면 이외에 형성된 불필요한 퇴적막(7)을 제거한다.Next, as shown in Fig. 1D, RF power is again applied to the lower electrode in the same chamber to stop the introduction of the C 4 F 8 and N 2 gases, and the Ar plasma ( Continue to 8). By the sputter etching by this Ar plasma 8, the unnecessary deposition film 7 formed other than the side surface of the wiring groove 5 is removed.
이상과 같이 하여, 다공성 MSQ(2) 내에 형성된 배선 홈(5)의 측면에만 퇴적막(7)이 형성된다.As described above, the deposition film 7 is formed only on the side surface of the wiring groove 5 formed in the porous MSQ 2.
그 후, 도시하지 않지만 배선 홈(5) 내에 도전체막을 형성한다. 상세하게는, 배리어 메탈막 및 시드층을 차례로 형성한 후, Cu 등의 금속을 퇴적시키고 불필요한 금속을 CMP에 의해 제거하여 평탄화한다.Thereafter, although not shown, a conductor film is formed in the wiring groove 5. Specifically, after the barrier metal film and the seed layer are sequentially formed, metals such as Cu are deposited and unnecessary metals are removed by CMP to planarize.
이상 설명한 바와 같이, 본 제1 실시 형태에서는 다공성 MSQ(2) 내에 배선 홈(5)을 형성한 후 이 배선 홈(5)의 측면에 퇴적막(7)을 형성하고, 그 후 배선 홈(5) 내에 도전체막을 형성하였다. 본 제1 실시 형태에 따르면, 도전체막을 형성할 때, 배선 홈(5) 측면의 빈 구멍(21)은 퇴적막(7)에 의해 덮여 있고 요철 형상은 완화되어 있다. 따라서, 배선 홈(5) 내에 커버리지 좋게 또한 높은 밀착성으로 도전체막을 형성할 수 있다.As described above, in the first embodiment, after the wiring groove 5 is formed in the porous MSQ 2, the deposition film 7 is formed on the side surface of the wiring groove 5, and then the wiring groove 5 is formed. ), A conductor film was formed. According to the first embodiment, when the conductor film is formed, the empty hole 21 on the side of the wiring groove 5 is covered by the deposition film 7 and the uneven shape is relaxed. Therefore, the conductor film can be formed in the wiring groove 5 with good coverage and high adhesion.
또, 본 제1 실시 형태에서는 퇴적막(7)을 플라즈마 에칭 장치로 형성하고 있다. 즉, 배선 홈(5)의 형성과, 퇴적막(7)의 형성과, 불필요한 퇴적막(7)의 스퍼터 제거를 에칭 장치의 동일 챔버 내에서 연속하여(현장에서) 행하고 있다. 따라서, 반도체 제조 장치 사이에서 반도체 장치를 반송하는 시간을 대폭 단축할 수 있다.In the first embodiment, the deposition film 7 is formed by a plasma etching apparatus. That is, the formation of the wiring groove 5, the formation of the deposition film 7, and the unnecessary sputter removal of the deposition film 7 are continuously performed (at the site) in the same chamber of the etching apparatus. Therefore, the time which conveys a semiconductor device between semiconductor manufacturing apparatuses can be shortened significantly.
또, 본 제1 실시 형태에서는 다공성 Low - k막으로서 메틸기를 함유하는 다공성 MSQ(2)를 이용하였지만, 수소기를 함유하는 다공성 HSQ(다공성 실리카), 메틸기와 수소기의 양 쪽을 함유하는 하이브리드막 및 카본을 주성분으로 하는 다공성 유기막을 이용해도 좋다. 이 경우도, 상술한 본 제1 실시 형태에서 얻어지는 효과와 동일한 효과를 얻을 수 있다.In the first embodiment, a porous MSQ (2) containing a methyl group was used as the porous Low-k membrane, but a hybrid membrane containing both a porous HSQ (porous silica) containing a hydrogen group and a methyl group and a hydrogen group was used. And a porous organic membrane containing carbon as a main component. Also in this case, the same effects as those obtained in the first embodiment described above can be obtained.
또한, 본 제1 실시 형태에서는 플라즈마 에칭 장치로서 2주파 여기 평행 평판형 RIE 장치를 이용하였지만, 마그네트론형 RIE 장치, 유도 결합 플라즈마 에칭 장치, ECR 에칭 장치 등을 이용해도 좋다.In the first embodiment, a two-frequency excitation parallel plate type RIE apparatus is used as the plasma etching apparatus, but a magnetron type RIE apparatus, an inductively coupled plasma etching apparatus, an ECR etching apparatus, or the like may be used.
<제2 실시 형태><2nd embodiment>
전술한 제1 실시 형태에서는, 다공성 MSQ(2) 내에 배선 홈(5)을 형성하는 공정과, 배선 홈(5)의 측면을 포함하는 실리콘 기판(1) 전체면에 퇴적막(7)을 형성하는 공정을 따로따로 행하였다. 본 제2 실시 형태에서는 이 2개의 공정을 동시에 행하는 것을 특징으로 한다. 또, 그 이외의 공정에 대해서는 제1 실시 형태와 동일하므로 간단하게 설명한다.In the first embodiment described above, the deposition film 7 is formed on the entire surface of the silicon substrate 1 including the step of forming the wiring groove 5 in the porous MSQ 2 and the side surfaces of the wiring groove 5. The process to perform was performed separately. In the second embodiment, these two steps are performed simultaneously. In addition, since it is the same as that of 1st Embodiment about a process other than that, it demonstrates easily.
우선, 제1 실시 형태와 동일한 방법[도1의 (a) 참조]으로 실리콘 기판(1) 상에 다공성 MSQ(2)를 형성하고 그 위에 SiC 마스크(3)를 형성한다.First, the porous MSQ 2 is formed on the silicon substrate 1 and the SiC mask 3 is formed thereon in the same manner as in the first embodiment (see Fig. 1A).
다음에, 도1의 (b)에 도시한 공정에 있어서 하기 (a) 내지 (e)에 기재한 개량 중 1개를 행하거나, 복수를 조합하여 행한다.Next, in the process shown in Fig. 1B, one of the improvements described in the following (a) to (e) is performed, or a plurality thereof is combined.
(a) 실리콘 기판(1)의 온도를 마이너스 1O ℃ 이하로 낮춘다.(a) The temperature of the silicon substrate 1 is lowered to minus 10 degrees C or less.
(b) C4F8유량을 수 sccm 증대시킨다.(b) Increase the C 4 F 8 flow rate by several sccm.
(c) 챔버 내의 압력을 수십 mTorr 증대시킨다.(c) Increase the pressure in the chamber by several tens of mTorr.
(d) 하부 전극에 인가하는 RF 전력을 수백 W 저하시킨다.(d) The RF power applied to the lower electrode is reduced by several hundred W.
(e) N2가스의 유량을 수십 sccm 저하시킨다.(e) The flow rate of N 2 gas is reduced by several tens of sccm.
이상과 같은 방법에 의해, 다공성 MSQ(2) 내에 배선 홈(5)이 형성되는 동시에, 도1의 (c)에 도시한 바와 같이 배선 홈(5)의 측면을 포함하는 실리콘 기판(1) 전체면에 퇴적막(7)이 형성된다.By the above method, the wiring groove 5 is formed in the porous MSQ 2 and the entire silicon substrate 1 including the side surface of the wiring groove 5 as shown in Fig. 1C. The deposition film 7 is formed on the surface.
다음에, 제1 실시 형태와 같은 방법[도1의 (d) 참조]으로 배선 홈(5)의 측면 이외에 형성된 불필요한 퇴적막(7)을 제거한다. 이에 의해, 다공성 MSQ(2) 내에 형성된 배선 홈(5)의 측면에만 퇴적막(7)이 형성된다.Next, in the same manner as in the first embodiment (see Fig. 1 (d)), the unnecessary deposition film 7 formed in addition to the side surface of the wiring groove 5 is removed. As a result, the deposition film 7 is formed only on the side surface of the wiring groove 5 formed in the porous MSQ 2.
그 후, 배선 홈(5) 내에 도전체막을 형성한다. 상세하게는, 배리어 메탈 및 시드층을 차례로 형성한 후, Cu 등의 금속을 퇴적시키고 불필요한 금속을 CMP에 의해 제거하여 평탄화한다.Thereafter, a conductor film is formed in the wiring groove 5. Specifically, after the barrier metal and the seed layer are sequentially formed, metals such as Cu are deposited and unnecessary metals are removed by CMP and planarized.
이상 설명한 바와 같이, 본 제2 실시 형태에서는 전술한 제1 실시 형태에 있어서 도1의 (b)에 도시한 배선 홈(5)의 형성 공정과, 도1의 (c)에 도시한 퇴적막(7)의 형성 공정을 동시에 행하는 것으로 하였다. 따라서, 본 제2 실시 형태에 따르면, 제1 실시 형태에서 얻어진 효과에다가 처리 공정수를 줄일 수 있어 일괄 처리량을 향상시킬 수 있다고 하는 효과를 얻을 수 있다.As described above, in the second embodiment, in the first embodiment described above, the process of forming the wiring groove 5 shown in FIG. 1B and the deposition film shown in FIG. The formation process of 7) was performed simultaneously. Therefore, according to the second embodiment, in addition to the effects obtained in the first embodiment, the number of processing steps can be reduced, and the effect of improving the collective throughput can be obtained.
본 발명에 따르면, 다공성 저유전율막에 형성된 배선 홈 내에 커버리지 좋게 또한 높은 밀착성으로 도전체막을 형성할 수 있다.According to the present invention, the conductor film can be formed in the wiring groove formed in the porous low dielectric constant film with good coverage and high adhesion.
Claims (4)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100768474B1 (en) * | 2005-09-27 | 2007-10-18 | 김홍배 | Controller for Detecting Bubbles Generated within Electric Cooker |
| KR100847843B1 (en) * | 2007-07-24 | 2008-07-23 | 주식회사 동부하이텍 | Method for fabricating semiconductor device having porous low-k material |
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| US8018023B2 (en) * | 2008-01-14 | 2011-09-13 | Kabushiki Kaisha Toshiba | Trench sidewall protection by a carbon-rich layer in a semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100768474B1 (en) * | 2005-09-27 | 2007-10-18 | 김홍배 | Controller for Detecting Bubbles Generated within Electric Cooker |
| KR100847843B1 (en) * | 2007-07-24 | 2008-07-23 | 주식회사 동부하이텍 | Method for fabricating semiconductor device having porous low-k material |
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