JP2004207358A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
JP2004207358A
JP2004207358A JP2002372343A JP2002372343A JP2004207358A JP 2004207358 A JP2004207358 A JP 2004207358A JP 2002372343 A JP2002372343 A JP 2002372343A JP 2002372343 A JP2002372343 A JP 2002372343A JP 2004207358 A JP2004207358 A JP 2004207358A
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Prior art keywords
film
wiring groove
forming
porous
semiconductor device
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JP3717073B2 (en
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Takashi Yunogami
隆 湯之上
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Semiconductor Leading Edge Technologies Inc
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Semiconductor Leading Edge Technologies Inc
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Priority to JP2002372343A priority Critical patent/JP3717073B2/en
Priority to KR1020030095121A priority patent/KR20040057964A/en
Publication of JP2004207358A publication Critical patent/JP2004207358A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To form a conductor film with good coverage and contact inside the wiring groove formed on a porous low dielectric material film. <P>SOLUTION: A porous MSQ(2) is formed on a silicon substrate 1 and an SiC mask 3 is then formed thereon. A wiring groove 5 is formed within the porous MSQ(2) with the plasma etching with an SiC mask 3 used as a mask, and a deposited film 7 is formed on the entire surface of the silicon substrate 1 including the side surface of the wiring groove 5 using the plasma of deposition gas. Thereafter, unwanted deposition film 7 formed to the area other than the side surface of the wiring groove 5 is removed with the sputter etching and a conductor film is formed inside the wiring groove 5. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明が属する技術分野】
本発明は、半導体集積回路におけるＣｕ配線に係り、特に空孔を有する低誘電率膜（ポーラスＬｏｗ−ｋ膜）を層間絶縁膜として用いた半導体集積回路におけるＣｕ配線の形成方法に関する。
【０００２】
【従来の技術】
半導体集積回路の微細化に伴い、メタル配線間のピッチが縮小し、メタル配線の信号遅延が深刻な問題となっている。
この問題を解決するため、配線材料にＣｕを用いて配線抵抗を低減し、層間絶縁膜に低誘電率膜を用いて静電容量を低減することが必要不可欠になっている。特に、次世代の半導体集積回路では、より一層の層間容量低減のため、絶縁膜中に複数の空孔を有する、いわゆる多孔性の低誘電率膜（以下「ポーラスＬｏｗ−ｋ膜」という。）の使用が検討されている（例えば、特許文献１参照）。
【０００３】
【特許文献１】
特開平９−２９８２４１号公報 （第２−３頁、第１０−１１図）
【０００４】
【発明が解決しようとする課題】
しかしながら、ポーラスＬｏｗ−ｋ膜は空孔を有しているため、ポーラスＬｏｗ−ｋ膜に形成された配線溝の側面に凹凸が形成されてしまう。この状態で、バリアメタル膜及びシード層を形成しても、それらをカバレージ良く形成できないという問題があった。
また、バリアメタル膜及びシード層が配線溝の側面から剥れてしまうという問題があった。すなわち、配線溝の側面と、バリアメタル膜及びシード層との密着性が低いという問題があった。
【０００５】
本発明は、上記従来の課題を解決するためになされたもので、多孔性の低誘電率膜に形成された配線溝内に、カバレージ良く且つ高い密着性で導電体膜を形成することを目的とする。
【０００６】
【課題を解決する為の手段】
この発明に係る半導体装置の製造方法は、基板上に多孔性の低誘電率膜を形成する工程と、
プラズマエッチングにより、前記低誘電率膜内に配線溝を形成する工程と、
プラズマエッチング装置において、堆積性を有するガスのプラズマを用いて、前記配線溝の側面を含む前記基板の全面に堆積膜を形成する工程と、
スパッタエッチングにより、前記配線溝の側面以外に形成された不要な前記堆積膜を除去する工程と、
前記配線溝内に導電体膜を形成する工程と、
を含むことを特徴とするものである。
【０００７】
この発明に係る半導体装置の製造方法において、前記配線溝を形成する工程と、前記堆積膜を形成する工程とを同時に行うことができる。
【０００８】
この発明に係る半導体装置の製造方法において、前記配線溝を形成する工程、前記堆積膜を形成する工程および前記堆積膜を除去する工程を、同一の処理室内で行うことができる。
【０００９】
この発明に係る半導体装置の製造方法において、前記低誘電率膜は、ポーラスＭＳＱ、ポーラスＨＳＱ、メチル基と水素基の両方を含有するハイブリッド膜、カーボンを主成分とするポーラス有機膜の何れかである。
【００１０】
【発明の実施の形態】
以下、図面を参照して本発明の実施の形態について説明する。図中、同一または相当する部分には同一の符号を付してその説明を簡略化ないし省略することがある。
【００１１】
実施の形態１．
図１を参照して、本発明の実施の形態１による半導体装置の製造方法について説明する。
図１は、本発明の実施の形態１による半導体装置の製造方法を説明するための図である。詳細には、図１（ａ）はポーラスＭＳＱ上にＳｉＣマスクを形成した後の状態を示す図であり、図１（ｂ）はポーラスＭＳＱ内に配線溝を形成した後の状態を示す図であり、図１（ｃ）は基板全面に堆積膜を形成した状態を示す図であり、図１（ｄ）は不要な堆積膜をスパッタエッチングした後の状態を示す図である。
【００１２】
先ず、図１（ａ）に示すように、シリコン基板等の基板１上に、複数の空孔２１を有する多孔性低誘電率膜（以下「ポーラスＬｏｗ−ｋ膜」という。）２としてポーラスＭＳＱを形成する。ポーラスＭＳＱ（２）の空孔２１の大きさは、数Å〜数百Å程度である。次に、ポーラスＭＳＱ（２）上に、ハードマスク３としてＳｉＣマスクを形成する。
【００１３】
次に、図１（ｂ）に示すように、ＳｉＣマスク（３）をマスクとしてポーラスＭＳＱ（２）をプラズマエッチングする。ここで、プラズマエッチング装置として、処理室（チャンバ）内に基板を載置する下部電極とそれに対向する上部電極とを備えた２周波励起平行平板型ＲＩＥ（reactive ion etching）装置を用いた（図示省略）。
ポーラスＭＳＱ（２）のプラズマエッチングについて詳述すると、先ず、上部電極に対向する下部電極上にシリコン基板１を配置する。シリコン基板１の温度は、熱交換器等を用いて約２５℃に保っておく。次に、チャンバ内にプロセスガスとしてＣ４Ｆ８／Ｎ２／Ａｒをそれぞれ１０／２２５／１４００ｓｃｃｍの流量で導入して、排気機構を用いてチャンバ内の圧力を１５０ｍＴｏｒｒに保つ。そして、上部電極に周波数６０ＭＨｚ、出力１０００ＷのＲＦ電力（高周波電力）を印加し、下部電極に周波数１３．５６ＭＨｚ、出力１４００ＷのＲＦ電力を印加すると、チャンバ内にプラズマ４が発生する。このプラズマ４でポーラスＭＳＱ（２）を異方性エッチングすることにより、ポーラスＭＳＱ（２）内に配線溝５が形成される。エッチング終了後は、配線溝５の側面が、ポーラスＭＳＱ（２）の空孔２１により凹凸形状となる。
なお、本発明において、配線溝は、導電体膜を埋め込むための溝又は孔を意味する。
【００１４】
次に、図１（ｃ）に示すように、同一のチャンバ内で、下部電極へのＲＦ電力印加のみを中止し、その他の条件は変えずに、プラズマ６を継続して生成する。この結果、Ｃ４Ｆ８から解離したＣｘＦｙ（ｘ＝１〜４，ｙ＝１〜８）分子が配線溝５の側面を含むシリコン基板１全面に堆積する。すなわち、配線溝５の側面を含むシリコン基板１全面に堆積膜７としてＣｘＦｙ膜を形成する。これにより、配線溝５の側面に露出する空孔２１が塞がれ、上記凹凸形状が緩和される。
なお、上記堆積膜７の組成、膜厚及びカバレージは、上部電極に印加するＲＦ電力、混合ガスＣ４Ｆ８／Ｎ２／Ａｒの流量比、プロセス圧力、基板温度等のパラメータを適宜調整することにより、最適化が可能である。
【００１５】
次に、図１（ｄ）に示すように、同一のチャンバ内で、下部電極にＲＦ電力を再度印加し、Ｃ４Ｆ８及びＮ２ガスの導入を中止し、その他の条件は変えずに、Ａｒプラズマ８を継続して生成する。このＡｒプラズマ８によるスパッタエッチングにより、配線溝５の側面以外に形成された不要な堆積膜７を除去する。
以上のようにして、ポーラスＭＳＱ（２）内に形成された配線溝５の側面にのみ堆積膜７が形成される。
【００１６】
その後、図示しないが、配線溝５内に導電体膜を形成する。詳細には、バリアメタル膜及びシード層を順次形成した後、Ｃｕ等の金属を堆積させ、不要な金属をＣＭＰにより除去して平坦化する。
【００１７】
以上説明したように、本実施の形態１では、ポーラスＭＳＱ（２）内に配線溝５を形成した後、この配線溝５の側面に堆積膜７を形成し、その後、配線溝５内に導電体膜を形成した。本実施の形態１によれば、導電体膜を形成する際、配線溝５側面の空孔２１は堆積膜７により覆われており、凹凸形状は緩和されている。従って、配線溝５内にカバレージ良く且つ高い密着性で導電体膜を形成することができる。
【００１８】
また、本実施の形態１では、堆積膜７をプラズマエッチング装置で形成している。すなわち、配線溝５の形成と、堆積膜７の形成と、不要な堆積膜７のスパッタ除去とを、エッチング装置の同一チャンバ内で連続して（Ｉｎ−ｓｉｔｕで）行っている。よって、半導体製造装置間で半導体装置を搬送する時間を大幅に短縮することができる。
【００１９】
なお、本実施の形態１では、ポーラスＬｏｗ−ｋ膜としてメチル基を含有するポーラスＭＳＱ（２）を用いたが、水素基を含有するポーラスＨＳＱ（ポーラスシリカ）、メチル基と水素基の両方を含有するハイブリッド膜、カーボンを主成分とするポーラス有機膜を用いてもよい。この場合も、上述した本実施の形態１で得られる効果と同様の効果が得られる。
【００２０】
また、本実施の形態１では、プラズマエッチング装置として２周波励起平行平板型ＲＩＥ装置を用いたが、マグネトロン型ＲＩＥ装置、誘導結合プラズマエッチング装置、ＥＣＲエッチング装置等を用いてもよい。
【００２１】
実施の形態２．
前述した実施の形態１では、ポーラスＭＳＱ（２）内に配線溝５を形成する工程と、配線溝５の側面を含むシリコン基板１全面に堆積膜７を形成する工程と、を別々に行った。本実施の形態２では、この２つの工程を同時に行うことを特徴とする。なお、それ以外の工程については、実施の形態１と同様であるため、簡単に説明する。
【００２２】
先ず、実施の形態１と同様の方法（図１（ａ）参照）で、シリコン基板１上にポーラスＭＳＱ（２）を形成し、その上にＳｉＣマスク３を形成する。
【００２３】
次に、図１（ｂ）に示す工程において、下記（ａ）〜（ｅ）に記載した改良のうち１つを行うか、複数を組み合わせて行う。
（ａ）シリコン基板１の温度をマイナス１０℃以下に下げる。
（ｂ）Ｃ４Ｆ８流量を数ｓｃｃｍ増大させる。
（ｃ）チャンバ内の圧力を数十ｍＴｏｒｒ増大させる。
（ｄ）下部電極に印加するＲＦ電力を数百Ｗ低下させる。
（ｅ）Ｎ２ガスの流量を数十ｓｃｃｍ低下させる。
【００２４】
以上のような方法により、ポーラスＭＳＱ（２）内に配線溝５が形成されると同時に、図１（ｃ）に示すように配線溝５の側面を含むシリコン基板１全面に堆積膜７が形成される。
【００２５】
次に、実施の形態１と同様の方法（図１（ｄ）参照）で、配線溝５の側面以外に形成された不要な堆積膜７を除去する。これにより、ポーラスＭＳＱ（２）内に形成された配線溝５の側面にのみ堆積膜７が形成される。
【００２６】
その後、配線溝５内に導電体膜を形成する。詳細には、バリアメタル及びシード層を順次形成した後、Ｃｕ等の金属を堆積させ、不要な金属をＣＭＰにより除去して平坦化する。
【００２７】
以上説明したように、本実施の形態２では、前述した実施の形態１において、図１（ｂ）に示す配線溝５の形成工程と、図１（ｃ）に示す堆積膜７の形成工程とを同時に行うこととした。従って、本実施の形態２によれば、実施の形態１で得られた効果に加えて、処理工程数を減らすことができ、スループットを向上させることができるという効果が得られる。
【００２８】
【発明の効果】
本発明によれば、多孔性の低誘電率膜に形成された配線溝内に、カバレージ良く且つ高い密着性で導電体膜を形成することができる。
【図面の簡単な説明】
【図１】本発明の実施の形態１による半導体装置の製造方法を説明するための断面図である。
【符号の説明】
１ 基板（シリコン基板）
２ 多孔性低誘電率膜（ポーラスＭＳＱ）
３ ハードマスク（ＳｉＣマスク）
４ プラズマ
５ 配線溝
６ プラズマ
７ 堆積膜（ＣｘＦｙ膜）
８ プラズマ（Ａｒプラズマ）
２１ 空孔[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a Cu wiring in a semiconductor integrated circuit, and more particularly to a method of forming a Cu wiring in a semiconductor integrated circuit using a low dielectric constant film (porous Low-k film) having holes as an interlayer insulating film.
[0002]
[Prior art]
With the miniaturization of semiconductor integrated circuits, the pitch between metal wires has been reduced, and signal delay of metal wires has become a serious problem.
In order to solve this problem, it is indispensable to reduce the wiring resistance by using Cu as a wiring material and to reduce the capacitance by using a low dielectric constant film as an interlayer insulating film. In particular, in a next-generation semiconductor integrated circuit, a so-called porous low dielectric constant film (hereinafter, referred to as a “porous Low-k film”) having a plurality of holes in an insulating film in order to further reduce interlayer capacitance. Is being studied (for example, see Patent Document 1).
[0003]
[Patent Document 1]
JP-A-9-298241 (page 2-3, FIG. 10-11)
[0004]
[Problems to be solved by the invention]
However, since the porous Low-k film has pores, unevenness is formed on the side surface of the wiring groove formed in the porous Low-k film. Even if a barrier metal film and a seed layer are formed in this state, there is a problem that they cannot be formed with good coverage.
Further, there is a problem that the barrier metal film and the seed layer are peeled off from the side surface of the wiring groove. That is, there is a problem that the adhesion between the side surface of the wiring groove and the barrier metal film and the seed layer is low.
[0005]
The present invention has been made to solve the above-mentioned conventional problems, and has as its object to form a conductor film with good coverage and high adhesion in a wiring groove formed in a porous low dielectric constant film. And
[0006]
[Means for solving the problem]
A method of manufacturing a semiconductor device according to the present invention includes a step of forming a porous low dielectric constant film on a substrate,
Forming a wiring groove in the low dielectric constant film by plasma etching;
In a plasma etching apparatus, a step of forming a deposited film on the entire surface of the substrate including side surfaces of the wiring grooves using plasma of a gas having a deposition property;
A step of removing the unnecessary deposited film formed other than the side surface of the wiring groove by sputter etching;
Forming a conductor film in the wiring groove;
It is characterized by including.
[0007]
In the method of manufacturing a semiconductor device according to the present invention, the step of forming the wiring groove and the step of forming the deposited film can be performed simultaneously.
[0008]
In the method of manufacturing a semiconductor device according to the present invention, the step of forming the wiring groove, the step of forming the deposited film, and the step of removing the deposited film can be performed in the same processing chamber.
[0009]
In the method for manufacturing a semiconductor device according to the present invention, the low dielectric constant film may be any one of porous MSQ, porous HSQ, a hybrid film containing both a methyl group and a hydrogen group, and a porous organic film containing carbon as a main component. is there.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts have the same reference characters allotted, and description thereof may be simplified or omitted.
[0011]
Embodiment 1 FIG.
With reference to FIG. 1, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described.
FIG. 1 is a view for explaining a method for manufacturing a semiconductor device according to the first embodiment of the present invention. In detail, FIG. 1A is a diagram showing a state after forming a SiC mask on the porous MSQ, and FIG. 1B is a diagram showing a state after forming a wiring groove in the porous MSQ. FIG. 1C is a view showing a state in which a deposited film is formed on the entire surface of the substrate, and FIG. 1D is a view showing a state after an unnecessary deposited film is sputter-etched.
[0012]
First, as shown in FIG. 1A, a porous low dielectric constant film (hereinafter, referred to as a “porous Low-k film”) 2 having a plurality of holes 21 is formed on a substrate 1 such as a silicon substrate. To form The size of the pores 21 of the porous MSQ (2) is about several to several hundreds of mm. Next, an SiC mask is formed as the hard mask 3 on the porous MSQ (2).
[0013]
Next, as shown in FIG. 1B, the porous MSQ (2) is plasma-etched using the SiC mask (3) as a mask. Here, as a plasma etching apparatus, a two-frequency excitation parallel plate type RIE (reactive ion etching) apparatus including a lower electrode for mounting a substrate in a processing chamber and an upper electrode facing the lower electrode was used (illustration shown). Omitted).
The plasma etching of the porous MSQ (2) will be described in detail. First, the silicon substrate 1 is disposed on the lower electrode facing the upper electrode. The temperature of the silicon substrate 1 is kept at about 25 ° C. using a heat exchanger or the like. Next, C 4 F 8 / N 2 / Ar is introduced as a process gas into the chamber at a flow rate of 10/225/1400 sccm, and the pressure in the chamber is maintained at 150 mTorr using an exhaust mechanism. When RF power (high-frequency power) having a frequency of 60 MHz and output of 1000 W is applied to the upper electrode and RF power having a frequency of 13.56 MHz and output of 1400 W is applied to the lower electrode, plasma 4 is generated in the chamber. By anisotropically etching the porous MSQ (2) with the plasma 4, a wiring groove 5 is formed in the porous MSQ (2). After the completion of the etching, the side surface of the wiring groove 5 becomes uneven due to the holes 21 of the porous MSQ (2).
In the present invention, the wiring groove means a groove or a hole for embedding a conductor film.
[0014]
Next, as shown in FIG. 1C, only the application of RF power to the lower electrode is stopped in the same chamber, and the plasma 6 is continuously generated without changing other conditions. As a result, CxFy (x = 1 to 4, y = 1 to 8) molecules dissociated from C 4 F 8 are deposited on the entire surface of the silicon substrate 1 including the side surface of the wiring groove 5. That is, a CxFy film is formed as the deposited film 7 on the entire surface of the silicon substrate 1 including the side surface of the wiring groove 5. As a result, the holes 21 exposed on the side surfaces of the wiring grooves 5 are closed, and the irregularities are alleviated.
The composition, thickness, and coverage of the deposited film 7 are appropriately adjusted by adjusting parameters such as RF power applied to the upper electrode, a flow ratio of the mixed gas C 4 F 8 / N 2 / Ar, process pressure, and substrate temperature. This allows optimization.
[0015]
Next, as shown in FIG. 1D, in the same chamber, RF power was again applied to the lower electrode, the introduction of C 4 F 8 and N 2 gas was stopped, and other conditions were not changed. , Ar plasma 8 is continuously generated. Unnecessary deposited film 7 formed on portions other than the side surfaces of wiring groove 5 is removed by the sputter etching using Ar plasma 8.
As described above, the deposition film 7 is formed only on the side surface of the wiring groove 5 formed in the porous MSQ (2).
[0016]
Thereafter, although not shown, a conductor film is formed in the wiring groove 5. Specifically, after a barrier metal film and a seed layer are sequentially formed, a metal such as Cu is deposited, and unnecessary metal is removed by CMP to planarize.
[0017]
As described above, in the first embodiment, after the wiring groove 5 is formed in the porous MSQ (2), the deposition film 7 is formed on the side surface of the wiring groove 5, and thereafter, the conductive film is formed in the wiring groove 5. A body membrane was formed. According to the first embodiment, when forming the conductor film, the holes 21 on the side surfaces of the wiring grooves 5 are covered with the deposited film 7, and the unevenness is reduced. Therefore, the conductor film can be formed in the wiring groove 5 with good coverage and high adhesion.
[0018]
In the first embodiment, the deposited film 7 is formed by a plasma etching apparatus. That is, the formation of the wiring groove 5, the formation of the deposition film 7, and the sputter removal of the unnecessary deposition film 7 are performed continuously (in-situ) in the same chamber of the etching apparatus. Therefore, the time for transporting the semiconductor device between the semiconductor manufacturing apparatuses can be significantly reduced.
[0019]
In the first embodiment, the porous MSQ (2) containing a methyl group is used as the porous Low-k film, but the porous HSQ (porous silica) containing a hydrogen group and both the methyl group and the hydrogen group are used. A hybrid film containing the same, or a porous organic film containing carbon as a main component may be used. In this case, the same effect as that obtained in the first embodiment can be obtained.
[0020]
In the first embodiment, a two-frequency excitation parallel plate RIE device is used as a plasma etching device, but a magnetron RIE device, an inductively coupled plasma etching device, an ECR etching device, or the like may be used.
[0021]
Embodiment 2 FIG.
In the first embodiment, the step of forming the wiring groove 5 in the porous MSQ (2) and the step of forming the deposition film 7 on the entire surface of the silicon substrate 1 including the side surface of the wiring groove 5 are separately performed. . The second embodiment is characterized in that these two steps are performed simultaneously. The other steps are the same as those in the first embodiment, and thus will be described briefly.
[0022]
First, a porous MSQ (2) is formed on a silicon substrate 1 by the same method as in the first embodiment (see FIG. 1A), and a SiC mask 3 is formed thereon.
[0023]
Next, in the step shown in FIG. 1B, one of the improvements described in the following (a) to (e) is performed or a plurality of improvements are performed.
(A) The temperature of the silicon substrate 1 is reduced to -10 ° C or lower.
(B) Increase the C 4 F 8 flow rate by several sccm.
(C) Increase the pressure in the chamber by several tens of mTorr.
(D) RF power applied to the lower electrode is reduced by several hundred watts.
(E) Decrease the flow rate of N 2 gas by several tens of sccm.
[0024]
By the above-described method, the wiring groove 5 is formed in the porous MSQ (2), and at the same time, the deposition film 7 is formed on the entire surface of the silicon substrate 1 including the side surface of the wiring groove 5 as shown in FIG. Is done.
[0025]
Next, by the same method as in the first embodiment (see FIG. 1D), the unnecessary deposited film 7 formed on portions other than the side surfaces of the wiring groove 5 is removed. Thus, the deposition film 7 is formed only on the side surfaces of the wiring grooves 5 formed in the porous MSQ (2).
[0026]
After that, a conductor film is formed in the wiring groove 5. Specifically, after a barrier metal and a seed layer are sequentially formed, a metal such as Cu is deposited, and unnecessary metal is removed by CMP to planarize.
[0027]
As described above, in the second embodiment, the process of forming the wiring groove 5 shown in FIG. 1B and the process of forming the deposited film 7 shown in FIG. At the same time. Therefore, according to the second embodiment, in addition to the effects obtained in the first embodiment, the effects that the number of processing steps can be reduced and the throughput can be improved can be obtained.
[0028]
【The invention's effect】
According to the present invention, a conductor film can be formed with good coverage and high adhesion in a wiring groove formed in a porous low dielectric constant film.
[Brief description of the drawings]
FIG. 1 is a sectional view for illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
[Explanation of symbols]
1 substrate (silicon substrate)
2 Porous low dielectric constant film (porous MSQ)
3 Hard mask (SiC mask)
4 plasma 5 wiring groove 6 plasma 7 deposited film (CxFy film)
8 Plasma (Ar plasma)
21 void

Claims (4)

基板上に多孔性の低誘電率膜を形成する工程と、
プラズマエッチングにより、前記低誘電率膜内に配線溝を形成する工程と、
プラズマエッチング装置において、堆積性を有するガスのプラズマを用いて、前記配線溝の側面を含む前記基板の全面に堆積膜を形成する工程と、
スパッタエッチングにより、前記配線溝の側面以外に形成された不要な前記堆積膜を除去する工程と、
前記配線溝内に導電体膜を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。Forming a porous low dielectric constant film on the substrate,
Forming a wiring groove in the low dielectric constant film by plasma etching;
In a plasma etching apparatus, a step of forming a deposited film on the entire surface of the substrate including side surfaces of the wiring grooves using plasma of a gas having a deposition property;
By sputter etching, a step of removing the unnecessary deposited film formed other than the side surface of the wiring groove,
Forming a conductor film in the wiring groove;
A method for manufacturing a semiconductor device, comprising: 請求項１に記載の製造方法において、
前記配線溝を形成する工程と、前記堆積膜を形成する工程とを同時に行うことを特徴とする半導体装置の製造方法。The method according to claim 1,
A method for manufacturing a semiconductor device, wherein the step of forming the wiring groove and the step of forming the deposited film are performed simultaneously. 請求項１又は２に記載の製造方法において、
前記配線溝を形成する工程、前記堆積膜を形成する工程および前記堆積膜を除去する工程を、同一の処理室内で行うことを特徴とする半導体装置の製造方法。The method according to claim 1 or 2,
A method for manufacturing a semiconductor device, wherein the step of forming the wiring groove, the step of forming the deposited film, and the step of removing the deposited film are performed in the same processing chamber. 請求項１から３の何れかに記載の製造方法において、
前記低誘電率膜は、ポーラスＭＳＱ、ポーラスＨＳＱ、メチル基と水素基の両方を含有するハイブリッド膜、カーボンを主成分とするポーラス有機膜の何れかであることを特徴とする半導体装置の製造方法。The method according to any one of claims 1 to 3,
The method for manufacturing a semiconductor device, wherein the low dielectric constant film is any one of a porous MSQ, a porous HSQ, a hybrid film containing both a methyl group and a hydrogen group, and a porous organic film containing carbon as a main component. .
JP2002372343A 2002-12-24 2002-12-24 Manufacturing method of semiconductor device Expired - Fee Related JP3717073B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009170901A (en) * 2008-01-14 2009-07-30 Toshiba Corp Protection of sidewall of trench by carbon-rich layer in semiconductor device

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KR100768474B1 (en) * 2005-09-27 2007-10-18 김홍배 Controller for Detecting Bubbles Generated within Electric Cooker
KR100847843B1 (en) * 2007-07-24 2008-07-23 주식회사 동부하이텍 Method for fabricating semiconductor device having porous low-k material

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009170901A (en) * 2008-01-14 2009-07-30 Toshiba Corp Protection of sidewall of trench by carbon-rich layer in semiconductor device
US8018023B2 (en) 2008-01-14 2011-09-13 Kabushiki Kaisha Toshiba Trench sidewall protection by a carbon-rich layer in a semiconductor device

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