KR20040057831A - Method for forming a gate of a semiconductor devise - Google Patents
Method for forming a gate of a semiconductor devise Download PDFInfo
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- KR20040057831A KR20040057831A KR1020020084651A KR20020084651A KR20040057831A KR 20040057831 A KR20040057831 A KR 20040057831A KR 1020020084651 A KR1020020084651 A KR 1020020084651A KR 20020084651 A KR20020084651 A KR 20020084651A KR 20040057831 A KR20040057831 A KR 20040057831A
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 43
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 14
- 230000003628 erosive effect Effects 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 반도체 소자의 게이트 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a gate of a semiconductor device.
반도체 소자가 고집적화됨에 따라, 게이트 라인의 선폭(line width) 및 라인간 스페이스(space)가 0.1㎛ 이하로 작아지면서 게이트 식각시 게이트 산화막에 대한 높은 식각선택비, 셀과 고립패턴(isolate pattern)에 대한 적정한 패턴사이즈(Critical Dimension; CD), 수직 프로파일(vertical profile)의 확보 등은 소자의 개발 및 수율확보 측면에서 큰 이슈(issue)가 되고 있다.As semiconductor devices become highly integrated, the line width and interline space of gate lines are reduced to 0.1 μm or less, resulting in high etching selectivity for gate oxides, gate cells, and isolation patterns during gate etching. Proper pattern size (CD) and securing a vertical profile have become a big issue in terms of device development and yield.
이미 잘 알려진 통상적인 게이트 형성방법은 도 1 내지 도 2에 도시된 바와 같다.Conventional gate formation methods that are well known are as shown in FIGS.
도 1을 참조하면, 반도체기판(2) 위에 20 ∼ 50Å 정도의 얇은 게이트 산화막(4)을 형성한 다음, 폴리실리콘막(6)을 2,500Å 정도 두께로 증착한다. 이 폴리실리콘막 위에 포토레지스트를 3,800Å 정도 도포한 다음, 노광 및 현상에 의해 게이트 라인을 한정하기 위한 포토레지스트 패턴(8)을 형성한다.Referring to FIG. 1, a thin gate oxide film 4 of about 20 to 50 kV is formed on a semiconductor substrate 2, and then a polysilicon film 6 is deposited to a thickness of about 2,500 kW. A photoresist is applied on the polysilicon film at about 3,800 GPa, and then a photoresist pattern 8 for defining a gate line by exposure and development is formed.
도 2를 참조하면, 상기 포토레지스트 패턴을 마스크로 사용하여 폴리실리콘막(6)을 식각하고, 포토레지스트 패턴을 제거함으로써 게이트 라인을 형성한다.Referring to FIG. 2, the polysilicon layer 6 is etched using the photoresist pattern as a mask to form a gate line by removing the photoresist pattern.
현재, 0.15㎛급의 소자에서는 게이트용 폴리실리콘막과 포토레지스트의 식각 선택비를 1:1 정도로 유지하여 식각이 가능하지만, 보다 미세한 0.1㎛급의 고집적 소자에서는 포토레지스트의 두께를 2,000 ∼ 2,500Å 정도로 낮추어야 한다. 이러한 포토레지스트의 두께로는 충분한 마스크의 역할을 하지 못한다. 즉, 도 3에 도시된 바와 같이, 폴리실리콘막(6)이 식각되는 동안 포토레지스트 패턴(8)이 식각되어 마스크로서의 역할을 충분히 수행할 수 없게 된다. 이로 인해 게이트 패턴의 가장자리가 식각되어 침식되는 현상이 일어나고,이는 소자의 특성을 저하시키는 악영향을 미친다.Currently, etching is possible by maintaining the etch selectivity of the gate polysilicon film and the photoresist at about 1: 1 in the 0.15 占 퐉 device, but the thickness of the photoresist is 2,000 to 2,500 k ohm in the fine 0.1 占 퐉 highly integrated device. Should be lowered to the extent. The thickness of this photoresist does not serve as a sufficient mask. That is, as shown in FIG. 3, the photoresist pattern 8 may be etched while the polysilicon film 6 is etched, and thus may not sufficiently perform the role of a mask. As a result, a phenomenon in which the edge of the gate pattern is etched and eroded occurs, which adversely affects the characteristics of the device.
본 발명이 이루고자 하는 기술적 과제는, 게이트 패턴 형성을 위한 식각공정에서 게이트의 측면이 침식되는 것을 방지하여 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 게이트 형성방법을 제공하는 것이다.An object of the present invention is to provide a method for forming a gate of a semiconductor device that can improve the reliability of the device by preventing the side of the gate from eroding in the etching process for forming the gate pattern.
도 1 내지 도 2는 종래의 게이트 형성방법을 도시한 단면도들이다.1 to 2 are cross-sectional views illustrating a conventional gate forming method.
도 3은 종래 게이트 형성방법의 문제점을 설명하기 위한 단면도이다.3 is a cross-sectional view illustrating a problem of a conventional gate forming method.
도 4 내지 도 7은 본 발명에 의한 반도체 소자의 게이트 형성방법을 설명하기 위한 단면도들이다.4 to 7 are cross-sectional views illustrating a method of forming a gate of a semiconductor device according to the present invention.
상기 과제를 이루기 위하여 본 발명에 의한 반도체 소자의 게이트 형성방법은, 반도체기판 위에 게이트산화막을 형성하는 단계와, 상기 게이트산화막 위에 폴리실리콘막을 형성하는 단계와, 상기 폴리실리콘막 위에 제1 포토레지스트 막과 제1 물질층을 차례로 형성하는 단계와, 상기 제1 물질층 위에, 제2 포토레지스트 막으로 이루어진 패턴을 형성하는 단계와, 상기 제2 포토레지스트 막을 이용하여 상기 제1 물질층을 식각하는 단계와, 상기 제1 물질층을 이용하여 상기 제1 포토레지스트 막을 식각하는 단계와, 상기 제1 포토레지스트 막을 이용하여 상기 폴리실리콘막을 식각하는 단계, 및 상기 제1 포토레지스트 막을 제거하는 단계를 포함한다.In order to achieve the above object, a method of forming a gate of a semiconductor device according to the present invention includes forming a gate oxide film on a semiconductor substrate, forming a polysilicon film on the gate oxide film, and forming a first photoresist film on the polysilicon film. And sequentially forming a first material layer, forming a pattern of a second photoresist film on the first material layer, and etching the first material layer by using the second photoresist film. And etching the first photoresist film using the first material layer, etching the polysilicon film using the first photoresist film, and removing the first photoresist film. .
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 4 내지 도 7은 본 발명에 의한 반도체 소자의 게이트 형성방법을 설명하기 위한 단면도들이다.4 to 7 are cross-sectional views illustrating a method of forming a gate of a semiconductor device according to the present invention.
도 4를 참조하면, 반도체기판(42) 위에, 예를 들어 20 ∼ 50Å 정도의 얇은 게이트 산화막(44)을 형성한 다음, 폴리실리콘막(46)을 2,500Å 정도 증착한다. 이 폴리실리콘막(46) 위에 제1 포토레지스트(48)를 4,000 ∼ 8,000Å 정도 도포한다. 다음, 제1 포토레지스트 막(48) 위에, 소정의 식각 공정에서 상기 포토레지스트 막과 식각 선택비를 갖는 물질, 예를 들어 저온 산화막(Low Temperature Oxide; LTO)(50)을 100℃ 이하의 온도에서 실란(SiH4) 가스와 N2O 가스를 이용하여 100 ∼ 150Å 정도의 두께로 증착한다. 다음, 상기 저온 산화막(50) 위에 게이트 패턴을 형성하기 위한 제2 포토레지스트(52)를 도포하고, 현상 및 노광공정을 실시하여 게이트 라인을 한정하기 위한 패턴을 형성한다. 이 제2 포토레지스트(52) 패턴은 0.1㎛급 라인을 패터닝하기 위한 정도의 두께, 즉 3,800Å 의 두께로 형성한다. 그리고, 상기 제1 포토레지스트(48)는 후속 공정에서 노광 및 현상, 즉 통상의 사진공정으로 패터닝되는 것이 아니라 상기 저온 산화막(50)을 마스크로 하여 식각되기 때문에, 게이트 패턴 형성을 위한 식각 공정에서 충분히 마스크 역할을 할 수 있는 정도의 두께, 예를 들어 4,000 ∼ 8,000Å 정도의 두께로 형성하는 것이 바람직하다.Referring to FIG. 4, a thin gate oxide film 44 of, for example, about 20 to 50 kV is formed on the semiconductor substrate 42, and then the polysilicon film 46 is deposited to about 2,500 kV. The first photoresist 48 is coated on the polysilicon film 46 by about 4,000 to 8,000 GPa. Next, on the first photoresist film 48, a material having an etch selectivity with respect to the photoresist film in a predetermined etching process, for example, a low temperature oxide film (LTO) 50, has a temperature of 100 ° C. or less. Using a silane (SiH 4 ) gas and N 2 O gas to deposit a thickness of about 100 ~ 150 ∼. Next, a second photoresist 52 for forming a gate pattern is coated on the low temperature oxide film 50, and a pattern for defining a gate line is formed by performing development and exposure processes. This second photoresist 52 pattern is formed to a thickness of about 3,800 mm 3, which is about the thickness for patterning a 0.1 µm class line. In addition, since the first photoresist 48 is etched using the low temperature oxide film 50 as a mask instead of being exposed and developed in a subsequent process, that is, in a normal photo process, in the etching process for forming a gate pattern. It is preferable to form in thickness of the grade which can fully serve as a mask, for example, thickness of about 4,000-8,000 Pa.
도 5를 참조하면, 상기 제2 포토레지스트 패턴을 마스크로 사용하여 저온 산화막(50)을 식각한다. 이 때, 식각 가스로는 CHF3/CF4/C2F6/Ar 가스를 사용하고, 30±10mT의 압력에서 식각한다. 다음에, 식각된 상기 저온 산화막을 마스크로 사용하여 제1 포토레지스트 막(48)을 식각하는데, O2/N2/HBr을 식각 가스로 하여 10±5mT의 압력에서 실시한다.Referring to FIG. 5, the low temperature oxide film 50 is etched using the second photoresist pattern as a mask. At this time, as an etching gas, CHF 3 / CF 4 / C 2 F 6 / Ar gas is used, and etching is performed at a pressure of 30 ± 10 mT. Next, the first photoresist film 48 is etched using the etched low-temperature oxide film as a mask, and is subjected to a pressure of 10 ± 5 mT with O 2 / N 2 / HBr as an etching gas.
도 6을 참조하면, CF4/C2F6가스를 이용하여 자연산화막을 제거하는데, 이 때 상기 저온 산화막도 함께 제거된다. 다음에, 제1 포토레지스트(48) 패턴을 식각 마스크로, Cl2/HBr/Cf4/HeO2등의 가스를 식각 가스로 사용하여 폴리실리콘막(46)을 식각한다. 상기 제1 포토레지스트(48) 패턴은 5,000 ∼ 8,000Å 정도로 두껍게 형성되었기 때문에 폴리실리콘막(46)이 완전히 식각되는 동안 충분히 마스크 역할을 수행할 수 있다.Referring to FIG. 6, the native oxide layer is removed using a CF 4 / C 2 F 6 gas, at which time the low temperature oxide layer is also removed. Next, the polysilicon film 46 is etched using the first photoresist 48 pattern as an etching mask and a gas such as Cl 2 / HBr / Cf 4 / HeO 2 as an etching gas. Since the first photoresist 48 pattern is formed to be about 5,000 to 8,000 Å thick, the first photoresist 48 may serve as a mask while the polysilicon layer 46 is completely etched.
도 7을 참조하면, 제1 포토레지스트 패턴을 제거한 상태를 도시한 것으로, 종래와는 달리 폴리실리콘막(46)의 침식이 일어나지 않아 수직한 프로파일을 갖는 게이트 라인이 형성되었음을 알 수 있다.Referring to FIG. 7, a state in which the first photoresist pattern is removed is illustrated. Unlike the related art, erosion of the polysilicon layer 46 does not occur, and thus a gate line having a vertical profile is formed.
한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능하다.On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.
상술한 본 발명에 의한 반도체 소자의 게이트 형성방법에 따르면, 게이트용 폴리실리콘막을 식각하기 위한 포토레지스트 위에 식각 선택비를 갖는 물질층 패턴을 형성하고, 이를 마스크로 하여 포토레지스트 패턴을 형성한다. 따라서, 0.1㎛ 이하의 디자인 룰을 갖는 고집적 소자를 제조할 때에도 상기 포토레지스트의 두께를, 게이트 식각에 필요한 충분한 두께로 형성할 수 있다. 따라서, 게이트 패턴의 침식을 방지하여 소자의 신뢰성을 확보할 수 있고, 포토레지스트와 게이트 물질의 식각 선택비에 대한 여유를 확보할 수 있으므로 공정 마진(margin)을 향상시킬 수 있다.According to the gate forming method of a semiconductor device according to the present invention described above, a material layer pattern having an etch selectivity is formed on a photoresist for etching a gate polysilicon film, and a photoresist pattern is formed using the mask as a mask. Therefore, even when manufacturing a highly integrated device having a design rule of 0.1 μm or less, the thickness of the photoresist can be formed to a sufficient thickness required for gate etching. Therefore, the device may be secured by preventing erosion of the gate pattern, and a margin for etching selectivity between the photoresist and the gate material may be secured, thereby improving process margins.
Claims (4)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020084651A KR20040057831A (en) | 2002-12-26 | 2002-12-26 | Method for forming a gate of a semiconductor devise |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1020020084651A KR20040057831A (en) | 2002-12-26 | 2002-12-26 | Method for forming a gate of a semiconductor devise |
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| KR20040057831A true KR20040057831A (en) | 2004-07-02 |
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| KR1020020084651A KR20040057831A (en) | 2002-12-26 | 2002-12-26 | Method for forming a gate of a semiconductor devise |
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2002
- 2002-12-26 KR KR1020020084651A patent/KR20040057831A/en not_active Application Discontinuation
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