KR20040057818A - Method for fabricating capacitor of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a capacitor of a semiconductor device is provided to effectively enhance the capacitance by increasing the area of a storage node using an isolation layer of line/spacer shape. CONSTITUTION: A nitride layer is formed on a semiconductor substrate(21). A polysilicon layer is formed to open a capacitor forming region. The first oxide spacer is formed at sidewalls of the open region of the polysilicon layer. The first oxide layer with different etch rate is formed to form a contact hole between the first oxide spacers. The second oxide spacer is formed at sidewalls of the open region of the first oxide layer. A nitride hard mask of line/space shape is formed at the capacitor forming region by etching the nitride layer. An isolation layer(31) of line/space shape is formed by etching the substrate using the nitride hard mask. Then, a dielectric film(33) and an upper electrode(34a) are sequentially formed.

Description

Method for fabricating capacitor of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the fabrication of semiconductor devices, and more particularly, to semiconductors capable of efficiently increasing capacitance by increasing the area of storage nodes in a three-dimensional form by using two line / spacer type device isolation lines. It relates to a method of forming a capacitor of the device.

In recent years, as semiconductor devices have been highly integrated and cell sizes have been reduced, it has become difficult to sufficiently secure a capacitance proportional to the surface area of a storage electrode. In particular, in the DRAM device in which the unit cell is composed of one MOS transistor and a capacitor, it is important to increase the capacitance while reducing the area of the capacitor which occupies a large area of the chip in order to increase the capacitance. It becomes a factor.

Thus, the capacitor represented by (ε _o × ε _r × A) / T (where, ε _o is the vacuum dielectric constant, ε _r is the dielectric constant of the dielectric film, A is the area of the capacitor, and T is the thickness of the dielectric film) In order to increase the capacitance C, a material having a high dielectric constant was used as the dielectric film, a thin dielectric film was formed, or the surface area of the storage electrode was increased.

Hereinafter, a capacitor forming process of a semiconductor device of the prior art will be described with reference to the accompanying drawings.

1A to 1E are cross-sectional views of a process for forming a capacitor of a semiconductor device of the prior art.

The planar capacitor structure made using the impurity diffusion region of the silicon substrate, which has been used previously, cannot be applied as the area of the memory device is reduced, and has been changed into a three-dimensional structure in order to increase the storage capacity of the information charge.

However, the capacitor formation method and structure are simple, and the planar capacitor form is used in many devices such as 18M merged planar DRAM in logic (PDL).

In the conventional manufacturing process of the capacitor having a planar structure, as shown in FIG. 1A, a photoresist pattern for forming a nitride film 12 on a semiconductor substrate 11 and defining an active region by a photolithography process is shown. (13) is formed.

As shown in FIG. 1B, the semiconductor substrate 11 exposing the photoresist pattern 13 as a mask is selectively etched to form a shallow trench isolation (STI) region.

Subsequently, as shown in FIG. 1C, the device isolation layer 14 is formed in the STI region.

As shown in FIG. 1D, the dielectric material layer 15, the capacitor electrode material layer 16, and the photoresist pattern 17 for defining the capacitor formation region are formed.

Subsequently, as shown in FIG. 1E, the exposed dielectric material layer 15 and the capacitor electrode material layer 16 are selectively removed using the photoresist pattern 17 as a mask to form a planar capacitor.

That is, substrates used as storage electrodes are isolated from each other through a STI (Sallow Trench Isolation) process, and the storage electrodes thus formed can be patterned only in a limited area.

However, such a capacitor formation process of the semiconductor device of the prior art has the following problems.

Since the substrates used as the storage electrodes are isolated from each other through the STI (Sallow Trench Isolation) process, the storage electrodes can be patterned only in a limited area, so that it is difficult to increase the electrode formation area to increase the amount of information charge.

The present invention has been made to solve such a problem of the capacitor formation process of the semiconductor device of the prior art, by using two line / spacer type device isolation line to increase the area of the storage node in a three-dimensional form to increase the capacitance It is an object of the present invention to provide a method for forming a capacitor of a semiconductor device so that it can be efficiently improved.

1A to 1E are cross-sectional views of a process for forming a capacitor of a semiconductor device of the prior art.

2A to 2Q are cross-sectional views of a process for forming a capacitor of a semiconductor device according to the present invention.

-Explanation of symbols for the main parts of the drawing-

21. Semiconductor Substrate 22. Nitride Film

23. Polysilicon Film 24. First Photoresist Pattern Layer

25a. First Oxide Spacer 26. First Oxide Film

27. Second photoresist pattern layer 29a. Secondary oxide spacer

30. Nitride hard mask 31. Device isolation layer

32. Third Photoresist Pattern Layer 33. Dielectric Layer

34. Material layer for forming upper electrode 35. Fourth photoresist pattern layer

34a. Capacitor Top Electrode

According to another aspect of the present invention, there is provided a method of forming a capacitor of a semiconductor device, the method including: forming a nitride film on a semiconductor substrate and forming a polysilicon film to open a capacitor formation region; Forming a first oxide spacer on an open region side of the polysilicon film; Forming a first oxide film having an etch rate different from that of the first oxide spacer such that a contact hole is formed between the first oxide spacer; Forming a second oxide spacer on an open region side of the first oxide film; Etching the nitride layer using the spacers as a mask to form a nitride hard mask layer in a line / space form in a capacitor formation region; Etching the substrate to a predetermined depth using the nitride hard mask to form a device isolation layer; A method of forming a capacitor in a semiconductor device, the method comprising removing isolation lines in a capacitor formation region, forming a dielectric layer, and forming a capacitor upper electrode.

That is, according to the method of forming a capacitor of a semiconductor device according to the present invention, a device isolation layer having a three-dimensional shape using two line / spacer shapes formed in parallel in each other in the capacitor formation region, that is, first and second oxide spacers. As the surface area of the storage node of the capacitor is formed along the device isolation layer having a three-dimensional shape, the surface area of the lower electrode of the storage node, that is, the capacitor is increased in the same area, thereby improving the capacitance. Accordingly, it is possible to enable high integration of the semiconductor device.

A preferred embodiment of the method for forming a capacitor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2Q are cross-sectional views of a process for forming a capacitor of a semiconductor device according to the present invention.

The present invention increases the pattern of the storage electrode during the device isolation process by using two lines / spacers in the planner type, and the oxide film formed on the storage node during the field oxidation process is used for the photo process. It can be easily removed through.

First, as shown in FIG. 2A, an SiO ₂ film, that is, an initial oxide film, is grown on a semiconductor substrate 21 by a thermal oxidation process, and then a nitride film 22 is formed thereon. In this case, the nitride layer 22 serves as a hard mask when the semiconductor substrate 21 is later etched to form trenches.

The first photoresist pattern layer is formed on the nitride layer 22 to form a polysilicon layer 23 in consideration of a hard mask effect and to define a portion serving as a storage electrode of a planar capacitor. Form (24).

After the process of forming the first photoresist pattern layer 24 is performed, as shown in FIG. 2B, the polysilicon film 23 is selectively etched using the first photoresist pattern layer 24 as a mask. The polysilicon film 23 is patterned. In addition, an oxide film 25 having a low wet etching rate, that is, an HDP and an HLD oxide layer is deposited on the entire surface of the patterned polysilicon layer 23, and then, as illustrated in FIG. 2C, the polysilicon layer patterned by an etch back process. (23) A first oxide spacer 25a is formed on the side of the pattern.

Subsequently, as illustrated in FIG. 2D, a first oxide layer 26 is formed on the entire surface where the first oxide spacer 25a is formed to form another spacer in an isolated line in a subsequent process.

The first oxide layer 26 may be formed of a material having a different etching rate from that of the first oxide spacer 25a, that is, any one or more of PE-TEOS, FSG, SOG, USG, and BPSG having a high wet etching rate. Selected and patterned polysilicon film 23 is deposited to be thick enough to cover is formed.

As shown in FIG. 2E, the first oxide layer 26 is planarized by a chemical mechanical polishing (CMP) process, a photoresist is applied thereon, and an exposure and development process is performed to separate the isolation line, that is, the second The second photoresist pattern 27 is formed to form contact holes for forming oxide spacers.

Subsequently, as shown in FIG. 2F, the first oxide layer 26 is etched using the second photoresist pattern 27 as a mask until the lower nitride layer 22 enters, thereby forming contact holes. The second oxide spacer forming material 29 is deposited with a material having a different etching rate from that of the first oxide layer 26, that is, an oxide film having a low wet etching rate, that is, an HDP or HLD oxide layer.

Thereafter, as illustrated in FIG. 2G, a chemical mechanical polishing process is performed to expose the upper portion of the polysilicon film 23 to form the second oxide spacer 29a.

2H, polysilicon remaining on both sides of the first oxide film 26 and the first oxide spacer 25a remaining between the first and second oxide spacers 25a and 29a by an etch back process. The film 23 is etched back to be selectively removed, whereby a portion of the surface of the lower nitride film 22 is exposed. In addition, the polysilicon layer 23 may be removed using a wet etching process using sulfuric acid such as a strong acid in consideration of the nitride layer 22 of the underlying layer to pattern a portion to be formed as a hard mask.

Subsequently, as illustrated in FIG. 2I, the nitride layer 22 is patterned through a hard mask made of the first and second oxide spacers 25a and 29a to serve as a storage electrode of the planar capacitor. A nitride hard mask 30 is defined to define the portion.

Thereafter, as illustrated in FIG. 2J, the semiconductor substrate 21 is etched using the nitride hard mask 30.

At this time, the storage electrodes of the capacitor are also defined and form trenches in a line / space form.

As shown in FIG. 2K, a gap isolation oxide film is buried by an STI process to form a device isolation layer 31. As illustrated in FIG. 2L, the nitride hard mask 30 is removed, and then device isolation is performed. The third photoresist pattern 32 is formed to open a portion where the capacitor is formed on the layered product.

Subsequently, as illustrated in FIG. 2M, the exposed gap fill oxide film is removed using the third photoresist pattern 32 as a mask.

Thereafter, as shown in FIG. 2N, a dielectric layer 33 having an oxide-nitride-oxide (ONO) structure is formed, and a material layer 34 for forming a capacitor upper electrode is formed on the entire surface thereof, as shown in FIG. 2O. .

As shown in FIG. 2P, a fourth photoresist pattern 35 is formed on the material layer for forming the capacitor upper electrode, and as shown in FIG. 2Q, an upper part of the capacitor exposed by the fourth photoresist pattern. The electrode forming material layer 34 is selectively removed to form the capacitor upper electrode 34a.

This process results in more area and more capacity than previous planar capacitors.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

The capacitor forming method of the semiconductor device according to the present invention described above has the following effects.

Lines and spaces, that is, three-dimensional isolation lines are formed so as not to be affected by the device isolation layer, and the storage electrodes and three-dimensional shapes can be used to increase the electrode area, thereby effectively increasing capacitance. You can.

Claims (4)

Forming a nitride film on the semiconductor substrate and forming a polysilicon film to open the capacitor formation region; Forming a first oxide spacer on an open region side of the polysilicon film; Forming a first oxide film having an etch rate different from that of the first oxide spacer such that a contact hole is formed between the first oxide spacer; Forming a second oxide spacer on an open region side of the first oxide film; Etching the nitride layer using the spacers as a mask to form a nitride hard mask layer in a line / space form in a capacitor formation region; Etching the substrate to a predetermined depth using the nitride hard mask to form a device isolation layer; Removing the isolation lines in the capacitor formation region and depositing a dielectric layer and forming a capacitor upper electrode. The method of claim 1, wherein the dielectric layer is formed in an oxide-nitride-oxide (ONO) structure. The method of claim 1, wherein the first oxide spacer formed on the side of the open region of the polysilicon film is formed using an HDP or HLD oxide film having a lower wet etching rate than that of the first oxide film. The capacitor of claim 1, wherein the first oxide layer is formed by selecting any one or more of PE-TEOS, FSG, SOG, USG, and BPSG having a higher wet etching rate than that of the first oxide spacer. Way.