KR20040056253A - high speed interrupt unit for PLC - Google Patents

Abstract

PURPOSE: A high speed interrupt unit provided with an input and output function for use in a programmable logic controller is provided to realize one chip by implementing operation of interrupt circuit with VHDL(very high speed integrated circuits hardware description language). CONSTITUTION: A high speed interrupt unit provided with an input and output function for use in a programmable logic controller includes an input signal use selection switch, an input voltage direction selection switch, an input voltage setting switch, an input unit, a bus driver and a control processor. The control processor utilizes the inner memory area to transmit the CPU unit and the status. The CPU unit records the WY00 region of address 0X00 which is referred by the interrupt unit and consisted of an interrupt acknowledge(IA), an interrupt end bit(IEB) and an enable/disable(ED) data. The interrupt unit records the WX10 region of the address 0X10 which is referred by the CPU unit and are composed of a rising/falling edge(UD), a channel No., response(RSP) and an interrupt available(AV) data. And, the interrupt unit records the WX11 region of the address 0X11 which is referred by the CPU unit and consisted of the c0 to cn-1 channels of current input status of data.

Description

High speed interrupt unit for PLC with I / O function

The present invention relates to a high-speed interrupt unit for a PLC having an input / output function, and more particularly, an interrupt unit capable of performing an input / output function as a high-speed interrupt unit, which is one of a special unit such as a programmable logic controller (PLC), in particular, a POSFA PLC. It is about.

In general, the interrupt unit transmits a signal for an external special situation to the PLC side, and when the interrupt input signal requiring a high-speed response is input to the PLC momentarily, a interrupt program is executed. A special unit of PLC that pauses and executes a prepared interrupt routine first. That is, the interrupt unit may be referred to as an emergency unit for a situation that must be solved in advance of a system operation currently being performed, such as an abnormal operation or a dangerous moment of an external device. Therefore, the interrupt unit must always operate without being reliably down and must respond quickly to the input signal within a given time.

Interrupt units for conventional PLCs, in particular POSFA PLCs, were designed based on an 8-bit microprocessor and the entire operation was implemented in software.

Therefore, when the microprocessor of the PLC stops operating, it may not serve as an interrupt unit. This is because the algorithm implementation of the system software running on the microprocessor depends on the developer's ability, and thus the performance is not guaranteed to guarantee the stability of the operation, and it is used as a special unit using some of the functions of the general purpose developed microprocessor. This may cause the original interrupt unit not to function due to lighting.

For this reason, foreign-made interrupt units such as Mitsubishi may be composed of pure logic without a microprocessor, that is, only hardware configuration. However, since they were only used for interrupt units only, separate input / output modules were provided for input / output. It was inconvenient to do it, and it was difficult to debug because the operation status of the internal data could not be easily known, and the interrupt input voltage was fixed at 12V or 24V, and any of the rising edge or the falling edge was also detected in the detection of the interrupt signal. Fixed on one side, it was inconvenient to accept signals from various interrupt sources.

In addition, even in the case of the input / output module, even if all channels provided in advance were not used, all unnecessary channels had to be opened, and thus there was no simple on / off function.

The present invention has been made to solve the above problems, VHDL (Very High) by the pure hardware logic without a microprocessor to solve the instability problem that the conventional interrupt unit for PLC is implemented by using a microprocessor Speed integrated circuits can be implemented in one chip using Hardware Description Language, easily display the internal data state for debugging, select the interrupt input voltage for signal processing from various interrupt sources, and Rising edge or polling edge can be selected for detection, and I / O function that can be used as input / output (I / O) unit by selecting necessary input / output channels in addition to basic function of interrupt unit High speed interrupt for PL Intended to provide a unit.

1 is a basic block diagram of an interrupt unit.

2 is a view showing a development board embodiment according to the present invention.

3 is an input terminal and a wiring diagram.

4 is a timing diagram.

5 is a diagram illustrating an entire routine in which an interrupt unit operates while exchanging data with a CPU.

6 is a VHDL internal structure diagram.

7 is a VHDL external circuit diagram.

8A and 8B are exemplary views of actual embodiments of the present invention.

9 is a diagram for describing a method of transmitting an input / output signal.

In order to achieve the above technical problem, the interrupt unit of the present invention is implemented in one chip using VHDL, and solves problems of the existing interrupt unit and adds new functions.

That is, in the interrupt unit for the high speed PLC,

An input signal use selection switch unit (DIP_SW1) for selecting a function of each interrupt input channel between enable and disable;

An input voltage direction selector switch (DIP_SW2) for selecting the edge direction of each interrupt signal;

An input voltage setting switch unit (Jump1) for selecting the level of each interrupt signal voltage;

An input unit for receiving input of a predetermined number n of channels,

A bus driver section for address, data, IRQ1, etc. to be connected to the compact PLC backplane,

Consists of a control processing unit implemented in one chip using VHDL,

In particular, the control processing unit uses an internal storage for transferring status with the CPU unit,

The WY00 area at address 0x00 is written by the CPU unit and referenced by the interrupt unit, and is composed of Interrupt Acknowledge (IA), Interrupt End Bit (IEB), and Enable / Disable (ED) data.

The WX10 area at address 0x10 is written by the interrupt unit and referenced by the CPU unit, and is composed of rising / falling edge (U / D), Channel NO., RSP (Response), and AV (Interrupt Available) data.

The WX11 area at address 0x11 is written by the interrupt unit and referenced by the CPU unit, and is composed of data of the channel current input state of c0 to c n-1,

In the control processing unit,

Determining whether an external interrupt signal is generated when the ED is 1;

If the external interrupt signal did not occur, go to the step of checking the queue, if the external interrupt signal has occurred, check the Int Busy again to see if there is an interrupt currently running,

If there is an interrupt currently being executed, it is entered into the queue, and if there is no interrupt currently being executed, the internal parameter (WX10) is updated by updating the rising / falling edge (U / D), Channel NO., RSP (Response) and AV (Interrupt Available). Setting an internal parameter (WX11) by updating the input state, generating an interrupt signal and detecting the CPU IA (WY00);

If IA of the CPU is detected, setting Int Busy = 1, AV = 0, Int = 0, and detecting the IEB confirming the termination of the interrupt;

If IEB is detected, set RSP = 1, Int Busy = 0, search for queue,

If there is no interruption in the queue, the process returns to the external interrupt detection step, and if there is an interruption in the queue, the process returns to the step of searching for Int Busy after processing the interrupt having the highest priority. It is a high-speed interrupt unit for PLC equipped with an input / output function.

In addition, according to an embodiment, the switch unit (DIP_SW3) for selecting the LED display mode for debugging the internal data operation state,

According to the selection state of the selection switch unit (DIP_SW3) further comprises an LED unit for displaying the internal data state,

The LED display mode is 2 bits (m1, m0), and the input / output function is configured to display interrupt operation when (m1, m0) = 00, WY00 state if 01, WX10 state if 10, and WX11 state if 11. It is a high speed interrupt unit for PLC.

Hereinafter, an interrupt unit of the present invention having the above configuration will be described in more detail with reference to the accompanying drawings.

The apparatus of the present invention is an interrupt unit developed for a PLC, in particular a POSFA PLC, the basic operation of which is designed based on the basic concept of the existing POSFA interrupt unit, and includes an improved content to perform more advanced functions. have. The core part of the internal circuit is realized by VHDL in ALTERA's PLD to realize one-chip and high speed operation and stabilization of operation.

1 is a basic block diagram of an interrupt unit, and FIG. 2 is a diagram showing a development board embodiment according to the present invention.

Here, the input is n-channel, for example, 16-channel, and cut off the internal circuit and the external input signal through a port coupler (photo coupler). The input signal is selectable by the switch unit, for example, jumper Jump1, so that the input voltage level can be selected. For example, 12V and 24V can be selected and inputted. Of course, the polarity of input voltage can be used as common GND or common VCC.

In addition, it is possible to select and use a desired channel among the 16 channels through the switch unit DIP_SW1, as well as to select the edge direction of the interrupt signal through the other switch unit DIP_SW2. In addition, according to an embodiment of the present invention, all of the predetermined number of LEDs, for example, four states of display, are enabled through the LED, so that the state of the input and the state of the internal memory can be checked.

The internal operation of the interrupt unit according to the operation of the jump and dip switch is shown in Table 1 below.

switch Contents Jump1 Input Voltage Selection Jump [Connection: 12V, Short: 24V] Jump2 Used to download ALTERA chip programs [Up: 3.3V, Down: 5V] Jump3 Select / WR signal cable when Compact PLC Back Plane is connected [Up: C10 connection, bottom: B16 connection] Dip_SW1 Interrupt Channel Enable / Disable Selection Switch [Up: Disable, Down: Enable] Dip_SW2 Interrupt Signal Edge Direction Selector Switch [Operation at Up: Falling Edge, Down: Rising Edge] Dip_SW3 LED Display Mode selection switch (m1, m0 from left to right) m1, m0 = 00: Interrupt operation 01: WY00 state 10: WX10 state 11: WX11 state

Hereinafter, each theme will be described in more detail.

◈ Input

The following operation is performed and implemented in VHDL.

Input channel: n channels, for example 16 channels

Input voltage: selectable voltage level, for example, 12V and 24V

[Input select jumper (Jump1) On: 12V (8mA), Off: 24V (17mA)]

Input channel: Input channel order and external wiring method are the same as in FIG.

Input signal method selection DIP switch (DIP_SW2)

→ UP: Operation at Falling Edge

→ Down: Operation at Rising Edge

Input Enable / Disable Selection DIP Switch (DIP_SW1)

→ UP: Disable

→ Down: Enable

Executes an interrupt operation for the channel selected for Enable. On the other hand, regardless of Enable / Disable selection, the input signal is displayed as 1 (input high) or 0 (input low) in WX11. In this case, set the LED status selection DIP switch (DIP_SW3) to 11 and check the input status with the LED.

◈ Interrupt Priority

When several interrupts occur during execution or at the same time, interrupts with higher priority are processed according to interrupt priority, and it is also implemented in VHDL.

I.e. (highest priority) 0> 1> 2> ......> 15 (lowest)

Is in order.

For example,

If input 3 during interrupt 5,-> execute 3 times after finishing 5 times.

If you input 6 during interrupt 5, it executes 6 times after finishing 5 times.

If you input 6, 7, 1, 2 during interrupt 5,-> 5 times and then 1, 2, 6, 7

Is configured to.

◈ Interrupt output

□ Interrupt output: It is output by IRQ1 and it is a low active signal.

INT signal is composed of Open Collector circuit, so that several interrupt units can be used at the same time.

□ LED display: According to the state of switch part (DIP_SW3), status output as shown in Table 2 below (Low Active).

m1, m0 LED status 0, 0 Interrupt processing status indication, operating independently for each channel, turned on when the interrupt input signal comes in, and turned off when the interrupt routine ends. 0, 1 WY00 internal value is displayed. 1: on, 0: off 1, 0 The WX10 internal value is displayed. 1: on, 0: off 1, 1 The WX11 internal value is displayed. 1: on, 0: off

◈ I / O signal transfer method with CPU unit

The CPU unit communicates the interrupt status by using an internal storage location as shown in Table 3 and Fig. 9 below. The ID of the interrupt unit is set to 0x0C by default, and like other modules, it can be confirmed through a specific address, for example, 0xFE address.

domain Address Contents WY00 0x00 The PLC CPU writes and the Interrupt Unit is referred to. ED : Enable Disable Interrupt Unit Total Operation Enable Indication When the interrupt is cleared to zero during interrupt operation, all other interrupt signals that are waiting are cleared. IEB : Interrupt End Bit Signal indicating the end of interrupt operation IA : Interrupt Acknowledge Signal indicating that the interrupt signal has been recognized WX10 0x10 U / D : Up Rising / Down Falling Edge Signal indicating whether input signal is Rising or Falling Edge [0: Rising Edge, 1: Falling Edge] Channel No. : Input channel number display Ch. 0: 0x0 ... Ch. 15: ~ 0xF RSP : When ResponseCPU notifies the end of internal interrupt routine by IEB signal, it is set to 1 immediately. AV : Set to 1 immediately after Available interrupt. When using multiple interrupt units, it is used to indicate the interrupted unit. WX11 0x11 The interrupt unit writes and is referenced by the PLC CPU. c0 to c15: It indicates the current input status for each channel. If it is High, it is 1 and if it is low, it is 0.

◈ Timing Diagram

The overall timing diagram of the interrupt unit is shown in FIG.

When an external interrupt signal occurs, the interrupt unit internally generates an interrupt BUSY signal. After the interrupt operation is completed, the interrupt BUSY disappears. In the interrupt unit, when the values of WX10, WX11, and WY00 are determined as shown in Table 3, the entire operation is completed for one interrupt.

The interrupt unit performs the interrupt operation only when the third bit ED value of WY00 is 1, and when the ED value is 0 when the interrupt of another channel is waiting, all waiting values are deleted.

The entire routine in which the interrupt unit operates while exchanging data with the CPU is illustrated in FIG. 5.

◈ Circuit diagram

The internal core operation of the interrupt unit is written in the VHDL language and is made on one chip using ALTERA 3256.

The inside of the VHDL has the structure as shown in FIG. 6, and there is an intqueue.VHD that queues and sorts the interrupt signal in the innermost so that services can be performed according to priority, and inteschd manages the entire schedule of interrupts. .VHD is in the next layer. Cpuif.VHD is in charge of the interface with the external circuit, and the top.gdf circuit is finally configured as shown in FIG.

8A and 8B are exemplary views of front and rear boards according to an embodiment embodied by the present invention.

According to the interrupt unit of the present invention as described above, it is possible to fundamentally solve the problem of the conventional interrupt unit for PLC, selectively use only a desired channel, and can be used as an input / output unit in addition to the interrupt unit, and furthermore, The operation status can be easily identified and debugged by LED, and the whole operation core part of the internal circuit is realized in VHDL (Very High Speed Integrated Circuits Hardware Description Language) in ALTERA's PLD to realize one chip. There is a very significant effect of realizing the operation and stabilization of the operation.

Claims (2)

In the high-speed interrupt unit for PLC equipped with input / output function, An input signal use selection switch unit (DIP_SW1) for selecting a function of each interrupt input channel between enable and disable; An input voltage direction selector switch (DIP_SW2) for selecting the edge direction of each interrupt signal; An input voltage setting switch unit (Jump1) for selecting the level of each interrupt signal voltage; An input unit for receiving input of a predetermined number n of channels, A bus driver section for address, data, IRQ1, etc. to be connected to the compact PLC backplane, Consists of a control processing unit implemented in one chip using VHDL, In particular, the control processing unit uses an internal storage for transferring status with the CPU unit, The WY00 area at address 0x00 is written by the CPU unit and referenced by the interrupt unit, and is composed of Interrupt Acknowledge (IA), Interrupt End Bit (IEB), and Enable / Disable (ED) data. The WX10 area at address 0x10 is recorded by the interrupt unit and referenced by the CPU unit, and is composed of rising / falling edge (U / D), channel NO., RSP (response), and AV (InterruptAvailable) data. The WX11 area at address 0x11 is written by the interrupt unit and referenced by the CPU unit, and is composed of data of the channel current input state of c0 to c n-1, In the control processing unit, Determining whether an external interrupt signal is generated when the ED is 1; If the external interrupt signal did not occur, go to the step of checking the queue, if the external interrupt signal has occurred, check the Int Busy again to see if there is an interrupt currently running, If there is an interrupt currently being executed, it is entered into the queue, and if there is no interrupt currently being executed, the internal parameter (WX10) is updated by updating the rising / falling edge (U / D), Channel NO., RSP (Response) and AV (Interrupt Available). Setting an internal parameter (WX11) by updating the input state, generating an interrupt signal and detecting the CPU IA (WY00); If IA of the CPU is detected, setting Int Busy = 1, AV = 0, Int = 0, and detecting the IEB confirming the termination of the interrupt; If IEB is detected, set RSP = 1, Int Busy = 0, search for queue, If there is no interruption in the queue, the process returns to the external interrupt detection step, and if there is an interruption in the queue, the process returns to the step of searching for Int Busy after processing the interrupt having the highest priority. PLC high-speed interrupt unit with input / output function. The method of claim 1, further comprising: a switch unit (DIP_SW3) for selecting an LED display mode for debugging an internal data operation state; According to the selection state of the selection switch unit (DIP_SW3) further comprises an LED unit for displaying the internal data state, The LED display mode is 2 bits (m1, m0), and the input / output function is configured to display interrupt operation when (m1, m0) = 00, WY00 state if 01, WX10 state if 10, and WX11 state if 11. High speed interrupt unit for PLC.