KR950000439Y1 - Auto-setting apparatus of serial communicational port - Google Patents

Abstract

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Description

Automatic setting device of serial communication port

1 is an automatic setting apparatus of a serial communication port according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10: control unit 20: configuration register

40: input / output interface 50: interrupt switching unit

The present invention relates to an automatic setting device of a serial communication port. More specifically, in a computer system in which a serial communication port is provided using a single input / output interface, the input / output address is automatically set so that the serial communication port and the external communication device do not collide. And an automatic setting device of a serial communication port for setting interrupt priority.

In general, computer systems including a personal computer (PC) have a serial communication port for communicating with an external device.

For reference, the priority of I / O address and interrupt signal of the serial communication port provided by IBM (International Business Machine) PC compatible models is shown in [Table-1] below.

TABLE 1

These two serial communication ports are sometimes supported through a single input / output interface to make the computer system more economical.

In this case, in order for the user to use the serial communication port correctly, it is necessary to confirm whether the serial communication port is properly designated through the input / output address, and then confirm that the priority of the interrupt signal required from the serial communication port is correctly specified. .

Such verification can be done by the user directly viewing a manual generated by a computer manufacturer and operating a jumper or a dual in-line package (DIP) switch as instructed by the manual.

However, the conventional serial communication port is inconvenient for the user to be familiar with the functions of the computer. In other words, serial communication port does not work when user designates wrong serial communication port and serial communication port is disconnected when user uses external communication device such as modem using same input / output change as serial communication port. If not enabled, both the serial communication port and the external communication device do not operate, and in severe cases, the serial communication port or the external communication device may be electrically damaged.

Accordingly, an object of the present invention is to solve the above-mentioned disadvantages, and when the external communication device is used in a computer system in which a serial communication port is provided using one input / output interface, the serial communication port and the external communication device are used. It is to provide an automatic setting device of a serial communication port that automatically assigns and sets an input / output address and an interrupt priority so as not to conflict.

In order to achieve the above object, a configuration of the present invention includes a control unit for enabling or disabling a buffer and an input / output interface according to a value of a configuration register in which an information signal for serial communication port setting is stored by a central processing unit; ; A configuration register for storing information signals relating to serial communication port settings output from the central processing unit when the address is designated by the control unit; A data buffer for transmitting a data signal between the system bus and the input / output interface according to the chip selection signal of the controller; An input / output interface that is enabled according to a chip select signal of the controller and transmits and receives a data signal; The interrupt switching unit switches the priority of the interrupt request signal of the input / output interface according to the interrupt selection signal of the control unit. With reference to the accompanying drawings, a preferred embodiment for easily carrying out this invention by the above-described configuration will be described in detail.

Figure is an automatic setting device for a serial communication port according to an embodiment of the present invention.

As shown in the figure, in the configuration of the automatic setting device of the serial communication port according to the embodiment of the present invention, the address signal input terminals A0 to A9 are connected to the address bus ADDR of the system and the control bus CONT of the system. ) Is a control unit 10 to which an address enable signal input terminal AEN and an input / output write signal input terminal IOW are connected, and a register enable signal output terminal (/ CON) of the control unit 10. An input terminal is connected to EN) and the data bus DATA of the system, and an output terminal is inputted to the configuration register 20 connected to the input terminals Q0 and Q1 of the controller 10, and to the data bus DATA of the system. Terminal is connected and chip select signal output terminal (/ CS) of control unit 10 A data buffer 30 having a gate terminal G connected to the BUF, and an input terminal connected to an output terminal of the data buffer 30, and the chip select signal output terminal / (CS of the control unit 10). The input / output interface 40 having the chip select input terminal CS connected to the BUF, the interrupt request signal output terminal IRQ of the input / output interface 40, and the interrupt selection signal output terminal (/ INT3) of the controller 10; It consists of an interrupt switch section 50 connected to the input terminal 4).

In the embodiment of the present invention, although the 8250 chip (Asynchronous Communication Element, ACE) of Intel Inc. is used as the input / output interface 40, the technical scope of the present invention is not limited thereto.

The configuration of the control unit 10 includes a PAL (Programmable Array Logic) having the following logical expression.

/ CON EN = / AEN * A9 * / A8 * / A7 * A6 * / A5 * A4 * / A3 * / IOW / INT3 4 = / Q1 * Q0

/ CS BUF = / AEN * A9 * A8 * A7 * A6 * A5 * A4 * A3 * / Q1 * Q0 + / AEN * A9 * / A8 * A7 * A6 * A5 * A4 * A3 * / Q1 * / Q0

In addition, the configuration of the configuration register 20, the inverter (I21) connected to the input terminal of the reset signal line (RESET) of the system, and the clear terminal (CLR) is connected to the output terminal of the inverter (I21), respectively, Input terminals D are respectively connected to the lower bit signal lines D0 and D1 of the data bus DATA, clock terminals are respectively connected to the register enable signal output terminal / CON EN of the controller 10, and the controller 10 D-type flip-flops 21 and 22 having output terminals Q connected to the input terminals Q0 and Q1, respectively.

In the embodiment of the present invention, as the above-described D-type flip-flops 21 and 22, a 74LS74 chip (Dual D-Type Positive-Edge-Triggered Flips-Flops with Preset and Clear) is used. Not limited to this, a negative edge triggered flip-flop may be used.

In addition, the configuration of the interrupt switching unit 50 described above includes the interrupt selection signal output terminal (/ INT3) of the control unit 10. Inverter I51 to which input terminal 4 is connected, and interrupt selection signal output terminal (/ INT3) of control unit 10; 4) the gate terminal is connected to the gate terminal connected to the output terminal of the buffer gate (G51) and the input terminal of the interrupt request signal output terminal (IRQ) of the input and output interface (IRQ) of the input and output interface (40), A buffer gate G52 having an input terminal coupled to the interrupt request signal output terminal IRQ of FIG.

The operation of the automatic setting device of the serial communication port according to the embodiment of the present invention by the above configuration is as follows.

When the power is applied, the automatic setting device of the serial communication port according to the embodiment of the present invention operates.

After the automatic setting device of the serial communication port is operated, if the reset signal RESET is output from the system bus to the configuration register 20 at the beginning of operation, the reset signal RESET is an inverter of the configuration register 20. After being inverted by (I21), it is input to the clear terminal CL of the D flip-flops 21 and 22. Therefore, the D-type flip-flops 21 and 22 of the configuration register 21 are cleared so that the configuration register 20 initially has an OH value.

When a signal having an OH value is input from the configuration register 20 to the input terminals Q0 and Q1 of the control unit 10, the control unit 10 generates a low register enable signal (/ CON). EN) to the configuration register 20, and the interrupt selection signal (/ INT3) in the low state. 4) is output to the interrupt switcher 50, and the chip selection signal (/ CS in the low state) is output. BUF) is output to the buffer 30 and the input / output interface 40. Therefore, operations of the configuration register 20, the buffer 30, and the input / output interface 40 are disabled.

The central processing unit (not shown) executes a Basic Input Output System (BIOS) program at initial booting to check whether an external communication device such as a modem occupies the first serial communication port.

When the first serial communication port is not occupied by an external communication device, the central processing unit outputs a value of 1H through the system data bus DATA, and then outputs a value of 2D0H to 2D7H through the system address bus ADDR. The output causes the control unit 10 to store the 1H value in the configuration register 20.

When the output of the configuration register 20 is 1H, when the 3F8H to 3FFH address is designated through the address bus ADDR of the system, the chip select signal (/ CS in the high state from the control unit 10 is set. By outputting the BUF, the buffer 30 and the input / output interface 40 are enabled. In addition, when the output of the configuration register 20 is 1H, the interrupt selection signal (/ INT3) in the high state is transmitted from the control unit 10. 4) is outputted, the buffer gate G52 of the interrupt switching unit 50 is turned on, and the fourth interrupt signal line INT 4 is connected to the interrupt request signal output terminal IRQ of the input / output interface 40.

Therefore, the input / output interface 40 is designated as the first serial communication port.

However, when the first serial communication port is occupied by an external communication device, the central processing unit continuously checks whether the second serial communication port is occupied by an external communication device.

When the second serial communication port is not occupied by an external communication device, the CPU outputs a value of 2H through the system data bus DATA, and then outputs a value of 2D0H to 2D7H through the system address bus ADDR. The output causes the control unit 10 to store the 2H value in the configuration register 20.

When the output of the configuration register 20 is 2H, when the 2F8H to 2FFH address is designated through the address bus ADDR of the system, the high-chip chip select signal (/ CS) is received from the controller 10. By outputting the BUF, the buffer 30 and the input / output interface 40 are enabled. In addition, when the output of the configuration register 20 is 2H, the interrupt selection signal (/ INT3 in the low state from the control unit 10 is performed. 4) is output, the buffer gate G51 of the interrupt switching unit 50 is turned on so that the third interrupt signal line INT 3 is connected to the interrupt request signal output terminal IRQ of the input / output interface 40.

Therefore, the input / output interface 40 is designated as the second serial communication port.

However, when both the first serial communication port and the second serial communication port are occupied by an external device, the central processing unit outputs a 0H or 3H value through the system data bus DATA, and then the system address bus ADDR. By outputting a value of 2D0H to 2D7H through), the control unit 10 allows 0H or 3H, a value, to be assigned to the configuration register 20.

When a signal having a value of 3H from the configuration register 20 is input to the input terminals Q0 and Q1 of the control unit 10, the control unit 10 generates a low state register enable signal (/ CON). EN) to the configuration register 20, and the interrupt selection signal (/ INT3) in the low state. 4) is output to the interrupt switch section 50, and the chip select signal (/ CS in the low state) is output. BUF) is output to the buffer 30 and the input / output force interface 40. Therefore, operations of the configuration register 20, the buffer 30, and the input / output interface 40 are disabled.

As described above, in the embodiment therein, when an external communication device is used in a computer system in which a serial communication port is provided by using one input / output interface, the input / output address is automatically avoided so that the serial communication port and the external communication device do not collide. And by assigning and setting the priority of the interrupt, it is possible to provide an automatic setting device of the serial communication port having the effect that the user can easily use the serial communication port and an external communication device even if the user does not have much computer knowledge. This effect of the invention can be used in the field of serial communication port of a computer.

Claims (3)

A control unit (10) for enabling or disabling a buffer and an input / output interface in accordance with a value of a configuration register in which an information signal for serial communication port setting is stored by a central processing unit; A configuration register 20 for storing information signals relating to serial communication port settings output from the central processing unit when its address is designated by the control unit 10; A data buffer 30 which is enabled by the chip select signal of the controller 20 and transmits a data signal between the system bus and the input / output interface; An input / output interface 40 which is enabled by the chip select signal of the controller 10 and transmits and receives a data signal; And an interrupt switching unit (50) for switching the priority of the interrupt request signal of the input thrust interface (40) according to the interrupt selection signal of the control unit (10). 2. The interrupt selection unit 50 according to claim 1, wherein the interrupt switching unit 50 includes the interrupt selection signal line (/ INT3) of the control unit 10. An inverter I51 connected to an input terminal at 4); Interrupt selection signal line (/ INT3) of the controller 10 A buffer gate G51 connected to a gate terminal 4 and an input terminal connected to the interrupt request signal line IRQ of the input / output interface 40; And a buffer gate (G52) connected to an output terminal of the inverter (I51) and having an input terminal connected to the interrupt request signal line (IRQ) of the input / output interface (40). 2. The inverter according to claim 1, wherein the configuration register (20) comprises: an inverter (I21) having an input terminal connected to a reset signal line (RESET) of a system bus; The clear terminals are respectively connected to the output of the inverter I21, the input terminals D are connected to the two bit signal lines of the data bus DATA of the system, respectively, and the register enable signal lines (/ CON) of the controller 10 are connected. Automatic setting device of the serial communication port, characterized in that consisting of the D-type flip-flop (21, 22) having a clock terminal connected to each EN) and an output terminal (Q) connected to the input terminal of the control unit 10, respectively.