KR19990030145U - Integrated PIU BOARD of System Main Board - Google Patents

Abstract

The present invention relates to the main board of the system, in particular, in a system equipped with a plurality of main boards that perform each function, a system main board to enable the integration of the common CPU and peripheral devices into one board Of the integrated CPU board.

Conventionally, the CPU and its peripheral devices are separately installed for each motherboard that performs a specific function. This is because when the circuit becomes complicated and the CPU types are different, integrated work is impossible when developing or modifying the firmware. There is a troublesome work.

The present invention integrates a common CPU and peripheral devices into a single board in a system equipped with several main boards that perform each function, thereby simplifying circuits and integrating them easily in firmware development or modification. Enable work.

Description

Integrated PIU BOARD of System Main Board

The present invention relates to the main board of the system, in particular, in a system equipped with a plurality of main boards that perform each function, a system main board to enable the integration of the common CPU and peripheral devices into one board Of the integrated CPU board.

In general, when a motherboard that performs a specific function is operated, the CPU (Central Processing Unit) operates according to the firmware programmed in the ROM. The program counter in the CPU designates the start address of the ROM. A board-specific operation is performed by reading an instruction stored in a storage location corresponding to the start address, and performing a board-specific operation. The data generated during the operation of the board is stored and used in RAM (Random Access Memory). On the other hand, if the firmware program stored in ROM causes a problem in the board operation due to a bug, the program should be debugged or the firmware program will be upgraded and replaced with a new program. In this case, after removing the ROM mounted on the board, attach it to a separate fusing device such as a ROM writer, and then transfer the changed firmware to the ROM writer, and the ROM writer fuses the ROM to the ROM writer. Program.

On the other hand, in the case of a system that performs several functions at the same time by mounting a plurality of main boards to perform a specific function as described above, as shown in Figure 1, the main board 20a to 20c performing each function Each of the main boards 20a to 20c is equipped with a CPU for controlling the functions of the main boards 20a to 20c and peripheral devices 10a to 10c, respectively. It works by sending and receiving messages.

As described above, in the related art, a CPU and a peripheral device are separately installed for each motherboard that performs a specific function, and when the circuit becomes complicated and the type of the CPU is different, the firmware is developed or modified. There is a troublesome work due to the inability to work.

The present invention has been made in view of the above problems, and in a system equipped with several main boards performing each function, the circuit and the peripheral devices that are commonly installed are integrated into one board, thereby simplifying the circuit. At the same time, an object of the present invention is to provide an integrated CPU board of a system main board that enables easy integration in firmware development or modification.

In order to achieve the above object, the present invention provides a main board of a system having a plurality of devices that perform a plurality of functions, the main board comprising: a CPU for controlling a plurality of devices provided in the main board; An EPROM for storing firmware data for operating the CPU; An RS232C connector for transmitting / receiving data through the serial port of another device under the control of the CPU; An SRAM for storing data generated when an integrated CPU board is operated under the control of the CPU; An SIO for interfacing input / output of serial data with another device through the RS232C connector according to the control of the CPU; A PLD for implementing logic logic necessary for additional operations of the CPU integrated board; A clock generator for generating and outputting a clock for operating the CPU and the peripheral device; And a display unit for displaying an operation state of the CPU integrated board.

1 is a conceptual diagram of a conventional system.

2 is an integrated CPU board mounted on a system main board according to an embodiment of the present invention.

Example of mounting.

Figure 3 is a detailed block diagram of the integrated CPU board of the system main board according to the present invention.

4 is a flowchart of signals input and output between the main board and the integrated CPU board.

Explanation of symbols on the main parts of the drawings

10a to 10c: CPU (Central Processing Unit) and peripheral device

20a to 20c: Main board 30: Integrated CPU board

31: CPU

32: EPROM (Erasable Programmable Read Only Melory)

33: Static Random Access Memory (SRAM)

34: clock generator 35: PLD (Programmable Logic Device)

36: SIO (Serial Input / Output interface)

37: display unit 38: RS232C connector

40: main board

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Integrated CPU board of the system main board according to the present invention is shown in Figure 3, the CPU 31, EPROM (Erasable Programmable Read Only Melory; 32), SRAM (Static Random Access Memory; 33), clock A generator 34, a programmable logic device (PLD) 35, a serial input / output interface (SIO) 36, a display unit 37, and an RS232C connector 38 are provided.

The CPU 31 controls a plurality of devices provided in the main board 40 in the main board 40 of the system having a plurality of devices performing a plurality of functions. The EPROM 32 stores firmware (FirmWare) data for operating the CPU 31. The SRAM 33 stores data generated when the integrated CPU board 30 operates under the control of the CPU 31. The clock generator 34 generates and outputs a clock for operating the CPU 31 and the peripheral device. The PLD 35 implements logic logic necessary for additional operation of the integrated CPU board 30. The SIO 36 interfaces the input / output of serial data with another device via the RS232C connector 38 under the control of the CPU 31. The display unit 37 displays an operation state of the integrated CPU board 30. The RS232C connector 38 transmits / receives data through the serial port of another device under the control of the CPU 31.

When described in detail with reference to the accompanying drawings, the operation of the present invention configured as described above are as follows.

First, according to an embodiment of the present invention, the integrated CPU board 30 is mounted at a predetermined position of the system main board 40, as shown in FIG. 2, and when the system operates, the CPU 31 ) Operates according to the firmware programmed in the EPROM 32. The program counter inside the CPU 31 designates the start address of the EPROM 32, and the CPU 31 corresponds to the EPROM corresponding to the start address. By starting the operation by reading the command stored in the (32), and performs a system-specific operation, a number of devices that implement a number of functions mounted on the main board 40 is implemented in the integrated CPU board (30) It operates under the control of the CPU 31, and data generated during the operation of the system is stored and used in the SRAM 33. At this time, the signals to and from the integrated CPU board 30 and the main board 40 are all signals related to the CPU, that is, data, address, and direct memory access (DMA) signals, as shown in FIG. And a chip select signal CS, an interrupt signal, and the like for controlling a plurality of devices mounted on the main board 40 and the like. At this time, the CPU 31 or other peripheral devices operate on the basis of the clock applied from the clock generator 34, and transmit data with other external devices through the SIO 36 and the RS232C connector 38. Can send / receive In addition, the operation state of the integrated CPU board 30 can be confirmed through the display unit 37.

On the other hand, when developing a device that performs a specific function on the motherboard 40, since the firmware for operating the CPU 31 is already programmed, it can be omitted, and only the firmware of the part related to the motherboard 40 is developed Will be added. In addition, in the related art, each main board 40 is provided with a CPU 31 and a peripheral device, and each main board 40 has a different memory table, but the integrated CPU board 30 according to the present invention is provided. ) Simplifies the hardware of the system itself and makes it easy to maintain, since the common parts of all boards' memory tables are unified.

As described above, the present invention integrates a common CPU and peripheral devices into a single board in a system equipped with a plurality of main boards that perform respective functions, thereby simplifying a circuit and at the same time developing or modifying firmware. In this way, it is possible to integrate easily.

Claims (1)

A main board (40) of a system having a plurality of devices for performing a plurality of functions, comprising: a CPU (31) for controlling a plurality of devices provided in the main board (40); An EPROM (32) for storing firmware data for operating the CPU (31); An RS232C connector 38 for transmitting / receiving data through the serial port of another device, under the control of the CPU 31; An SRAM 33 for storing data generated when an integrated CPU board is operated under the control of the CPU 31; An SIO (36) for interfacing input / output of serial data with another device through the RS232C connector (38) under the control of the CPU (31); A PLD 35 for implementing logic logic necessary for additional operation of the CPU integrated board; A clock generator 34 for generating and outputting a clock for operating the CPU 31 and a peripheral device; Integrated CPU board of the system main board comprising a display unit (37) for displaying the operation status of the CPU integrated board.